Matthias Koefferlein
6f7cca81fb
Updated test data
2020-05-23 13:19:52 +02:00
Matthias Koefferlein
c682cc85d0
Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests.
2020-05-21 23:59:30 +02:00
Matthias Koefferlein
fccd78a222
Fixed #448 and updated test data
2019-12-15 10:37:51 +01:00
Matthias Koefferlein
64d32c1ae9
LVS tests are more stable because of sorting of terminal names before assigning them (no hash order)
2019-07-24 21:23:19 +02:00
Matthias Koefferlein
c7e883cdb2
SPICE reader now assigned net names as pin names.
2019-07-12 19:00:27 +02:00
Matthias Koefferlein
a47190f3ab
Write short versions of LVS and L2N DB by default.
2019-07-12 17:43:43 +02:00
Matthias Koefferlein
cef96902ad
Boundary for circuits, reverted automatic generation of global pins
...
- global pins have been generated for device cells too and lead
to implicit pins which may not be desired. The original problem
was how to make abstract circuits comparable. This has to be
solved differently.
- Circuit boundaries are good for displaying the boxes for
abstract circuits
2019-07-09 19:55:48 +02:00
Matthias Koefferlein
95a1e38fe3
WIP: better reproducablility for .lvsdb layer names, updated tests.
2019-07-07 19:39:00 +02:00
Matthias Koefferlein
0595ec2e0f
WIP: one more test for LVS
2019-07-06 09:08:32 +02:00