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31 Commits

Author SHA1 Message Date
Matthias Koefferlein d248bfddf3 Updating copyright to new year 2024-01-01 17:06:23 +01:00
Matthias Koefferlein 579f5ffca4 Doc updates 2023-09-25 23:33:15 +02:00
Matthias Koefferlein 83aaca4485 WIP: unit tests for GSI binding of Region#net 2023-01-19 22:11:40 +01:00
Matthias Koefferlein a85dbd3d31 Updating copyright notice to 2023 2023-01-01 22:27:22 +01:00
Matthias Koefferlein 10456516db Updated copyright to 2022, preparations for 0.27.6 (was delayed due to code signing certificate issues) 2022-01-04 21:20:04 +01:00
Matthias Koefferlein 1c8442f485 Fixed #807 - now supporting incremental connect and clear_connections in DRC/LVS 2021-05-24 21:56:57 +02:00
Matthias Koefferlein 9f295523e4 explicit net joining - preparations 2021-03-27 21:56:53 +01:00
Matthias Koefferlein 7d4310d343 Updated copyright to 2021 2021-01-05 22:57:48 +01:00
Matthias Koefferlein 880b9904cf WIP Netlist probing will deliver an instantiation path now. 2020-06-14 22:04:16 +02:00
Matthias Köfferlein 2d0a9418f9
Implemented #579 (perimeter_only mode for antenna check) (#582) 
* WIP: added basic feature and tests.

* WIP: provide tests are GSI binding of new antenna check

* Fixed issue #579 (perimeter_only mode for antenna check)

* Updated DRC doc for 'perimeter_only'
 2020-06-05 10:55:07 +02:00
Matthias Köfferlein 6601d472bf
Implemented #570 (perimeter included in antenna check) (#572) 
* First implementation of the perimeter factor for antenna check, unit tests.

* Bugfix and unit tests for GSI binding of new antenna check version.

* DRC integration of perimeter-enabled antenna check.

* Enhanced DRC doc for antenna rule
 2020-05-30 21:45:48 +02:00
Matthias Koefferlein b84a9df2da Persisting texts now for .l2n format 2020-05-22 00:58:46 +02:00
Matthias Koefferlein 2933e0b2e1 Unit tests fixed after #526 update. 2020-03-28 22:31:19 +01:00
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein 6a47437702 Updated test data. 2019-12-18 17:28:46 +01:00
Matthias Koefferlein a05345945d Updated test data 2019-12-15 09:46:40 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein 3dd2978d1f Added RBA tests for LayoutToNetlist#build_nets and LayoutToNetlist#build_all_nets 2019-06-12 23:32:10 +02:00
Matthias Koefferlein c684633dd6 Some enhancements for netlist extraction and writer 
* Spice writer can now be configure to skip the debug
  comments
* < and > are allowed chars in spice names now
* global net names have second prio over labels now
 2019-05-31 00:11:28 +02:00
Matthias Koefferlein 7e62d04ffe Fixed rba unit tests. 2019-05-27 21:00:02 +02:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein 261fb027fd GSI binding of antenna check function + tests. 2019-03-02 00:38:51 +01:00
Matthias Koefferlein c90f7e4af9 Introduced perimeter parameters for MOS3/MOS4 2019-02-02 01:29:28 +01:00
Matthias Koefferlein f83e1dae43 Refactoring, some bugfixes, GSI bindings for L2N methods. 2019-01-20 23:12:27 +01:00
Matthias Koefferlein 9fa5618034 Added test for device combination. 2019-01-08 23:49:12 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein fb4048d317 Added RBA tests for four-terminal MOS extraction plus global nets. 2019-01-08 00:17:58 +01:00
Matthias Koefferlein 64c2548ab8 WIP: first steps towards global nets. 2019-01-06 15:28:40 +01:00
Matthias Koefferlein ad6d9b5715 WIP: provide a less memory intensive way to deliver shapes from nets. 2019-01-04 17:41:09 +01:00
Matthias Koefferlein 9c607d7663 Added a first version of the layout to netlist extraction feature 
The main entry point is RBA::LayoutToNetlist which is the
GSI binding for the layout to netlist extractor. For a first
impression about the abilities of this extractor see the
Ruby tests in testdata/ruby/dbLayoutToNetlist.rb.

The framework itself consists of many classes, specifically

- RBA::Netlist for the netlist representation
- RBA::DeviceClass and superclasses (e.g. RBA::DeviceClassResistor and
  RBA::DeviceClassMOS3Transistor) for the description of devices.
- RBA::DeviceExtractor and superclasses (i.e. RBA::DeviceExtractorMOS3Transistor or
  the generic RBA::GenericDeviceExtractor) for the implementation of the
  device extraction.
- RBA::Connectivity for the description of inter- and intra-layer connections.
 2018-12-30 22:43:56 +01:00