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Merge pull request #1305 from KLayout/issue-1304

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Fixed issue #1304 (terminal order for MOS devices)
This commit is contained in:
Matthias Köfferlein
2023-03-04 19:32:46 +01:00
committed by GitHub
parent f413635deb 28883ee383
commit 2facc75807
129 changed files with 6082 additions and 5579 deletions
Download Patch File Download Diff File Expand all files Collapse all files
testdata/algo/lvs_test1_au.lvsdb.1
Vendored
+4 -4
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
testdata/algo/lvs_test1_au.lvsdb.2
Vendored
+4 -4
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
testdata/algo/lvs_test1b_au.lvsdb.1
Vendored
+4 -4
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
testdata/algo/lvs_test1b_au.lvsdb.2
Vendored
+4 -4
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
testdata/algo/lvs_test2_au.lvsdb.1
Vendored
+35 -35
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference
testdata/algo/lvs_test2_au.lvsdb.2
Vendored
+35 -35
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference
testdata/algo/lvs_test2b_au.lvsdb.1
Vendored
+35 -35
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference
testdata/algo/lvs_test2b_au.lvsdb.2
Vendored
+35 -35
View File
@@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference
testdata/algo/nreader1.cir
Vendored
+1 -1
View File
@@ -13,5 +13,5 @@ R$2 3 1 7650
* device instance $3 4.665,0.335 RES
R$3 3 2 2670
* device instance $4 1.765,7.485 HVPMOS
M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
.ENDS TOP
testdata/algo/nreader17.cir
Vendored
+15
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@@ -0,0 +1,15 @@
* recursive expansion of parametrized subcircuits
Xsub1a a b c sub1 w=1.5 l=0.15
Xsub1b a b c sub1 w=3.0 l=0.25
.subckt sub1 n1 n2 n3 w=1.0 l=0.5
Xsub2a n1 n2 n3 sub2 w l m=1
Xsub2b n1 n2 n3 sub2 w l m=2
.ends
.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0
Mnmos n1 n2 n3 n1 nmos w=w l=l m=m
.ends
testdata/algo/nreader17b.cir
Vendored
+24
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@@ -0,0 +1,24 @@
* recursive expansion of parametrized subcircuits
.param w1 1.5 w2 {w1*2}
.param l1 0.15 l2 'l1+0.1'
Xsub1a a b c sub1 w=w1 l=l1
Xsub1b a b c sub1 w=w2 l=l2
.subckt sub1 n1 n2 n3 w l
* declares w and l parameters instead of nodes:
w = 1.0
l = 1.0
.param w1 = w
.param l1 = l
Xsub2a n1 n2 n3 sub2 w=w1 l=l1 m=1
.param w2 "w+0.0" l2 l*(0.5+0.5)
Xsub2b n1 n2 n3 sub2 w=w2 l=l2 m=2
.ends
.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0
Mnmos n1 n2 n3 n1 nmos w=w l=l m=m
.ends
testdata/algo/nreader18.cir
Vendored
+59
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@@ -0,0 +1,59 @@
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/inverter1_generated_sky130_fd_pr/inverter1/inverter1.sch
**.subckt inverter1 I Q VDD VSS
*.ipin I
*.opin Q
*.iopin VDD
*.iopin VSS
XXpmos Q I VDD VDD pmos4_standard w=1.5u l=150n nf=4
XXnmos Q I VSS VSS nmos4_standard w=1.5u l=150n nf=4
XXDUMMY0 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2
XXDUMMY1 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2
XXDUMMY2 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2
XXDUMMY3 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2
**.ends
* expanding symbol: BAG_prim/pmos4_standard/pmos4_standard.sym # of pins=4
** sym_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sym
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sch
.subckt pmos4_standard D G S B model w l nf
w=100n
l=18n
nf=4
model=pmos4_standard
spiceprefix=X
*.iopin D
*.iopin G
*.iopin S
*.iopin B
MM1 D G S B sky130_fd_pr__pfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u'
+ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W'
+ sa=0 sb=0 sd=0 mult=1 m=nf
.ends
* expanding symbol: BAG_prim/nmos4_standard/nmos4_standard.sym # of pins=4
** sym_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sym
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sch
.subckt nmos4_standard D G S B model w l nf
w=100n
l=18n
nf=4
model=nmos4_standard
spiceprefix=X
*.iopin D
*.iopin G
*.iopin S
*.iopin B
MM1 D G S B sky130_fd_pr__nfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u'
+ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W'
+ sa=0 sb=0 sd=0 mult=1 m=nf
.ends
.end
testdata/algo/nreader1b.cir
Vendored
+1 -1
View File
@@ -13,5 +13,5 @@ R$2 3 1 7650 M2
* device instance $3 4.665,0.335 RES, model M3
R$3 3 2 2670 M3
* device instance $4 1.765,7.485 HVPMOS
M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
.ENDS TOP
testdata/algo/nreader2.cir
Vendored
+6 -6
View File
@@ -54,13 +54,13 @@ X$12 12 13 15 12 11 15 INVX1
* net 6 A
* net 7 BULK
* device instance $1 0.85,5.8 LVPMOS
M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 1.55,5.8 LVPMOS
M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 0.85,2.135 LVNMOS
M$3 3 6 8 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 1.55,2.135 LVNMOS
M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
* cell INVX1
@@ -77,7 +77,7 @@ M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* net 5 IN
* net 6 BULK
* device instance $1 0.85,5.8 LVPMOS
M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 0.85,2.135 LVNMOS
M$2 3 5 2 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
testdata/algo/nreader3.cir
Vendored
+6 -6
View File
@@ -1,13 +1,13 @@
.subckt INVX1 1 2 3 4 5 6
m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um
m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um
m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um
m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um
.ends
.subckt ND2X1 1 2 3 4 5 6 7
m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um
m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um
m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um
m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um
m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um
m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um
m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um
m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um
.ends ND2X1
.subckt RINGO 11 12 13 14 15
testdata/algo/nreader7.cir
Vendored
+6 -6
View File
@@ -19,13 +19,13 @@ X$12 OUT FB INVX1
.ENDS RINGO
.SUBCKT ND2X1 OUT B A
M$1 OUT A VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A INT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$4 INT B OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$1 VDD A OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 INT A VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$4 OUT B INT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
.SUBCKT INVX1 OUT IN
M$1 VDD IN OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$1 OUT IN VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
testdata/algo/nreader8b.cir
Vendored
+4 -4
View File
@@ -1,8 +1,8 @@
.subckt ND2X1 1 2 3 4 5 6 7
m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um
m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um
m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um
m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um
m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um
m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um
m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um
m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um
.ends ND2X1
testdata/algo/nreader8x.cir
Vendored
+2 -2
View File
@@ -1,3 +1,3 @@
m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um
m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um
m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um
m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um
testdata/algo/nwriter11_au.txt
Vendored
+2 -2
View File
@@ -28,7 +28,7 @@ XSC2 3 7 4 3 C1
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter11b_au.txt
Vendored
+2 -2
View File
@@ -18,7 +18,7 @@ XSC2 n3 nc_12 n4 n3 C1
* pin p4
.SUBCKT C1 n1 n2 n4 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 n1 n4 n3 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 n3 n4 n1 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 n3 n4 n2 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 n2 n4 n3 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter5_au.txt
Vendored
+2 -2
View File
@@ -10,7 +10,7 @@
* net 3 n3
* net 4 n4
* device instance $1 r0 *1 0,0 M3CLS
M$1 1 4 3 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M3CLS
M$2 3 4 2 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter6_au.txt
Vendored
+2 -2
View File
@@ -12,7 +12,7 @@
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter8_au.txt
Vendored
+2 -2
View File
@@ -28,7 +28,7 @@ XSC2 3 2 4 3 C1
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1
testdata/lvs/double_height.cir
Vendored
+2 -2
View File
@@ -10,8 +10,8 @@ X$2 VSS VDD A1 Q1 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/double_height2.cir
Vendored
+2 -2
View File
@@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/double_height2_texts.cir
Vendored
+2 -2
View File
@@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/floating.cir
Vendored
+2 -2
View File
@@ -44,7 +44,7 @@ X$2 3 5 2 6 INVX1
* net 3 IN
* net 4 VSS
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
testdata/lvs/floating.lvsdb
Vendored
+4 -4
View File
@@ -284,9 +284,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 2)
terminal(B 3)
)
device(2 PMOS
@@ -297,9 +297,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 4)
terminal(G 1)
terminal(D 4)
terminal(D 2)
terminal(B 4)
)
testdata/lvs/inv.lvsdb
Vendored
+4 -4
View File
@@ -197,9 +197,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
device(2 NMOS
@@ -210,9 +210,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 1)
terminal(G 2)
terminal(D 1)
terminal(D 3)
terminal(B 5)
)
testdata/lvs/inv2.lvsdb
Vendored
+4 -4
View File
@@ -167,9 +167,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 4)
T(S 3)
T(G 2)
T(D 3)
T(D 4)
T(B 4)
)
D(2 NMOS
@@ -180,9 +180,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(S 1)
T(G 2)
T(D 1)
T(D 3)
T(B 1)
)
)
testdata/lvs/inv2_layout.cir
Vendored
+2 -2
View File
@@ -7,7 +7,7 @@
* net 3 OUT
* net 4 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 2 1 3 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
M$1 3 1 2 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
* device instance $2 r0 *1 1.025,0.65 NMOS
M$2 4 1 3 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
M$2 3 1 4 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
.ENDS INVERTER_WITH_DIODES
testdata/lvs/inv_layout.cir
Vendored
+2 -2
View File
@@ -9,7 +9,7 @@
* net 5 NWELL
* net 6 SUBSTRATE
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 3 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
M$1 4 1 3 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
* device instance $2 r0 *1 1.025,0.65 NMOS
M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
M$2 4 1 2 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
.ENDS INVERTER
testdata/lvs/invchain_cheat.cir.1
Vendored
+2 -2
View File
@@ -18,8 +18,8 @@ X$2 \$I2 \$I4 \$I5 \$I7 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/nand2_split_gate.cir.1
Vendored
+4 -4
View File
@@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,2 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,2 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES
testdata/lvs/nand2_split_gate.cir.2
Vendored
+4 -4
View File
@@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES
testdata/lvs/nand2_split_gate.cir.3
Vendored
+23
View File
@@ -0,0 +1,23 @@
* Extracted by KLayout
* cell NAND2_WITH_DIODES
* pin B
* pin A
* pin OUT
* pin VDD
* pin VSS
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
* net 1 B
* net 2 A
* net 4 OUT
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES
testdata/lvs/nand2_split_gate.lvsdb.1
Vendored
+8 -8
View File
@@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
testdata/lvs/nand2_split_gate.lvsdb.2
Vendored
+8 -8
View File
@@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
testdata/lvs/nand2_split_gate_early.cir.1
Vendored
+4 -4
View File
@@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,2 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,2 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES
testdata/lvs/nand2_split_gate_early.cir.2
Vendored
+4 -4
View File
@@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES
testdata/lvs/nand2_split_gate_early.lvsdb.1
Vendored
+8 -8
View File
@@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
testdata/lvs/nand2_split_gate_early.lvsdb.2
Vendored
+8 -8
View File
@@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
testdata/lvs/ringo.cir
Vendored
+5 -5
View File
@@ -16,12 +16,12 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U
M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U
M$4 1 B OUT BULK NMOS L=0.25U W=0.95U
M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U
M$3 1 A VSS BULK NMOS L=0.25U W=0.95U
M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U
.ENDS ND2X1
.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK
M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U
M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U
M$1 OUT IN VDD NWELL PMOS L=0.25U W=1.5U
M$2 OUT IN VSS BULK NMOS L=0.25U W=0.95U
.ENDS INVX1
testdata/lvs/ringo_device_subcircuits.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_fixed_sources.gds
Vendored
BIN
View File
Binary file not shown.
testdata/lvs/ringo_layout_var.cir
Vendored
+8 -8
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1B
* cell INVX1
@@ -71,9 +71,9 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_layout_var.lvsdb.1
Vendored
+2 -2
View File
@@ -692,9 +692,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_layout_var.lvsdb.2
Vendored
+2 -2
View File
@@ -692,9 +692,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_mixed_hierarchy.cir
Vendored
+6 -6
View File
@@ -35,13 +35,13 @@ X$15 3 12 16 3 11 16 INVX1
* cell instance $16 r0 *1 18.6,0
X$16 3 13 16 3 12 16 INVX1
* device instance $1 r0 *1 2.65,5.8 PMOS
M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 3 2 4 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 3.35,5.8 PMOS
M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 4 1 3 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 2.65,2.135 NMOS
M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 15 2 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 3.35,2.135 NMOS
M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS RINGO
* cell INVX1
@@ -58,7 +58,7 @@ M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
testdata/lvs/ringo_mixed_hierarchy.lvsdb
Vendored
+2 -2
View File
@@ -616,9 +616,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 2)
terminal(G 4)
terminal(D 2)
terminal(D 6)
terminal(B 2)
)
device(2 PMOS
testdata/lvs/ringo_simple.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple.lvsdb.1
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple.lvsdb.2
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_compare2.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_compare2.lvsdb.1
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_compare2.lvsdb.2
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_device_scaling.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
M$1 2 5 1 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
M$2 2 5 3 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
M$1 1 6 2 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
M$2 2 5 1 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
M$3 8 6 3 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
M$4 2 5 8 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
.ENDS ND2X1
testdata/lvs/ringo_simple_device_scaling.lvsdb.1
Vendored
+12 -12
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_device_scaling.lvsdb.2
Vendored
+12 -12
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_dmos.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 7 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 6 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$3 3 7 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 4 6 2 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_dmos.lvsdb.1
Vendored
+18 -44
View File
@@ -609,9 +609,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -851,62 +851,36 @@ xref(
)
)
circuit(ND2X1 ND2X1 nomatch
log(
entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
)
xref(
net(4 8 mismatch)
net(5 4 mismatch)
net(5 4 match)
net(4 3 mismatch)
net(7 6 match)
net(6 5 match)
net(2 2 mismatch)
net(2 2 match)
net(8 7 mismatch)
net(1 1 mismatch)
net(3 3 mismatch)
net(1 1 match)
net(3 8 mismatch)
pin(() 2 mismatch)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 mismatch)
device(4 4 match)
pin(2 () mismatch)
device(3 3 match)
device(4 4 mismatch)
device(1 1 match)
device(2 2 match)
device(1 1 mismatch)
)
)
circuit(RINGO RINGO match
circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1')
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)
testdata/lvs/ringo_simple_dmos.lvsdb.2
Vendored
+18 -44
View File
@@ -609,9 +609,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -851,62 +851,36 @@ xref(
)
)
circuit(ND2X1 ND2X1 nomatch
log(
entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
)
xref(
net(4 8 mismatch)
net(5 4 mismatch)
net(5 4 match)
net(4 3 mismatch)
net(7 6 match)
net(6 5 match)
net(2 2 mismatch)
net(2 2 match)
net(8 7 mismatch)
net(1 1 mismatch)
net(3 3 mismatch)
net(1 1 match)
net(3 8 mismatch)
pin(() 2 mismatch)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 mismatch)
device(4 4 match)
pin(2 () mismatch)
device(3 3 match)
device(4 4 mismatch)
device(1 1 match)
device(2 2 match)
device(1 1 mismatch)
)
)
circuit(RINGO RINGO match
circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1')
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)
testdata/lvs/ringo_simple_dmos_fixed.cir.1
Vendored
+83
View File
@@ -0,0 +1,83 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 11 12 13 14 15
* net 11 FB
* net 12 VDD
* net 13 OUT
* net 14 ENABLE
* net 15 VSS
* cell instance $1 r0 *1 1.8,0
X$1 12 1 15 12 11 14 15 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 12 2 15 12 1 15 INVX1
* cell instance $3 r0 *1 6,0
X$3 12 3 15 12 2 15 INVX1
* cell instance $4 r0 *1 7.8,0
X$4 12 4 15 12 3 15 INVX1
* cell instance $5 r0 *1 9.6,0
X$5 12 5 15 12 4 15 INVX1
* cell instance $6 r0 *1 11.4,0
X$6 12 6 15 12 5 15 INVX1
* cell instance $7 r0 *1 13.2,0
X$7 12 7 15 12 6 15 INVX1
* cell instance $8 r0 *1 15,0
X$8 12 8 15 12 7 15 INVX1
* cell instance $9 r0 *1 16.8,0
X$9 12 9 15 12 8 15 INVX1
* cell instance $10 r0 *1 18.6,0
X$10 12 10 15 12 9 15 INVX1
* cell instance $11 r0 *1 20.4,0
X$11 12 11 15 12 10 15 INVX1
* cell instance $12 r0 *1 22.2,0
X$12 12 13 15 12 11 15 INVX1
.ENDS RINGO
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin SUBSTRATE
.SUBCKT ND2X1 1 2 3 5 6 7 8
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 6 B
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_dmos_fixed.cir.2
Vendored
+83
View File
@@ -0,0 +1,83 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 11 12 13 14 15
* net 11 FB
* net 12 VDD
* net 13 OUT
* net 14 ENABLE
* net 15 VSS
* cell instance $1 r0 *1 1.8,0
X$1 12 1 15 12 11 14 15 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 12 2 15 12 1 15 INVX1
* cell instance $3 r0 *1 6,0
X$3 12 3 15 12 2 15 INVX1
* cell instance $4 r0 *1 7.8,0
X$4 12 4 15 12 3 15 INVX1
* cell instance $5 r0 *1 9.6,0
X$5 12 5 15 12 4 15 INVX1
* cell instance $6 r0 *1 11.4,0
X$6 12 6 15 12 5 15 INVX1
* cell instance $7 r0 *1 13.2,0
X$7 12 7 15 12 6 15 INVX1
* cell instance $8 r0 *1 15,0
X$8 12 8 15 12 7 15 INVX1
* cell instance $9 r0 *1 16.8,0
X$9 12 9 15 12 8 15 INVX1
* cell instance $10 r0 *1 18.6,0
X$10 12 10 15 12 9 15 INVX1
* cell instance $11 r0 *1 20.4,0
X$11 12 11 15 12 10 15 INVX1
* cell instance $12 r0 *1 22.2,0
X$12 12 13 15 12 11 15 INVX1
.ENDS RINGO
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin SUBSTRATE
.SUBCKT ND2X1 1 2 3 5 6 7 8
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 6 B
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 1.55,2.135 NMOS
M$3 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U
* device instance $4 r0 *1 0.85,2.135 NMOS
M$4 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U
.ENDS ND2X1
testdata/lvs/ringo_simple_dmos_fixed.lvs
Vendored
+83
View File
@@ -0,0 +1,83 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("ringo.cir")
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
contact = input(8, 0)
metal1 = input(9, 0)
via1 = input(10, 0)
metal2 = input(11, 0)
source = input(14, 0)
# Bulk layer for terminal provisioning
bulk = polygon_layer
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly
psd = pactive - pgate
ps = psd & source
pd = psd - source
ntie = active_in_nwell & nplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly
nsd = nactive - ngate
ns = nsd & source
nd = nsd - source
ptie = active_outside_nwell & pplus
# Device extraction
# PMOS transistor device extraction
extract_devices(dmos4("PMOS"), { "S" => ps, "D" => pd, "G" => pgate, "W" => nwell,
"tS" => ps, "tD" => pd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(dmos4("NMOS"), { "S" => ns, "D" => nd, "G" => ngate, "W" => bulk,
"tS" => ns, "tD" => nd, "tG" => poly, "tW" => bulk })
# Define connectivity for netlist extraction
# Inter-layer
connect(ps, pd)
connect(ns, nd)
connect(ps, contact)
connect(pd, contact)
connect(ns, contact)
connect(nd, contact)
connect(poly, contact)
connect(ntie, contact)
connect(nwell, ntie)
connect(ptie, contact)
connect(contact, metal1)
connect(metal1, via1)
connect(via1, metal2)
# Global
connect_global(bulk, "SUBSTRATE")
connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.simplify
compare
testdata/lvs/ringo_simple_dmos_fixed.lvsdb.1
Vendored
+918
View File
@@ -0,0 +1,918 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l4 '1/0')
layer(l5 '5/0')
layer(l10 '8/0')
layer(l13 '9/0')
layer(l14 '10/0')
layer(l15 '11/0')
layer(l9)
layer(l3)
layer(l1)
layer(l11)
layer(l8)
layer(l6)
layer(l12)
# Mask layer connectivity
connect(l4 l4 l11)
connect(l5 l5 l10)
connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
connect(l13 l10 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l9 l9)
connect(l3 l10 l3 l1)
connect(l1 l10 l3 l1)
connect(l11 l4 l10 l11)
connect(l8 l10 l8 l6)
connect(l6 l10 l8 l6)
connect(l12 l10 l12)
# Global nets and connectivity
global(l9 SUBSTRATE)
global(l12 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l3 (125 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (-550 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l3 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l3 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (233 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l8 (-342 -475) (217 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -790) (300 1700))
rect(l13 (-1350 0) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l3 (-275 -2150) (425 1500))
rect(l3 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l10 (1810 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-1580 3760) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (1220 920) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l13 (-110 1390) (300 1400))
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l13 (-140 -500) (0 0))
rect(l13 (-1750 1100) (300 1400))
rect(l13 (1100 -1700) (300 300))
rect(l13 (-300 0) (300 1400))
rect(l1 (-1750 -1450) (425 1500))
rect(l1 (950 -1500) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l8 (-950 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l8 (1208 1660) (192 950))
rect(l8 (-192 -950) (217 950))
rect(l6 (-425 -950) (208 950))
rect(l6 (-233 -950) (233 950))
)
net(5
rect(l4 (-100 4500) (2600 3500))
)
net(6 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-285 1050) (180 180))
rect(l13 (-70 -90) (0 0))
rect(l13 (-170 -150) (300 300))
)
net(7 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-265 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(8 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(5)
pin(6 name(B))
pin(7 name(A))
pin(8 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 7)
terminal(D 2)
terminal(B 5)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 5)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.22135)
param(PS 2.75)
param(PD 2.366)
terminal(S 3)
terminal(G 7)
terminal(D 4)
terminal(B 8)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.20615)
param(AD 0.40375)
param(PS 2.334)
param(PD 2.75)
terminal(S 4)
terminal(G 6)
terminal(D 2)
terminal(B 8)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (410 6260) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -240) (300 1400))
rect(l13 (-650 300) (1800 800))
rect(l13 (-1450 -1100) (300 300))
rect(l13 (300 400) (0 0))
rect(l3 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -4120) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -790) (300 4790))
rect(l13 (-150 -2500) (0 0))
rect(l1 (-225 1050) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (1800 800))
rect(l13 (-850 -400) (0 0))
rect(l8 (-650 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l4 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-465 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l13 (4040 2950) (610 300))
)
net(2
rect(l13 (5550 2950) (900 300))
)
net(3
rect(l13 (7350 2950) (900 300))
)
net(4
rect(l13 (9150 2950) (900 300))
)
net(5
rect(l13 (10950 2950) (900 300))
)
net(6
rect(l13 (12750 2950) (900 300))
)
net(7
rect(l13 (14550 2950) (900 300))
)
net(8
rect(l13 (16350 2950) (900 300))
)
net(9
rect(l13 (18150 2950) (900 300))
)
net(10
rect(l13 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l13 (21750 2950) (900 300))
rect(l13 (-19530 590) (320 320))
rect(l13 (17820 -320) (320 320))
rect(l14 (-18400 -260) (200 200))
rect(l14 (17940 -200) (200 200))
rect(l15 (-18040 -300) (17740 400))
rect(l15 (-17920 -200) (0 0))
rect(l15 (-220 -200) (400 400))
rect(l15 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l4 (500 4500) (1400 3500))
rect(l4 (-1900 -3500) (600 3500))
rect(l4 (23300 -3500) (1400 3500))
rect(l4 (-100 -3500) (600 3500))
rect(l10 (-24690 -1240) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l13 (-21740 860) (0 0))
rect(l13 (-2350 -450) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23400 -800) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (550 -400) (600 800))
rect(l11 (-24850 -1500) (500 1500))
rect(l11 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l13 (23440 3840) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(14 name(ENABLE)
rect(l13 (2440 2940) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(15 name(VSS)
rect(l10 (1110 1610) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-21740 -390) (0 0))
rect(l13 (-1900 -400) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23850 -750) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (550 -400) (600 800))
rect(l12 (-24850 -800) (500 1500))
rect(l12 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(4 8 match)
net(5 4 match)
net(7 6 match)
net(6 5 match)
net(2 2 match)
net(8 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)
testdata/lvs/ringo_simple_dmos_fixed.lvsdb.2
Vendored
+918
View File
@@ -0,0 +1,918 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l4 '1/0')
layer(l5 '5/0')
layer(l10 '8/0')
layer(l13 '9/0')
layer(l14 '10/0')
layer(l15 '11/0')
layer(l9)
layer(l3)
layer(l1)
layer(l11)
layer(l8)
layer(l6)
layer(l12)
# Mask layer connectivity
connect(l4 l4 l11)
connect(l5 l5 l10)
connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
connect(l13 l10 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l9 l9)
connect(l3 l10 l3 l1)
connect(l1 l10 l3 l1)
connect(l11 l4 l10 l11)
connect(l8 l10 l8 l6)
connect(l6 l10 l8 l6)
connect(l12 l10 l12)
# Global nets and connectivity
global(l9 SUBSTRATE)
global(l12 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l3 (125 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (-550 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l3 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l3 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l8 (-342 -475) (217 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (233 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -790) (300 1700))
rect(l13 (-1350 0) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l3 (-250 -2150) (425 1500))
rect(l3 (-450 -1500) (425 1500))
)
net(2 name(OUT)
rect(l10 (1810 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-1580 3760) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (1220 920) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l13 (-110 1390) (300 1400))
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l13 (-140 -500) (0 0))
rect(l13 (-1750 1100) (300 1400))
rect(l13 (1100 -1700) (300 300))
rect(l13 (-300 0) (300 1400))
rect(l1 (-1750 -1450) (425 1500))
rect(l1 (950 -1500) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l8 (-950 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l8 (1208 1660) (192 950))
rect(l8 (-192 -950) (217 950))
rect(l6 (-425 -950) (208 950))
rect(l6 (-233 -950) (233 950))
)
net(5
rect(l4 (-100 4500) (2600 3500))
)
net(6 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-285 1050) (180 180))
rect(l13 (-70 -90) (0 0))
rect(l13 (-170 -150) (300 300))
)
net(7 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-265 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(8 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(5)
pin(6 name(B))
pin(7 name(A))
pin(8 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 7)
terminal(D 2)
terminal(B 5)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 5)
)
device(3 D$NMOS
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.20615)
param(AD 0.40375)
param(PS 2.334)
param(PD 2.75)
terminal(S 4)
terminal(G 6)
terminal(D 2)
terminal(B 8)
)
device(4 D$NMOS$1
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.22135)
param(PS 2.75)
param(PD 2.366)
terminal(S 3)
terminal(G 7)
terminal(D 4)
terminal(B 8)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (410 6260) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -240) (300 1400))
rect(l13 (-650 300) (1800 800))
rect(l13 (-1450 -1100) (300 300))
rect(l13 (300 400) (0 0))
rect(l3 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -4120) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -790) (300 4790))
rect(l13 (-150 -2500) (0 0))
rect(l1 (-225 1050) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (1800 800))
rect(l13 (-850 -400) (0 0))
rect(l8 (-650 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l4 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-465 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l13 (4040 2950) (610 300))
)
net(2
rect(l13 (5550 2950) (900 300))
)
net(3
rect(l13 (7350 2950) (900 300))
)
net(4
rect(l13 (9150 2950) (900 300))
)
net(5
rect(l13 (10950 2950) (900 300))
)
net(6
rect(l13 (12750 2950) (900 300))
)
net(7
rect(l13 (14550 2950) (900 300))
)
net(8
rect(l13 (16350 2950) (900 300))
)
net(9
rect(l13 (18150 2950) (900 300))
)
net(10
rect(l13 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l13 (21750 2950) (900 300))
rect(l13 (-19530 590) (320 320))
rect(l13 (17820 -320) (320 320))
rect(l14 (-18400 -260) (200 200))
rect(l14 (17940 -200) (200 200))
rect(l15 (-18040 -300) (17740 400))
rect(l15 (-17920 -200) (0 0))
rect(l15 (-220 -200) (400 400))
rect(l15 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l4 (500 4500) (1400 3500))
rect(l4 (-1900 -3500) (600 3500))
rect(l4 (23300 -3500) (1400 3500))
rect(l4 (-100 -3500) (600 3500))
rect(l10 (-24690 -1240) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l13 (-21740 860) (0 0))
rect(l13 (-2350 -450) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23400 -800) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (550 -400) (600 800))
rect(l11 (-24850 -1500) (500 1500))
rect(l11 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l13 (23440 3840) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(14 name(ENABLE)
rect(l13 (2440 2940) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(15 name(VSS)
rect(l10 (1110 1610) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-21740 -390) (0 0))
rect(l13 (-1900 -400) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23850 -750) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (550 -400) (600 800))
rect(l12 (-24850 -800) (500 1500))
rect(l12 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(4 8 match)
net(5 4 match)
net(7 6 match)
net(6 5 match)
net(2 2 match)
net(8 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(4 3 match)
device(3 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)
testdata/lvs/ringo_simple_dummy_device.cir
Vendored
+6 -6
View File
@@ -54,9 +54,9 @@ M$1 16 1 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -75,11 +75,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_dummy_device.lvsdb.1
Vendored
+13 -13
View File
@@ -609,8 +609,8 @@ layout(
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -657,9 +657,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -670,9 +670,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -683,9 +683,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -717,9 +717,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -730,9 +730,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_dummy_device.lvsdb.2
Vendored
+13 -13
View File
@@ -609,8 +609,8 @@ layout(
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -657,9 +657,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -670,9 +670,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -683,9 +683,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -717,9 +717,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -730,9 +730,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_dummy_device.lvsdb.3
Vendored
-965
View File
@@ -1,965 +0,0 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l2 (-275 -2150) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-140 -500) (0 0))
rect(l11 (-1750 1100) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l6 (-950 860) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-70 -90) (0 0))
rect(l11 (-170 -150) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-90 -90) (0 0))
rect(l11 (-150 -150) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS$1
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$2
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (300 400) (0 0))
rect(l2 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-150 -2500) (0 0))
rect(l2 (-225 1050) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-850 -400) (0 0))
rect(l6 (-650 860) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-90 -90) (0 0))
rect(l11 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (27600 7650))
# Nets with their geometries
net(1
rect(l4 (26050 2800) (525 550))
rect(l4 (-525 -300) (300 300))
rect(l4 (-25 -2000) (250 1450))
rect(l8 (-465 310) (180 180))
rect(l11 (-240 -240) (300 300))
)
net(2
rect(l11 (4040 2950) (610 300))
)
net(3
rect(l11 (5550 2950) (900 300))
)
net(4
rect(l11 (7350 2950) (900 300))
)
net(5
rect(l11 (9150 2950) (900 300))
)
net(6
rect(l11 (10950 2950) (900 300))
)
net(7
rect(l11 (12750 2950) (900 300))
)
net(8
rect(l11 (14550 2950) (900 300))
)
net(9
rect(l11 (16350 2950) (900 300))
)
net(10
rect(l11 (18150 2950) (900 300))
)
net(11
rect(l11 (19950 2950) (900 300))
)
net(12 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17920 -200) (0 0))
rect(l13 (-220 -200) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(13 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l8 (-26490 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21740 860) (0 0))
rect(l11 (-2350 -450) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l9 (-26650 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(14 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(15 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(16 name(VSS)
rect(l8 (26010 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (520 -730) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-25780 -890) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (1260 -40) (300 1360))
rect(l11 (400 -1360) (300 1360))
rect(l11 (-24000 -1710) (0 0))
rect(l11 (-1900 -400) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l6 (-1025 400) (425 950))
rect(l6 (-1100 -950) (425 950))
rect(l10 (-25375 -2150) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(12 name(FB))
pin(13 name(VDD))
pin(14 name(OUT))
pin(15 name(ENABLE))
pin(16 name(VSS))
# Devices and their connections
device(1 D$NMOS
location(26450 2075)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 16)
terminal(G 1)
terminal(D 16)
terminal(B 16)
)
# Subcircuits and their connections
circuit(3 ND2X1 location(1800 0)
pin(0 13)
pin(1 2)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 15)
pin(6 16)
)
circuit(4 INVX1 location(4200 0)
pin(0 13)
pin(1 3)
pin(2 16)
pin(3 13)
pin(4 2)
pin(5 16)
)
circuit(5 INVX1 location(6000 0)
pin(0 13)
pin(1 4)
pin(2 16)
pin(3 13)
pin(4 3)
pin(5 16)
)
circuit(6 INVX1 location(7800 0)
pin(0 13)
pin(1 5)
pin(2 16)
pin(3 13)
pin(4 4)
pin(5 16)
)
circuit(7 INVX1 location(9600 0)
pin(0 13)
pin(1 6)
pin(2 16)
pin(3 13)
pin(4 5)
pin(5 16)
)
circuit(8 INVX1 location(11400 0)
pin(0 13)
pin(1 7)
pin(2 16)
pin(3 13)
pin(4 6)
pin(5 16)
)
circuit(9 INVX1 location(13200 0)
pin(0 13)
pin(1 8)
pin(2 16)
pin(3 13)
pin(4 7)
pin(5 16)
)
circuit(10 INVX1 location(15000 0)
pin(0 13)
pin(1 9)
pin(2 16)
pin(3 13)
pin(4 8)
pin(5 16)
)
circuit(11 INVX1 location(16800 0)
pin(0 13)
pin(1 10)
pin(2 16)
pin(3 13)
pin(4 9)
pin(5 16)
)
circuit(12 INVX1 location(18600 0)
pin(0 13)
pin(1 11)
pin(2 16)
pin(3 13)
pin(4 10)
pin(5 16)
)
circuit(13 INVX1 location(20400 0)
pin(0 13)
pin(1 12)
pin(2 16)
pin(3 13)
pin(4 11)
pin(5 16)
)
circuit(14 INVX1 location(22200 0)
pin(0 13)
pin(1 14)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 16)
)
)
)
# Reference netlist
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
net(16 name(DUMMY))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Devices and their connections
device(1 NMOS
name($1)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 16)
terminal(D 1)
terminal(B 1)
)
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(2 6 match)
net(11 15 match)
net(3 7 match)
net(4 8 match)
net(5 9 match)
net(6 10 match)
net(7 11 match)
net(8 12 match)
net(9 13 match)
net(10 14 match)
net(1 16 match)
net(15 4 match)
net(12 3 match)
net(14 5 match)
net(13 2 match)
net(16 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
device(1 1 match)
circuit(4 2 match)
circuit(5 3 match)
circuit(6 4 match)
circuit(7 5 match)
circuit(8 6 match)
circuit(9 7 match)
circuit(10 8 match)
circuit(11 9 match)
circuit(12 10 match)
circuit(13 11 match)
circuit(14 12 match)
circuit(3 1 match)
)
)
)
testdata/lvs/ringo_simple_implicit_connections.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
Vendored
+2 -2
View File
@@ -624,9 +624,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
Vendored
+2 -2
View File
@@ -624,9 +624,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_io.cir.1
Vendored
+6 -6
View File
@@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I3 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I3 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_io.cir.2
Vendored
+6 -6
View File
@@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I5 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_io.lvsdb.1
Vendored
+2 -2
View File
@@ -546,9 +546,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(S 1)
T(G 6)
T(D 1)
T(D 2)
T(B 4)
)
D(2 PMOS
testdata/lvs/ringo_simple_io.lvsdb.2
Vendored
+2 -2
View File
@@ -546,9 +546,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(S 1)
T(G 6)
T(D 1)
T(D 2)
T(B 4)
)
D(2 PMOS
testdata/lvs/ringo_simple_io2.lvsdb.1
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_io2.lvsdb.2
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INV
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INV
* cell nd2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS nd2X1
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2
Vendored
+2 -2
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_pin_swapping.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_pin_swapping.lvsdb.1
Vendored
+12 -12
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 5)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 5)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_pin_swapping.lvsdb.2
Vendored
+12 -12
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 5)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 5)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_same_device_classes.cir.1
Vendored
+6 -6
View File
@@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I3 A VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I3 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_same_device_classes.cir.2
Vendored
+6 -6
View File
@@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I5 A VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I5 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_same_device_classes.lvsdb.1
Vendored
+2 -2
View File
@@ -607,9 +607,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_same_device_classes.lvsdb.2
Vendored
+2 -2
View File
@@ -607,9 +607,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
testdata/lvs/ringo_simple_simplification.cir
Vendored
+8 -8
View File
@@ -52,9 +52,9 @@ X$21 6 11 9 6 15 9 INVX1
* net 4 VSS
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
.ENDS INVX2
* cell INVX1
@@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_simplification.lvsdb.1
Vendored
+16 -16
View File
@@ -727,9 +727,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -740,9 +740,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -753,9 +753,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -766,9 +766,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -800,9 +800,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -813,9 +813,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
@@ -847,9 +847,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -860,9 +860,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_simplification.lvsdb.2
Vendored
+16 -16
View File
@@ -727,9 +727,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -740,9 +740,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -753,9 +753,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -766,9 +766,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -800,9 +800,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -813,9 +813,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
@@ -847,9 +847,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -860,9 +860,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_simplification.lvsdb.3
Vendored
-1095
View File
File diff suppressed because it is too large Load Diff
testdata/lvs/ringo_simple_simplification_with_align.cir
Vendored
+8 -8
View File
@@ -52,9 +52,9 @@ X$17 6 11 9 6 15 9 INVX1
* net 4 VSS
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
.ENDS INVX2
* cell INVX1
@@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1
Vendored
+16 -16
View File
@@ -727,9 +727,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -740,9 +740,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -753,9 +753,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -766,9 +766,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -800,9 +800,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -813,9 +813,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
@@ -847,9 +847,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -860,9 +860,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2
Vendored
+16 -16
View File
@@ -727,9 +727,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -740,9 +740,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -753,9 +753,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -766,9 +766,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -800,9 +800,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -813,9 +813,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
@@ -847,9 +847,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -860,9 +860,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)
testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3
Vendored
-1095
View File
File diff suppressed because it is too large Load Diff
testdata/lvs/ringo_simple_with_tol.cir
Vendored
+6 -6
View File
@@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
testdata/lvs/ringo_simple_with_tol.lvsdb.1
Vendored
+12 -12
View File
@@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

Some files were not shown because too many files have changed in this diff Show More