diff --git a/src/db/db/db.pro b/src/db/db/db.pro index a65043b30..066dbb5d2 100644 --- a/src/db/db/db.pro +++ b/src/db/db/db.pro @@ -60,6 +60,8 @@ SOURCES = \ dbNetlistCompareCore.cc \ dbNetlistCompareGraph.cc \ dbNetlistCompareUtils.cc \ + dbNetlistSpiceReaderDelegate.cc \ + dbNetlistSpiceReaderExpressionParser.cc \ dbObject.cc \ dbPath.cc \ dbPCellDeclaration.cc \ @@ -279,6 +281,8 @@ HEADERS = \ dbNetlistCompareCore.h \ dbNetlistCompareGraph.h \ dbNetlistCompareUtils.h \ + dbNetlistSpiceReaderDelegate.h \ + dbNetlistSpiceReaderExpressionParser.h \ dbObject.h \ dbObjectTag.h \ dbObjectWithProperties.h \ diff --git a/src/db/db/dbNetlistSpiceReader.cc b/src/db/db/dbNetlistSpiceReader.cc index 04e8d94e8..978662e3e 100644 --- a/src/db/db/dbNetlistSpiceReader.cc +++ b/src/db/db/dbNetlistSpiceReader.cc @@ -21,19 +21,21 @@ */ #include "dbNetlistSpiceReader.h" +#include "dbNetlistSpiceReaderExpressionParser.h" +#include "dbNetlistSpiceReaderDelegate.h" #include "dbNetlist.h" -#include "dbNetlistDeviceClasses.h" -#include "tlStream.h" -#include "tlLog.h" -#include "tlString.h" -#include "tlFileUtils.h" #include "tlUri.h" -#include "tlTimer.h" +#include "tlFileUtils.h" #include "tlLog.h" +#include "tlTimer.h" -#include -#include +#include +#include +#include +#include +#include +#include namespace db { @@ -42,612 +44,81 @@ namespace db static const char *allowed_name_chars = "_.:,!+$/&\\#[]|<>"; -inline static int hex_num (char c) -{ - if (c >= '0' && c <= '9') { - return (int (c - '0')); - } else if (c >= 'a' && c <= 'f') { - return (int (c - 'f') + 10); - } else { - return -1; - } -} - -static std::string unescape_name (const std::string &n) -{ - std::string nn; - nn.reserve (n.size ()); - - const char *cp = n.c_str (); - while (*cp) { - - if (*cp == '\\' && cp[1]) { - - if (tolower (cp[1]) == 'x') { - - cp += 2; - - char c = 0; - for (int i = 0; i < 2 && *cp; ++i) { - int n = hex_num (*cp); - if (n >= 0) { - ++cp; - c = c * 16 + char (n); - } else { - break; - } - } - - nn += c; - - } else { - ++cp; - nn += *cp++; - } - - } else { - nn += *cp++; - } - - } - - return nn; -} - // ------------------------------------------------------------------------------------------------------ -NetlistSpiceReaderDelegate::NetlistSpiceReaderDelegate () +void +read_param_card (tl::Extractor &ex, const db::Netlist *netlist, std::map &variables) { - // .. nothing yet .. -} - -NetlistSpiceReaderDelegate::~NetlistSpiceReaderDelegate () -{ - // .. nothing yet .. -} - -void NetlistSpiceReaderDelegate::start (db::Netlist * /*netlist*/) -{ - // .. nothing yet .. -} - -void NetlistSpiceReaderDelegate::finish (db::Netlist * /*netlist*/) -{ - // .. nothing yet .. -} - -bool NetlistSpiceReaderDelegate::control_statement(const std::string & /*line*/) -{ - return false; -} - -bool NetlistSpiceReaderDelegate::wants_subcircuit (const std::string & /*circuit_name*/) -{ - return false; -} - -std::string NetlistSpiceReaderDelegate::translate_net_name (const std::string &nn) -{ - return unescape_name (nn); -} - -void NetlistSpiceReaderDelegate::error (const std::string &msg) -{ - throw tl::Exception (msg); -} - -template -static db::DeviceClass *make_device_class (db::Circuit *circuit, const std::string &name) -{ - if (! circuit || ! circuit->netlist ()) { - return 0; - } - - db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (name); - if (! cls) { - cls = new Cls (); - cls->set_name (name); - circuit->netlist ()->add_device_class (cls); - } - - return cls; -} - -static std::string parse_component (tl::Extractor &ex) -{ - const char *cp = ex.skip (); - const char *cp0 = cp; - - char quote = 0; - unsigned int brackets = 0; - - while (*cp) { - if (quote) { - if (*cp == quote) { - quote = 0; - } else if (*cp == '\\' && cp[1]) { - ++cp; - } - } else if ((isspace (*cp) || *cp == '=') && ! brackets) { - break; - } else if (*cp == '"' || *cp == '\'') { - quote = *cp; - } else if (*cp == '(') { - ++brackets; - } else if (*cp == ')') { - if (brackets > 0) { - --brackets; - } - } - ++cp; - } - - ex = tl::Extractor (cp); - return std::string (cp0, cp - cp0); -} - -void NetlistSpiceReaderDelegate::parse_element_components (const std::string &s, std::vector &strings, std::map &pv) -{ - tl::Extractor ex (s.c_str ()); - bool in_params = false; + // Syntax is: + // .param = [ = ... ] + // taken from: + // https://nmg.gitlab.io/ngspice-manual/circuitdescription/paramparametricnetlists/paramline.html while (! ex.at_end ()) { - if (ex.test_without_case ("params:")) { + std::string name; + ex.read_word (name); - in_params = true; + name = netlist->normalize_name (name); - } else { + ex.test ("="); - tl::Extractor ex0 = ex; - std::string n; - - if (ex.try_read_word (n) && ex.test ("=")) { - // a parameter. Note that parameter names are always made upper case. - pv.insert (std::make_pair (tl::to_upper_case (n), read_value (ex))); - } else { - ex = ex0; - if (in_params) { - ex.error (tl::to_string (tr ("Invalid syntax for parameter assignment - needs keyword followed by '='"))); - } - strings.push_back (parse_component (ex)); - } - - } + tl::Variant value = NetlistSpiceReaderExpressionParser (&variables).read (ex); + variables [name] = value; } } -double NetlistSpiceReaderDelegate::read_atomic_value (tl::Extractor &ex) -{ - if (ex.test ("(")) { - - double v = read_dot_expr (ex); - ex.expect (")"); - return v; - - } else { - - double v = 0.0; - ex.read (v); - - double f = 1.0; - if (*ex == 't' || *ex == 'T') { - f = 1e12; - } else if (*ex == 'g' || *ex == 'G') { - f = 1e9; - } else if (*ex == 'k' || *ex == 'K') { - f = 1e3; - } else if (*ex == 'm' || *ex == 'M') { - f = 1e-3; - if (ex.test_without_case ("meg")) { - f = 1e6; - } - } else if (*ex == 'u' || *ex == 'U') { - f = 1e-6; - } else if (*ex == 'n' || *ex == 'N') { - f = 1e-9; - } else if (*ex == 'p' || *ex == 'P') { - f = 1e-12; - } else if (*ex == 'f' || *ex == 'F') { - f = 1e-15; - } else if (*ex == 'a' || *ex == 'A') { - f = 1e-18; - } - while (*ex && isalpha (*ex)) { - ++ex; - } - - v *= f; - return v; - - } -} - -double NetlistSpiceReaderDelegate::read_bar_expr (tl::Extractor &ex) -{ - double v = read_atomic_value (ex); - while (true) { - if (ex.test ("+")) { - double vv = read_atomic_value (ex); - v += vv; - } else if (ex.test ("+")) { - double vv = read_atomic_value (ex); - v -= vv; - } else { - break; - } - } - return v; -} - -double NetlistSpiceReaderDelegate::read_dot_expr (tl::Extractor &ex) -{ - double v = read_bar_expr (ex); - while (true) { - if (ex.test ("*")) { - double vv = read_bar_expr (ex); - v *= vv; - } else if (ex.test ("/")) { - double vv = read_bar_expr (ex); - v /= vv; - } else { - break; - } - } - return v; -} - -double NetlistSpiceReaderDelegate::read_value (tl::Extractor &ex) -{ - return read_dot_expr (ex); -} - -bool NetlistSpiceReaderDelegate::try_read_value (const std::string &s, double &value) -{ - tl::Extractor ve (s.c_str ()); - double vv = 0; - if (ve.try_read (vv) || ve.test ("(")) { - ve = tl::Extractor (s.c_str ()); - value = read_value (ve); - return true; - } else { - return false; - } -} - -void NetlistSpiceReaderDelegate::parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, std::map &pv) -{ - parse_element_components (s, nn, pv); - - // interpret the parameters according to the code - if (element == "X") { - - // subcircuit call: - // Xname n1 n2 ... nn circuit [params] - - if (nn.empty ()) { - error (tl::to_string (tr ("No circuit name given for subcircuit call"))); - } - - model = nn.back (); - nn.pop_back (); - - } else if (element == "R" || element == "C" || element == "L") { - - // resistor, cap, inductor: two-terminal devices with a value - // Rname n1 n2 value - // Rname n1 n2 n3 value - // Rname n1 n2 value model [params] - // Rname n1 n2 n3 value model [params] - // Rname n1 n2 [params] - // Rname n1 n2 model [params] - // Rname n1 n2 n3 model [params] - // NOTE: there is no "Rname n1 n2 n3 [params]"! - // (same for C, L instead of R) - - if (nn.size () < 2) { - error (tl::to_string (tr ("Not enough specs for a R, C or L device"))); - } - - std::map::const_iterator rv = pv.find (element); - if (rv != pv.end ()) { - - // value given by parameter - value = rv->second; - - if (nn.size () >= 3) { - // Rname n1 n2 model [params] - // Rname n1 n2 n3 model [params] - model = nn.back (); - nn.pop_back (); - } - - } else if (nn.size () >= 3) { - - if (try_read_value (nn.back (), value)) { - - // Rname n1 n2 value - // Rname n1 n2 n3 value - nn.pop_back (); - - } else { - - // Rname n1 n2 value model [params] - // Rname n1 n2 n3 value model [params] - model = nn.back (); - nn.pop_back (); - if (! try_read_value (nn.back (), value)) { - error (tl::to_string (tr ("Can't find a value for a R, C or L device"))); - } else { - nn.pop_back (); - } - - } - - } - - } else { - - // others: n-terminal devices with a model (last node) - - if (nn.empty ()) { - error (tl::sprintf (tl::to_string (tr ("No model name given for element '%s'")), element)); - } - - model = nn.back (); - nn.pop_back (); - - if (element == "M") { - if (nn.size () != 4) { - error (tl::to_string (tr ("'M' element must have four nodes"))); - } - } else if (element == "Q") { - if (nn.size () != 3 && nn.size () != 4) { - error (tl::to_string (tr ("'Q' element must have three or four nodes"))); - } - } else if (element == "D") { - if (nn.size () != 2) { - error (tl::to_string (tr ("'D' element must have two nodes"))); - } - } - - // TODO: other devices? - - } -} - -bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map &pv) -{ - std::map params = pv; - - double mult = 1.0; - std::map::const_iterator mp = params.find ("M"); - if (mp != params.end ()) { - mult = mp->second; - } - - if (mult < 1e-10) { - error (tl::sprintf (tl::to_string (tr ("Invalid multiplier value (M=%.12g) - must not be zero or negative")), mult)); - } - - std::string cn = model; - db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (cn); - - if (element == "R") { - - if (nets.size () == 2) { - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a resistor device class as required by 'R' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "RES"; - } - cls = make_device_class (circuit, cn); - } - } else if (nets.size () == 3) { - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal resistor device class as required by 'R' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "RES3"; - } - cls = make_device_class (circuit, cn); - } - } else { - error (tl::to_string (tr ("A 'R' element requires two or three nets"))); - } - - // Apply multiplier - value /= mult; - - } else if (element == "L") { - - if (nets.size () == 2) { - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a inductor device class as required by 'L' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "IND"; - } - cls = make_device_class (circuit, cn); - } - } else { - error (tl::to_string (tr ("A 'L' element requires two nets"))); - } - - // Apply multiplier - value /= mult; - - } else if (element == "C") { - - if (nets.size () == 2) { - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a capacitor device class as required by 'C' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "CAP"; - } - cls = make_device_class (circuit, cn); - } - } else if (nets.size () == 3) { - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal capacitor device class as required by 'C' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "CAP3"; - } - cls = make_device_class (circuit, cn); - } - } else { - error (tl::to_string (tr ("A 'C' element requires two or three nets"))); - } - - // Apply multiplier - value *= mult; - - } else if (element == "D") { - - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a diode device class as required by 'D' element")), cn)); - } - } else { - if (cn.empty ()) { - cn = "DIODE"; - } - cls = make_device_class (circuit, cn); - } - - // Apply multiplier to "A" - std::map::iterator p; - p = params.find ("A"); - if (p != params.end ()) { - p->second *= mult; - } - - } else if (element == "Q") { - - if (nets.size () != 3 && nets.size () != 4) { - error (tl::to_string (tr ("'Q' element needs to have 3 or 4 terminals"))); - } else if (cls) { - if (nets.size () == 3) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a 3-terminal BJT device class as required by 'Q' element")), cn)); - } - } else { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal BJT device class as required by 'Q' element")), cn)); - } - } - } else { - if (nets.size () == 3) { - if (cn.empty ()) { - cn = "BJT3"; - } - cls = make_device_class (circuit, cn); - } else { - if (cn.empty ()) { - cn = "BJT4"; - } - cls = make_device_class (circuit, cn); - } - } - - // Apply multiplier to "AE" - std::map::iterator p; - p = params.find ("AE"); - if (p != params.end ()) { - p->second *= mult; - } - - } else if (element == "M") { - - if (cls) { - if (! dynamic_cast(cls)) { - error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal MOS device class as required by 'M' element")), cn)); - } - } else { - if (nets.size () == 4) { - if (cn.empty ()) { - cn = "MOS4"; - } - cls = make_device_class (circuit, cn); - } else { - error (tl::to_string (tr ("'M' element needs to have 4 terminals"))); - } - } - - // Apply multiplier to "W" - std::map::iterator p; - p = params.find ("W"); - if (p != params.end ()) { - p->second *= mult; - } - - } else { - error (tl::sprintf (tl::to_string (tr ("Not a known element type: '%s'")), element)); - } - - const std::vector &td = cls->terminal_definitions (); - if (td.size () != nets.size ()) { - error (tl::sprintf (tl::to_string (tr ("Wrong number of terminals: class '%s' expects %d, but %d are given")), cn, int (td.size ()), int (nets.size ()))); - } - - db::Device *device = new db::Device (cls, name); - circuit->add_device (device); - - for (std::vector::const_iterator t = td.begin (); t != td.end (); ++t) { - device->connect_terminal (t->id (), nets [t - td.begin ()]); - } - - size_t defp = std::numeric_limits::max (); - if (dynamic_cast (cls)) { - defp = db::DeviceClassCapacitor::param_id_C; - } else if (dynamic_cast (cls)) { - defp = db::DeviceClassResistor::param_id_R; - } else if (dynamic_cast (cls)) { - defp = db::DeviceClassInductor::param_id_L; - } - - std::vector &pd = cls->parameter_definitions_non_const (); - for (std::vector::iterator i = pd.begin (); i != pd.end (); ++i) { - std::map::const_iterator v = params.find (i->name ()); - if (v != params.end ()) { - device->set_parameter_value (i->id (), v->second / i->si_scaling ()); - } else if (i->id () == defp) { - device->set_parameter_value (i->id (), value / i->si_scaling ()); - } - } - - return true; -} - // ------------------------------------------------------------------------------------------------------ -NetlistSpiceReader::SpiceReaderStream::SpiceReaderStream () +class SpiceReaderStream +{ +public: + SpiceReaderStream (); + ~SpiceReaderStream (); + + void set_stream (tl::InputStream &stream); + void set_stream (tl::InputStream *stream); + void close (); + + std::pair get_line(); + int line_number () const; + std::string source () const; + bool at_end () const; + + void swap (SpiceReaderStream &other) + { + std::swap (mp_stream, other.mp_stream); + std::swap (m_owns_stream, other.m_owns_stream); + std::swap (mp_text_stream, other.mp_text_stream); + std::swap (m_line_number, other.m_line_number); + std::swap (m_stored_line, other.m_stored_line); + std::swap (m_has_stored_line, other.m_has_stored_line); + } + +private: + tl::InputStream *mp_stream; + bool m_owns_stream; + tl::TextInputStream *mp_text_stream; + int m_line_number; + std::string m_stored_line; + bool m_has_stored_line; +}; + + +SpiceReaderStream::SpiceReaderStream () : mp_stream (0), m_owns_stream (false), mp_text_stream (0), m_line_number (0), m_stored_line (), m_has_stored_line (false) { // .. nothing yet .. } -NetlistSpiceReader::SpiceReaderStream::~SpiceReaderStream () +SpiceReaderStream::~SpiceReaderStream () { close (); } void -NetlistSpiceReader::SpiceReaderStream::close () +SpiceReaderStream::close () { delete mp_text_stream; mp_text_stream = 0; @@ -660,7 +131,7 @@ NetlistSpiceReader::SpiceReaderStream::close () } std::pair -NetlistSpiceReader::SpiceReaderStream::get_line () +SpiceReaderStream::get_line () { if (at_end ()) { return std::make_pair (std::string (), false); @@ -694,25 +165,25 @@ NetlistSpiceReader::SpiceReaderStream::get_line () } int -NetlistSpiceReader::SpiceReaderStream::line_number () const +SpiceReaderStream::line_number () const { return m_line_number; } std::string -NetlistSpiceReader::SpiceReaderStream::source () const +SpiceReaderStream::source () const { return mp_stream->source (); } bool -NetlistSpiceReader::SpiceReaderStream::at_end () const +SpiceReaderStream::at_end () const { return !m_has_stored_line && mp_text_stream->at_end (); } void -NetlistSpiceReader::SpiceReaderStream::set_stream (tl::InputStream &stream) +SpiceReaderStream::set_stream (tl::InputStream &stream) { close (); mp_stream = &stream; @@ -723,7 +194,7 @@ NetlistSpiceReader::SpiceReaderStream::set_stream (tl::InputStream &stream) } void -NetlistSpiceReader::SpiceReaderStream::set_stream (tl::InputStream *stream) +SpiceReaderStream::set_stream (tl::InputStream *stream) { close (); mp_stream = stream; @@ -735,118 +206,289 @@ NetlistSpiceReader::SpiceReaderStream::set_stream (tl::InputStream *stream) // ------------------------------------------------------------------------------------------------------ -NetlistSpiceReader::NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate) - : mp_netlist (0), mp_delegate (delegate), m_stream () +struct SpiceCard { - static NetlistSpiceReaderDelegate std_delegate; - if (! delegate) { - mp_delegate.reset (&std_delegate); + SpiceCard (int _file_id, int _line, const std::string &_text) + : file_id (_file_id), line (_line), text (_text) + { } + + int file_id; + int line; + std::string text; +}; + +class SpiceCachedCircuit +{ +public: + typedef std::list cards_type; + typedef cards_type::const_iterator cards_iterator; + typedef NetlistSpiceReader::parameters_type parameters_type; + typedef std::vector pin_list_type; + typedef pin_list_type::const_iterator pin_const_iterator; + + SpiceCachedCircuit (const std::string &name) + : m_name (name) + { + // .. nothing yet .. + } + + const std::string &name () const + { + return m_name; + } + + void set_parameters (const parameters_type &pv) + { + m_parameters = pv; + } + + const parameters_type ¶meters () const + { + return m_parameters; + } + + void make_parameter (const std::string &name, const tl::Variant &value) + { + for (auto p = m_pins.begin (); p != m_pins.end (); ++p) { + if (*p == name) { + // remove pin and make parameter + m_pins.erase (p); + break; + } + } + + m_parameters [name] = value; + } + + cards_iterator begin_cards () const + { + return m_cards.begin (); + } + + cards_iterator end_cards () const + { + return m_cards.end (); + } + + void add_card (const SpiceCard &card) + { + m_cards.push_back (card); + } + + size_t pin_count () const + { + return m_pins.size (); + } + + pin_const_iterator begin_pins () const + { + return m_pins.begin (); + } + + pin_const_iterator end_pins () const + { + return m_pins.end (); + } + + void set_pins (const pin_list_type &pins) + { + m_pins = pins; + } + + void set_pins (pin_list_type &&pins) + { + m_pins = std::move (pins); + } + +private: + std::string m_name; + parameters_type m_parameters; + pin_list_type m_pins; + cards_type m_cards; +}; + +static std::string +read_name (tl::Extractor &ex, const db::Netlist *netlist) +{ + std::string n; + ex.read_word_or_quoted (n, allowed_name_chars); + return netlist->normalize_name (n); +} + +class SpiceCircuitDict +{ +public: + typedef NetlistSpiceReader::parameters_type parameters_type; + typedef std::map circuits_type; + typedef circuits_type::const_iterator circuits_iterator; + typedef std::vector global_nets_type; + typedef global_nets_type::const_iterator global_nets_iterator; + + SpiceCircuitDict (NetlistSpiceReader *reader, Netlist *netlist, NetlistSpiceReaderDelegate *delegate); + ~SpiceCircuitDict (); + + void read (tl::InputStream &stream); + void finish (); + + circuits_iterator begin_circuits () const + { + return m_cached_circuits.begin (); + } + + circuits_iterator end_circuits () const + { + return m_cached_circuits.end (); + } + + bool is_top_circuit (const std::string &name) const + { + return m_called_circuits.find (name) == m_called_circuits.end (); + } + + const SpiceCachedCircuit *anonymous_top_level_circuit () const + { + return mp_anonymous_top_level_circuit; + } + + global_nets_iterator begin_global_nets () const + { + return m_global_nets.begin (); + } + + global_nets_iterator end_global_nets () const + { + return m_global_nets.end (); + } + + const std::string &file_path (int file_id) const; + + const SpiceCachedCircuit *cached_circuit (const std::string &name) const; + SpiceCachedCircuit *create_cached_circuit (const std::string &name); + +private: + NetlistSpiceReader *mp_reader; + Netlist *mp_netlist; + tl::weak_ptr mp_delegate; + std::vector m_paths; + std::map m_file_id_per_path; + std::list m_streams; + SpiceReaderStream m_stream; + int m_file_id; + std::map m_cached_circuits; + SpiceCachedCircuit *mp_circuit; + SpiceCachedCircuit *mp_anonymous_top_level_circuit; + std::set m_called_circuits; + NetlistSpiceReader::parameters_type m_variables; + std::set m_global_net_names; + std::vector m_global_nets; + + void push_stream (const std::string &path); + void pop_stream (); + bool at_end (); + void read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector &nets); + void read_circuit (tl::Extractor &ex, const std::string &name); + bool read_card (); + void ensure_circuit (); + std::string get_line (); + void error (const std::string &msg); + void warn (const std::string &msg); + int file_id (const std::string &path); +}; + +SpiceCircuitDict::SpiceCircuitDict (NetlistSpiceReader *reader, Netlist *netlist, NetlistSpiceReaderDelegate *delegate) + : mp_reader (reader), mp_netlist (netlist), mp_delegate (delegate) +{ + m_file_id = -1; + mp_circuit = mp_anonymous_top_level_circuit = 0; +} + +SpiceCircuitDict::~SpiceCircuitDict () +{ + for (auto c = m_cached_circuits.begin (); c != m_cached_circuits.end (); ++c) { + delete c->second; + } + m_cached_circuits.clear (); + + mp_reader = 0; + mp_delegate = 0; +} + +const std::string & +SpiceCircuitDict::file_path (int file_id) const +{ + if (file_id < 0 || file_id > int (m_paths.size ())) { + static std::string empty; + return empty; + } else { + return m_paths [file_id]; } } -NetlistSpiceReader::~NetlistSpiceReader () +int +SpiceCircuitDict::file_id (const std::string &path) { - // .. nothing yet .. + auto ip = m_file_id_per_path.find (path); + if (ip != m_file_id_per_path.end ()) { + return ip->second; + } + + int id = int (m_paths.size ()); + m_file_id_per_path.insert (std::make_pair (path, id)); + m_paths.push_back (path); + return id; } -void NetlistSpiceReader::read (tl::InputStream &stream, db::Netlist &netlist) +const SpiceCachedCircuit * +SpiceCircuitDict::cached_circuit (const std::string &name) const { - tl::SelfTimer timer (tl::verbosity () >= 21, tl::to_string (tr ("Reading netlist ")) + stream.source ()); + auto c = m_cached_circuits.find (name); + return c == m_cached_circuits.end () ? 0 : c->second; +} - m_stream.set_stream (stream); +SpiceCachedCircuit * +SpiceCircuitDict::create_cached_circuit (const std::string &name) +{ + auto c = m_cached_circuits.find (name); + if (c != m_cached_circuits.end ()) { + return c->second; + } - mp_netlist = &netlist; - mp_circuit = 0; - mp_anonymous_top_circuit = 0; - mp_nets_by_name.reset (0); - m_global_nets.clear (); - m_circuits_read.clear (); - - // SPICE netlists are case insensitive - netlist.set_case_sensitive (false); + SpiceCachedCircuit *cc = new SpiceCachedCircuit (name); + m_cached_circuits.insert (std::make_pair (name, cc)); + return cc; +} +void +SpiceCircuitDict::read (tl::InputStream &stream) +{ try { - mp_delegate->start (&netlist); + m_stream.set_stream (stream); + + mp_circuit = 0; + mp_anonymous_top_level_circuit = 0; + m_called_circuits.clear (); + m_variables.clear (); + m_global_net_names.clear (); + m_global_nets.clear (); + + m_file_id = file_id (stream.source ()); while (! at_end ()) { read_card (); } - build_global_nets (); - - mp_delegate->finish (&netlist); - finish (); - } catch (tl::Exception &ex) { - // NOTE: because we do a peek to capture the "+" line continuation character, we're - // one line ahead. - std::string fmt_msg = tl::sprintf ("%s in %s, line %d", ex.msg (), m_stream.source (), m_stream.line_number ()); - finish (); + // Add a location to the exception + std::string fmt_msg = ex.msg () + tl::sprintf (tl::to_string (tr (" in %s, line %d")), m_stream.source (), m_stream.line_number ()); throw tl::Exception (fmt_msg); - } catch (...) { - - finish (); - throw; - } } -void NetlistSpiceReader::build_global_nets () -{ - for (std::vector::const_iterator gn = m_global_nets.begin (); gn != m_global_nets.end (); ++gn) { - - for (db::Netlist::bottom_up_circuit_iterator c = mp_netlist->begin_bottom_up (); c != mp_netlist->end_bottom_up (); ++c) { - - if (c.operator-> () == mp_anonymous_top_circuit) { - // no pins for the anonymous top circuit - continue; - } - - db::Net *net = c->net_by_name (*gn); - if (! net || net->pin_count () > 0) { - // only add a pin for a global net if there is a net with this name - // don't add a pin if it already has one - continue; - } - - const db::Pin &pin = c->add_pin (*gn); - c->connect_pin (pin.id (), net); - - for (db::Circuit::refs_iterator r = c->begin_refs (); r != c->end_refs (); ++r) { - - db::SubCircuit &sc = *r; - - db::Net *pnet = sc.circuit ()->net_by_name (*gn); - if (! pnet) { - pnet = new db::Net (); - pnet->set_name (*gn); - sc.circuit ()->add_net (pnet); - } - - sc.connect_pin (pin.id (), pnet); - - } - - } - - } -} - - -void NetlistSpiceReader::finish () -{ - m_streams.clear (); - m_stream.close (); - - mp_netlist = 0; - mp_circuit = 0; - mp_nets_by_name.reset (0); -} - -void NetlistSpiceReader::push_stream (const std::string &path) +void +SpiceCircuitDict::push_stream (const std::string &path) { tl::URI current_uri (m_stream.source ()); tl::URI new_uri (path); @@ -865,22 +507,44 @@ void NetlistSpiceReader::push_stream (const std::string &path) m_streams.push_back (SpiceReaderStream ()); m_streams.back ().swap (m_stream); m_stream.set_stream (istream); + + m_file_id = file_id (m_stream.source ()); } -void NetlistSpiceReader::pop_stream () +void +SpiceCircuitDict::pop_stream () { if (! m_streams.empty ()) { + m_stream.swap (m_streams.back ()); m_streams.pop_back (); + + m_file_id = file_id (m_stream.source ()); + } } -bool NetlistSpiceReader::at_end () +bool +SpiceCircuitDict::at_end () { return m_stream.at_end () && m_streams.empty (); } -std::string NetlistSpiceReader::get_line () +void +SpiceCircuitDict::error (const std::string &msg) +{ + throw tl::Exception (msg); +} + +void +SpiceCircuitDict::warn (const std::string &msg) +{ + std::string fmt_msg = tl::sprintf ("%s in %s, line %d", msg, m_stream.source (), m_stream.line_number ()); + tl::warn << fmt_msg; +} + +std::string +SpiceCircuitDict::get_line () { std::pair lp; @@ -920,19 +584,8 @@ std::string NetlistSpiceReader::get_line () return lp.first; } -bool NetlistSpiceReader::subcircuit_captured (const std::string &nc_name) -{ - std::map::const_iterator c = m_captured.find (nc_name); - if (c != m_captured.end ()) { - return c->second; - } else { - bool cap = mp_delegate->wants_subcircuit (nc_name); - m_captured.insert (std::make_pair (nc_name, cap)); - return cap; - } -} - -bool NetlistSpiceReader::read_card () +bool +SpiceCircuitDict::read_card () { std::string l = get_line (); if (l.empty ()) { @@ -940,45 +593,45 @@ bool NetlistSpiceReader::read_card () } tl::Extractor ex (l.c_str ()); + std::string name; - ex.skip (); - char next_char = toupper (*ex); + if (ex.test_without_case (".model")) { - if (ex.test_without_case (".")) { + // ignore model statements - // control statement - if (ex.test_without_case ("model")) { + } else if (ex.test_without_case (".global")) { - // ignore model statements - - } else if (ex.test_without_case ("global")) { - - while (! ex.at_end ()) { - std::string n = mp_delegate->translate_net_name (read_name (ex)); - if (m_global_net_names.find (n) == m_global_net_names.end ()) { - m_global_nets.push_back (n); - m_global_net_names.insert (n); - } + while (! ex.at_end ()) { + std::string n = mp_delegate->translate_net_name (read_name (ex, mp_netlist)); + if (m_global_net_names.find (n) == m_global_net_names.end ()) { + m_global_nets.push_back (n); + m_global_net_names.insert (n); } + } - } else if (ex.test_without_case ("subckt")) { + } else if (ex.test_without_case (".subckt")) { - std::string nc = read_name (ex); - if (subcircuit_captured (nc)) { - skip_circuit (ex); - } else { - read_circuit (ex, nc); - } + std::string nc = read_name (ex, mp_netlist); + read_circuit (ex, nc); - } else if (ex.test_without_case ("ends")) { + } else if (ex.test_without_case (".ends")) { - return true; + return true; - } else if (ex.test_without_case ("end")) { + } else if (ex.test_without_case (".end")) { - // ignore end statements + // ignore end statements - } else if (! mp_delegate->control_statement (l)) { + } else if (ex.test_without_case (".param")) { + + read_param_card (ex, mp_netlist, m_variables); + + ensure_circuit (); + mp_circuit->add_card (SpiceCard (m_file_id, m_stream.line_number (), l)); + + } else if (ex.test (".")) { + + if (! mp_delegate->control_statement (l)) { std::string s; ex.read_word (s); @@ -987,20 +640,39 @@ bool NetlistSpiceReader::read_card () } - } else if (isalpha (next_char)) { + } else if (ex.try_read_word (name)) { - ++ex; - - std::string name = read_name (ex); ensure_circuit (); - std::string es; - es.push_back (next_char); + if (ex.test ("=")) { + + name = mp_netlist->normalize_name (name); + + tl::Variant value = NetlistSpiceReaderDelegate::read_value (ex, m_variables); + m_variables [name] = value; + + mp_circuit->make_parameter (name, value); + + } else if (name[0] == 'X') { + + // register circuit calls so we can figure out the top level circuits + + tl::Extractor ex2 (l.c_str ()); + ex2.skip (); + ++ex2; + + std::vector nn; + parameters_type pv; + mp_delegate->parse_element_components (ex2.get (), nn, pv, m_variables); + + if (! nn.empty ()) { + m_called_circuits.insert (nn.back ()); + } - if (! read_element (ex, es, name)) { - warn (tl::sprintf (tl::to_string (tr ("Element type '%c' ignored")), next_char)); } + mp_circuit->add_card (SpiceCard (m_file_id, m_stream.line_number (), l)); + } else { warn (tl::to_string (tr ("Line ignored"))); } @@ -1008,31 +680,293 @@ bool NetlistSpiceReader::read_card () return false; } -void NetlistSpiceReader::error (const std::string &msg) -{ - throw tl::Exception (msg); -} - -void NetlistSpiceReader::warn (const std::string &msg) -{ - std::string fmt_msg = tl::sprintf ("%s in %s, line %d", msg, m_stream.source (), m_stream.line_number ()); - tl::warn << fmt_msg; -} - -void NetlistSpiceReader::ensure_circuit () +void +SpiceCircuitDict::ensure_circuit () { if (! mp_circuit) { - mp_circuit = new db::Circuit (); // TODO: make top name configurable - mp_circuit->set_name (".TOP"); - mp_anonymous_top_circuit = mp_circuit; - mp_netlist->add_circuit (mp_circuit); + mp_circuit = new SpiceCachedCircuit (".TOP"); + m_cached_circuits.insert (std::make_pair (mp_circuit->name (), mp_circuit)); + + mp_anonymous_top_level_circuit = mp_circuit; } } -db::Net *NetlistSpiceReader::make_net (const std::string &name) +void +SpiceCircuitDict::read_circuit (tl::Extractor &ex, const std::string &nc) +{ + std::vector nn; + NetlistSpiceReader::parameters_type pv; + mp_delegate->parse_element_components (ex.skip (), nn, pv, m_variables); + + if (cached_circuit (nc)) { + error (tl::sprintf (tl::to_string (tr ("Redefinition of circuit %s")), nc)); + } + + SpiceCachedCircuit *cc = create_cached_circuit (nc); + cc->set_pins (nn); + cc->set_parameters (pv); + + std::swap (cc, mp_circuit); + NetlistSpiceReader::parameters_type vars = pv; + m_variables.swap (vars); + + while (! at_end ()) { + if (read_card ()) { + break; + } + } + + std::swap (cc, mp_circuit); + m_variables.swap (vars); +} + +void +SpiceCircuitDict::finish () +{ + m_streams.clear (); + m_stream.close (); +} + +// ------------------------------------------------------------------------------------------------------ + +class SpiceNetlistBuilder +{ +public: + typedef NetlistSpiceReader::parameters_type parameters_type; + + SpiceNetlistBuilder (SpiceCircuitDict *dict, Netlist *netlist, NetlistSpiceReaderDelegate *delegate); + + void set_strict (bool s) + { + m_strict = s; + } + + void build (); + +private: + SpiceCircuitDict *mp_dict; + tl::weak_ptr mp_delegate; + Netlist *mp_netlist; + bool m_strict; + const SpiceCachedCircuit *mp_circuit; + std::map > m_circuits; + db::Circuit *mp_netlist_circuit; + db::Circuit *mp_anonymous_top_level_netlist_circuit; + std::unique_ptr > mp_nets_by_name; + std::map m_captured; + NetlistSpiceReader::parameters_type m_variables; + const SpiceCard *mp_current_card; + + db::Circuit *circuit_for (const SpiceCachedCircuit *cached_circuit, const parameters_type &pv); + void register_circuit_for (const SpiceCachedCircuit *cc, const parameters_type &pv, db::Circuit *circuit, bool anonymous_top_level); + Circuit *build_circuit (const SpiceCachedCircuit *circuit, const parameters_type &pv, bool anonymous_top_level = false); + std::string get_line (); + void error (const std::string &msg); + void warn (const std::string &msg); + Net *make_net(const std::string &name); + void process_card (const SpiceCard &card); + bool subcircuit_captured (const std::string &nc_name); + bool process_element (tl::Extractor &ex, const std::string &prefix, const std::string &name); + void build_global_nets (); +}; + +SpiceNetlistBuilder::SpiceNetlistBuilder (SpiceCircuitDict *dict, Netlist *netlist, NetlistSpiceReaderDelegate *delegate) + : mp_dict (dict), mp_delegate (delegate), mp_netlist (netlist), m_strict (true) +{ + mp_circuit = 0; + mp_netlist_circuit = 0; + mp_anonymous_top_level_netlist_circuit = 0; + mp_current_card = 0; +} + +void +SpiceNetlistBuilder::error (const std::string &msg) +{ + throw tl::Exception (msg); +} + +void +SpiceNetlistBuilder::warn (const std::string &msg) +{ + if (mp_current_card) { + std::string fmt_msg = tl::sprintf ("%s in %s, line %d", msg, mp_dict->file_path (mp_current_card->file_id), mp_current_card->line); + tl::warn << fmt_msg; + } else { + tl::warn << msg; + } +} + +db::Circuit * +SpiceNetlistBuilder::circuit_for (const SpiceCachedCircuit *cc, const parameters_type &pv) +{ + auto c = m_circuits.find (cc); + if (c == m_circuits.end ()) { + return 0; + } + auto cp = c->second.find (pv); + if (cp == c->second.end ()) { + return 0; + } + return cp->second; +} + +void +SpiceNetlistBuilder::register_circuit_for (const SpiceCachedCircuit *cc, const parameters_type &pv, db::Circuit *circuit, bool anonymous_top_level) +{ + m_circuits [cc][pv] = circuit; + if (anonymous_top_level) { + mp_anonymous_top_level_netlist_circuit = circuit; + } +} + +void +SpiceNetlistBuilder::build () +{ + try { + + m_variables.clear (); + mp_netlist_circuit = 0; + mp_anonymous_top_level_netlist_circuit = 0; + mp_circuit = 0; + mp_current_card = 0; + m_captured.clear (); + + mp_delegate->do_start (); + + for (auto c = mp_dict->begin_circuits (); c != mp_dict->end_circuits (); ++c) { + if (mp_dict->is_top_circuit (c->first) && ! subcircuit_captured (c->first)) { + // we have a top circuit candidate + build_circuit (c->second, c->second->parameters (), c->second == mp_dict->anonymous_top_level_circuit ()); + } + } + + build_global_nets (); + mp_delegate->do_finish (); + + } catch (tl::Exception &ex) { + + // add a source location to the exception + if (mp_current_card) { + std::string fmt_msg = ex.msg () + tl::sprintf (tl::to_string (tr (" in %s, line %d")), mp_dict->file_path (mp_current_card->file_id), mp_current_card->line); + throw tl::Exception (fmt_msg); + } else { + throw; + } + + } +} + +static std::string +make_circuit_name (const std::string &name, const NetlistSpiceReader::parameters_type &pv) +{ + std::string res = name; + + res += "("; + for (auto p = pv.begin (); p != pv.end (); ++p) { + if (p != pv.begin ()) { + res += ","; + } + res += p->first; + res += "="; + if (p->second.can_convert_to_double()) { + double v = p->second.to_double (); + double va = fabs (v); + if (va < 1e-15) { + res += tl::sprintf ("%g", v); + } else if (va < 0.1e-12) { + res += tl::sprintf ("%gF", v * 1e15); + } else if (va < 0.1e-9) { + res += tl::sprintf ("%gP", v * 1e12); + } else if (va < 0.1e-6) { + res += tl::sprintf ("%gN", v * 1e9); + } else if (va < 0.1e-3) { + res += tl::sprintf ("%gU", v * 1e6); + } else if (va< 0.1) { + res += tl::sprintf ("%gM", v * 1e3); + } else if (va < 0.1e3) { + res += tl::sprintf ("%g", v); + } else if (va < 0.1e6) { + res += tl::sprintf ("%gK", v * 1e-3); + } else if (va < 0.1e9) { + res += tl::sprintf ("%gMEG", v * 1e-6); + } else if (va < 0.1e12) { + res += tl::sprintf ("%gG", v * 1e-9); + } else { + res += tl::sprintf ("%g", v); + } + } else { + res += p->second.to_string (); + } + } + res += ")"; + + return res; +} + +db::Circuit * +SpiceNetlistBuilder::build_circuit (const SpiceCachedCircuit *cc, const parameters_type &pv, bool anonymous_top_level) +{ + db::Circuit *c = circuit_for (cc, pv); + if (c) { + return c; + } + + c = new db::Circuit (); + mp_netlist->add_circuit (c); + if (pv.empty ()) { + c->set_name (cc->name ()); + } else { + c->set_name (make_circuit_name (cc->name (), pv)); + } + + register_circuit_for (cc, pv, c, anonymous_top_level); + + std::unique_ptr > n2n (mp_nets_by_name.release ()); + mp_nets_by_name.reset (0); + + NetlistSpiceReader::parameters_type vars = cc->parameters (); + for (auto p = pv.begin (); p != pv.end (); ++p) { + vars [p->first] = p->second; + } + + std::swap (vars, m_variables); + std::swap (c, mp_netlist_circuit); + std::swap (cc, mp_circuit); + + // produce the explicit pins + for (auto i = mp_circuit->begin_pins (); i != mp_circuit->end_pins (); ++i) { + std::string net_name = mp_delegate->translate_net_name (mp_netlist->normalize_name (*i)); + db::Net *net = make_net (net_name); + // use the net name to name the pin (otherwise SPICE pins are always unnamed) + size_t pin_id = i - mp_circuit->begin_pins (); + if (! i->empty ()) { + mp_netlist_circuit->add_pin (net->name ()); + } else { + mp_netlist_circuit->add_pin (std::string ()); + } + mp_netlist_circuit->connect_pin (pin_id, net); + } + + for (auto card = mp_circuit->begin_cards (); card != mp_circuit->end_cards (); ++card) { + mp_current_card = card.operator-> (); + process_card (*card); + } + + mp_current_card = 0; + mp_nets_by_name.reset (n2n.release ()); + + std::swap (cc, mp_circuit); + std::swap (c, mp_netlist_circuit); + std::swap (vars, m_variables); + + return c; +} + +db::Net * +SpiceNetlistBuilder::make_net (const std::string &name) { if (! mp_nets_by_name.get ()) { mp_nets_by_name.reset (new std::map ()); @@ -1045,7 +979,7 @@ db::Net *NetlistSpiceReader::make_net (const std::string &name) net = new db::Net (); net->set_name (name); - mp_circuit->add_net (net); + mp_netlist_circuit->add_net (net); mp_nets_by_name->insert (std::make_pair (name, net)); @@ -1056,84 +990,152 @@ db::Net *NetlistSpiceReader::make_net (const std::string &name) return net; } -std::string NetlistSpiceReader::read_name (tl::Extractor &ex) +void +SpiceNetlistBuilder::process_card (const SpiceCard &card) { - std::string n; - ex.read_word_or_quoted (n, allowed_name_chars); - return mp_netlist->normalize_name (n); + tl::Extractor ex (card.text.c_str ()); + + std::string name; + if (ex.try_read_word (name) && ex.test ("=")) { + + m_variables.insert (std::make_pair (mp_netlist->normalize_name (name), NetlistSpiceReaderDelegate::read_value (ex, m_variables))); + + } else { + + ex = tl::Extractor (card.text.c_str ()); + ex.skip (); + + if (ex.test_without_case (".param")) { + + read_param_card (ex, mp_netlist, m_variables); + + } else if (isalpha (*ex)) { + + std::string prefix; + prefix.push_back (toupper (*ex)); + + ++ex; + name = read_name (ex, mp_netlist); + + if (! process_element (ex, prefix, name)) { + warn (tl::sprintf (tl::to_string (tr ("Element type '%s' ignored")), prefix)); + } + + } else { + warn (tl::to_string (tr ("Line ignored"))); + } + + } } -bool NetlistSpiceReader::read_element (tl::Extractor &ex, const std::string &element, const std::string &name) +bool +SpiceNetlistBuilder::subcircuit_captured (const std::string &nc_name) +{ + std::map::const_iterator c = m_captured.find (nc_name); + if (c != m_captured.end ()) { + return c->second; + } else { + bool cap = mp_delegate->wants_subcircuit (nc_name); + m_captured.insert (std::make_pair (nc_name, cap)); + return cap; + } +} + +bool +SpiceNetlistBuilder::process_element (tl::Extractor &ex, const std::string &prefix, const std::string &name) { // generic parse std::vector nn; - std::map pv; + NetlistSpiceReader::parameters_type pv; std::string model; double value = 0.0; - mp_delegate->parse_element (ex.skip (), element, model, value, nn, pv); + mp_delegate->parse_element (ex.skip (), prefix, model, value, nn, pv, m_variables); model = mp_netlist->normalize_name (model); std::vector nets; for (std::vector::const_iterator i = nn.begin (); i != nn.end (); ++i) { - nets.push_back (make_net (mp_delegate->translate_net_name (mp_netlist->normalize_name (*i)))); + nets.push_back (make_net (mp_delegate->translate_net_name (*i))); } - if (element == "X" && ! subcircuit_captured (model)) { - if (! pv.empty ()) { - warn (tl::to_string (tr ("Circuit parameters are not allowed currently"))); - } - read_subcircuit (name, model, nets); - return true; - } else { - return mp_delegate->element (mp_circuit, element, name, model, value, nets, pv); - } -} + if (prefix == "X" && ! subcircuit_captured (model)) { -void NetlistSpiceReader::read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector &nets) -{ - db::Circuit *cc = mp_netlist->circuit_by_name (nc_name); - if (! cc) { - - cc = new db::Circuit (); - mp_netlist->add_circuit (cc); - cc->set_name (nc_name); - - // we'll make the names later ... - for (std::vector::const_iterator i = nets.begin (); i != nets.end (); ++i) { - cc->add_pin (std::string ()); + const db::SpiceCachedCircuit *cc = mp_dict->cached_circuit (model); + if (! cc) { + if (m_strict) { + error (tl::sprintf (tl::to_string (tr ("Subcircuit '%s' not found in netlist")), model)); + } else { + db::SpiceCachedCircuit *cc_nc = mp_dict->create_cached_circuit (model); + cc = cc_nc; + std::vector pins; + pins.resize (nn.size ()); + cc_nc->set_pins (pins); + } + } else { + // issue warnings on unknown parameters which are skipped otherwise + for (auto p = pv.begin (); p != pv.end (); ++p) { + if (cc->parameters ().find (p->first) == cc->parameters ().end ()) { + warn (tl::sprintf (tl::to_string (tr ("Not a known parameter for circuit '%s': '%s'")), cc->name (), p->first)); + } + } } - } else { - - if (cc->pin_count () != nets.size ()) { + if (cc->pin_count () != nn.size ()) { error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between circuit definition and circuit call: %d expected, got %d")), int (cc->pin_count ()), int (nets.size ()))); } - } + db::Circuit *c = build_circuit (cc, pv); - db::SubCircuit *sc = new db::SubCircuit (cc, sc_name); - mp_circuit->add_subcircuit (sc); + db::SubCircuit *sc = new db::SubCircuit (c, name); + mp_netlist_circuit->add_subcircuit (sc); - for (std::vector::const_iterator i = nets.begin (); i != nets.end (); ++i) { - sc->connect_pin (i - nets.begin (), *i); + for (std::vector::const_iterator i = nets.begin (); i != nets.end (); ++i) { + sc->connect_pin (i - nets.begin (), *i); + } + + return true; + + } else { + return mp_delegate->element (mp_netlist_circuit, prefix, name, model, value, nets, pv); } } -void NetlistSpiceReader::skip_circuit (tl::Extractor & /*ex*/) +void +SpiceNetlistBuilder::build_global_nets () { - while (! at_end ()) { + for (auto gn = mp_dict->begin_global_nets (); gn != mp_dict->end_global_nets (); ++gn) { - std::string l = get_line (); - tl::Extractor ex (l.c_str ()); - if (ex.test_without_case (".")) { + for (auto c = mp_netlist->begin_bottom_up (); c != mp_netlist->end_bottom_up (); ++c) { + + if (c.operator-> () == mp_anonymous_top_level_netlist_circuit) { + // no pins for the anonymous top circuit + continue; + } + + db::Net *net = c->net_by_name (*gn); + if (! net || net->pin_count () > 0) { + // only add a pin for a global net if there is a net with this name + // don't add a pin if it already has one + continue; + } + + const db::Pin &pin = c->add_pin (*gn); + c->connect_pin (pin.id (), net); + + for (db::Circuit::refs_iterator r = c->begin_refs (); r != c->end_refs (); ++r) { + + db::SubCircuit &sc = *r; + + db::Net *pnet = sc.circuit ()->net_by_name (*gn); + if (! pnet) { + pnet = new db::Net (); + pnet->set_name (*gn); + sc.circuit ()->add_net (pnet); + } + + sc.connect_pin (pin.id (), pnet); - // control statement - if (ex.test_without_case ("subckt")) { - skip_circuit (ex); - } else if (ex.test_without_case ("ends")) { - break; } } @@ -1141,67 +1143,52 @@ void NetlistSpiceReader::skip_circuit (tl::Extractor & /*ex*/) } } -void NetlistSpiceReader::read_circuit (tl::Extractor &ex, const std::string &nc) +// ------------------------------------------------------------------------------------------------------ + +NetlistSpiceReader::NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate) + : mp_delegate (delegate), m_strict (false) { - std::vector nn; - std::map pv; - mp_delegate->parse_element_components (ex.skip (), nn, pv); - - for (std::vector::iterator i = nn.begin (); i != nn.end (); ++i) { - *i = mp_delegate->translate_net_name (mp_netlist->normalize_name (*i)); + static NetlistSpiceReaderDelegate std_delegate; + if (! delegate) { + mp_delegate.reset (&std_delegate); } +} - if (! pv.empty ()) { - warn (tl::to_string (tr ("Circuit parameters are not allowed currently"))); - } +NetlistSpiceReader::~NetlistSpiceReader () +{ + // .. nothing yet .. +} - db::Circuit *cc = mp_netlist->circuit_by_name (nc); - if (! cc) { +void NetlistSpiceReader::read (tl::InputStream &stream, db::Netlist &netlist) +{ + tl::SelfTimer timer (tl::verbosity () >= 21, tl::to_string (tr ("Reading netlist ")) + stream.source ()); - cc = new db::Circuit (); - mp_netlist->add_circuit (cc); - cc->set_name (nc); - for (std::vector::const_iterator i = nn.begin (); i != nn.end (); ++i) { - cc->add_pin (std::string ()); + try { + + mp_delegate->set_netlist (&netlist); + + // SPICE netlists are case insensitive + netlist.set_case_sensitive (false); + + SpiceCircuitDict dict (this, &netlist, mp_delegate.get ()); + try { + dict.read (stream); + dict.finish (); + } catch (...) { + dict.finish (); + throw; } - } else { + SpiceNetlistBuilder builder (&dict, &netlist, mp_delegate.get ()); + builder.set_strict (m_strict); + builder.build (); - if (cc->pin_count () != nn.size ()) { - error (tl::sprintf (tl::to_string (tr ("Pin count mismatch between implicit (through call) and explicit circuit definition: %d expected, got %d in circuit %s")), int (cc->pin_count ()), int (nn.size ()), nc)); - } + mp_delegate->set_netlist (0); + } catch (...) { + mp_delegate->set_netlist (0); + throw; } - - if (m_circuits_read.find (cc) != m_circuits_read.end ()) { - error (tl::sprintf (tl::to_string (tr ("Redefinition of circuit %s")), nc)); - } - m_circuits_read.insert (cc); - - std::unique_ptr > n2n (mp_nets_by_name.release ()); - mp_nets_by_name.reset (0); - - std::swap (cc, mp_circuit); - - // produce the explicit pins - for (std::vector::const_iterator i = nn.begin (); i != nn.end (); ++i) { - db::Net *net = make_net (*i); - // use the net name to name the pin (otherwise SPICE pins are always unnamed) - size_t pin_id = i - nn.begin (); - if (! i->empty ()) { - mp_circuit->rename_pin (pin_id, net->name ()); - } - mp_circuit->connect_pin (pin_id, net); - } - - while (! at_end ()) { - if (read_card ()) { - break; - } - } - - mp_nets_by_name.reset (n2n.release ()); - std::swap (cc, mp_circuit); } } diff --git a/src/db/db/dbNetlistSpiceReader.h b/src/db/db/dbNetlistSpiceReader.h index 45d273939..2d8bce4c3 100644 --- a/src/db/db/dbNetlistSpiceReader.h +++ b/src/db/db/dbNetlistSpiceReader.h @@ -25,136 +25,19 @@ #include "dbCommon.h" #include "dbNetlistReader.h" -#include "tlStream.h" -#include -#include +#include "tlStream.h" +#include "tlObject.h" +#include "tlVariant.h" + #include -#include -#include +#include namespace db { class Netlist; -class Net; -class Circuit; -class DeviceClass; -class Device; - -/** - * @brief A specialized exception class to handle netlist reader delegate errors - */ -class DB_PUBLIC NetlistSpiceReaderDelegateError - : public tl::Exception -{ -public: - NetlistSpiceReaderDelegateError (const std::string &msg) - : tl::Exception (msg) - { } -}; - -/** - * @brief A delegate to handle various forms of devices and translates them - * - * The reader delegate can be configured to receive subcircuit elements too. - * In this case, parameters are allowed. - * For receiving subcircuit elements, the delegate needs to indicate - * this by returning true upon "wants_subcircuit". - */ -class DB_PUBLIC NetlistSpiceReaderDelegate - : public tl::Object -{ -public: - NetlistSpiceReaderDelegate (); - virtual ~NetlistSpiceReaderDelegate (); - - /** - * @brief Called when the netlist reading starts - */ - virtual void start (db::Netlist *netlist); - - /** - * @brief Called when the netlist reading ends - */ - virtual void finish (db::Netlist *netlist); - - /** - * @brief Called when an unknown control statement is encountered - * - * Returns true if the statement is understood. - */ - virtual bool control_statement (const std::string &line); - - /** - * @brief Returns true, if the delegate wants subcircuit elements with this name - * - * The name is always upper case. - */ - virtual bool wants_subcircuit (const std::string &circuit_name); - - /** - * @brief This method translates a raw net name to a valid net name - * - * The default implementation will unescape backslash sequences into plain characters. - */ - virtual std::string translate_net_name (const std::string &nn); - - /** - * @brief Makes a device from an element line - * - * @param circuit The circuit that is currently read. - * @param element The upper-case element code ("M", "R", ...). - * @param name The element's name. - * @param model The upper-case model name (may be empty). - * @param value The default value (e.g. resistance for resistors) and may be zero. - * @param nets The nets given in the element line. - * @param parameters The parameters of the element statement (parameter names are upper case). - * - * The default implementation will create corresponding devices for - * some known elements using the Spice writer's parameter conventions. - * - * This method returns true, if the element was read. - */ - virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms); - - /** - * @brief Parses an element from a line - * - * @param s The line to parse (the part after the element and name) - * @param model Out parameter: the model name if given - * @param value Out parameter: the value if given (for R, L, C) - * @param nn Out parameter: the net names - * @param pv Out parameter: the parameter values (key/value pairs) - */ - virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, std::map &pv); - - /** - * @brief Produces an error with the given message - */ - virtual void error (const std::string &msg); - - /** - * @brief Reads a set of string components and parameters from the string - * A special key "param:" is recognized for starting a parameter list. - */ - void parse_element_components (const std::string &s, std::vector &strings, std::map &pv); - - /** - * @brief Reads a value from the extractor (with formula evaluation) - */ - double read_value (tl::Extractor &ex); - - /** - * @brief Tries to read a value from the extractor (with formula evaluation) - */ - bool try_read_value (const std::string &s, double &v); - -private: - double read_atomic_value (tl::Extractor &ex); - double read_dot_expr (tl::Extractor &ex); - double read_bar_expr (tl::Extractor &ex); -}; +class NetlistSpiceReaderDelegate; /** * @brief A SPICE format reader for netlists @@ -163,76 +46,25 @@ class DB_PUBLIC NetlistSpiceReader : public NetlistReader { public: + typedef std::map parameters_type; + NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate = 0); virtual ~NetlistSpiceReader (); virtual void read (tl::InputStream &stream, db::Netlist &netlist); -private: - - class SpiceReaderStream + /** + * @brief Sets or resets strict mode + * In strict mode, all subcircuits need to be present in the net list for example. + */ + void set_strict (bool s) { - public: - SpiceReaderStream (); - ~SpiceReaderStream (); + m_strict = s; + } - void set_stream (tl::InputStream &stream); - void set_stream (tl::InputStream *stream); - void close (); - - std::pair get_line(); - int line_number () const; - std::string source () const; - bool at_end () const; - - void swap (SpiceReaderStream &other) - { - std::swap (mp_stream, other.mp_stream); - std::swap (m_owns_stream, other.m_owns_stream); - std::swap (mp_text_stream, other.mp_text_stream); - std::swap (m_line_number, other.m_line_number); - std::swap (m_stored_line, other.m_stored_line); - std::swap (m_has_stored_line, other.m_has_stored_line); - } - - private: - tl::InputStream *mp_stream; - bool m_owns_stream; - tl::TextInputStream *mp_text_stream; - int m_line_number; - std::string m_stored_line; - bool m_has_stored_line; - }; - - db::Netlist *mp_netlist; - db::Circuit *mp_circuit; - db::Circuit *mp_anonymous_top_circuit; +private: tl::weak_ptr mp_delegate; - std::list m_streams; - SpiceReaderStream m_stream; - std::unique_ptr > mp_nets_by_name; - std::map m_captured; - std::vector m_global_nets; - std::set m_global_net_names; - std::set m_circuits_read; - - void push_stream (const std::string &path); - void pop_stream (); - bool at_end (); - bool read_element (tl::Extractor &ex, const std::string &element, const std::string &name); - void read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector &nets); - void read_circuit (tl::Extractor &ex, const std::string &name); - void skip_circuit (tl::Extractor &ex); - bool read_card (); - std::string read_name (tl::Extractor &ex); - std::string get_line (); - void error (const std::string &msg); - void warn (const std::string &msg); - void finish (); - db::Net *make_net (const std::string &name); - void ensure_circuit (); - bool subcircuit_captured (const std::string &nc_name); - void build_global_nets (); + bool m_strict; }; } diff --git a/src/db/db/dbNetlistSpiceReaderDelegate.cc b/src/db/db/dbNetlistSpiceReaderDelegate.cc new file mode 100644 index 000000000..45e45d70d --- /dev/null +++ b/src/db/db/dbNetlistSpiceReaderDelegate.cc @@ -0,0 +1,588 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2023 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include "dbNetlistSpiceReaderDelegate.h" +#include "dbNetlistSpiceReader.h" +#include "dbNetlistSpiceReaderExpressionParser.h" +#include "dbNetlist.h" +#include "dbCircuit.h" +#include "dbNetlistDeviceClasses.h" + +namespace db +{ + +// ------------------------------------------------------------------------------------------------------ + +inline static int hex_num (char c) +{ + if (c >= '0' && c <= '9') { + return (int (c - '0')); + } else if (c >= 'a' && c <= 'f') { + return (int (c - 'f') + 10); + } else { + return -1; + } +} + +static std::string unescape_name (const std::string &n) +{ + std::string nn; + nn.reserve (n.size ()); + + const char *cp = n.c_str (); + while (*cp) { + + if (*cp == '\\' && cp[1]) { + + if (tolower (cp[1]) == 'x') { + + cp += 2; + + char c = 0; + for (int i = 0; i < 2 && *cp; ++i) { + int n = hex_num (*cp); + if (n >= 0) { + ++cp; + c = c * 16 + char (n); + } else { + break; + } + } + + nn += c; + + } else { + ++cp; + nn += *cp++; + } + + } else { + nn += *cp++; + } + + } + + return nn; +} + +// ------------------------------------------------------------------------------------------------------ + +NetlistSpiceReaderDelegate::NetlistSpiceReaderDelegate () + : mp_netlist (0) +{ + // .. nothing yet .. +} + +NetlistSpiceReaderDelegate::~NetlistSpiceReaderDelegate () +{ + // .. nothing yet .. +} + +void NetlistSpiceReaderDelegate::start (db::Netlist * /*netlist*/) +{ + // .. nothing yet .. +} + +void NetlistSpiceReaderDelegate::finish (db::Netlist * /*netlist*/) +{ + // .. nothing yet .. +} + +bool NetlistSpiceReaderDelegate::control_statement(const std::string & /*line*/) +{ + return false; +} + +bool NetlistSpiceReaderDelegate::wants_subcircuit (const std::string & /*circuit_name*/) +{ + return false; +} + +std::string NetlistSpiceReaderDelegate::translate_net_name (const std::string &nn) +{ + return unescape_name (nn); +} + +void NetlistSpiceReaderDelegate::error (const std::string &msg) +{ + throw tl::Exception (msg); +} + +template +static db::DeviceClass *make_device_class (db::Circuit *circuit, const std::string &name) +{ + if (! circuit || ! circuit->netlist ()) { + return 0; + } + + db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (name); + if (! cls) { + cls = new Cls (); + cls->set_name (name); + circuit->netlist ()->add_device_class (cls); + } + + return cls; +} + +static std::string parse_component (tl::Extractor &ex) +{ + const char *cp = ex.skip (); + const char *cp0 = cp; + + char quote = 0; + unsigned int brackets = 0; + + while (*cp) { + if (quote) { + if (*cp == quote) { + quote = 0; + } else if (*cp == '\\' && cp[1]) { + ++cp; + } + } else if ((isspace (*cp) || *cp == '=') && ! brackets) { + break; + } else if (*cp == '"' || *cp == '\'') { + quote = *cp; + } else if (*cp == '(') { + ++brackets; + } else if (*cp == ')') { + if (brackets > 0) { + --brackets; + } + } + ++cp; + } + + ex = tl::Extractor (cp); + return std::string (cp0, cp - cp0); +} + +void NetlistSpiceReaderDelegate::parse_element_components (const std::string &s, std::vector &strings, std::map &pv, const std::map &variables) +{ + tl::Extractor ex (s.c_str ()); + bool in_params = false; + + while (! ex.at_end ()) { + + if (ex.test_without_case ("params:")) { + + in_params = true; + + } else { + + tl::Extractor ex0 = ex; + std::string n; + + if (ex.try_read_word (n) && ex.test ("=")) { + + // a parameter + pv [mp_netlist ? mp_netlist->normalize_name (n) : tl::to_upper_case (n)] = read_value (ex, variables); + + } else { + + // a net/model component + ex = ex0; + if (in_params) { + ex.error (tl::to_string (tr ("Invalid syntax for parameter assignment - needs keyword followed by '='"))); + } + + std::string comp_name = parse_component (ex); + comp_name = mp_netlist ? mp_netlist->normalize_name (comp_name) : tl::to_upper_case (comp_name); + + // resolve variables if string type + auto v = variables.find (comp_name); + if (v != variables.end ()) { + if (v->second.is_a_string ()) { + strings.push_back (v->second.to_string ()); + } else if (v->second.can_convert_to_double ()) { + // NOTE: this allows using a variable name "x" instead of "x=x" + pv [comp_name] = v->second; + } else { + strings.push_back (comp_name); + } + } else { + strings.push_back (comp_name); + } + + } + + } + + } +} + +void NetlistSpiceReaderDelegate::parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, std::map &pv, const std::map &variables) +{ + parse_element_components (s, nn, pv, variables); + + // interpret the parameters according to the code + if (element == "X") { + + // subcircuit call: + // Xname n1 n2 ... nn circuit [params] + + if (nn.empty ()) { + error (tl::to_string (tr ("No circuit name given for subcircuit call"))); + } + + model = nn.back (); + nn.pop_back (); + + } else if (element == "R" || element == "C" || element == "L") { + + // resistor, cap, inductor: two-terminal devices with a value + // Rname n1 n2 value + // Rname n1 n2 n3 value + // Rname n1 n2 value model [params] + // Rname n1 n2 n3 value model [params] + // Rname n1 n2 [params] + // Rname n1 n2 model [params] + // Rname n1 n2 n3 model [params] + // NOTE: there is no "Rname n1 n2 n3 [params]"! + // (same for C, L instead of R) + + if (nn.size () < 2) { + error (tl::to_string (tr ("Not enough specs for a R, C or L device"))); + } + + auto rv = pv.find (element); + if (rv != pv.end ()) { + + // value given by parameter + value = rv->second.to_double (); + + if (nn.size () >= 3) { + // Rname n1 n2 model [params] + // Rname n1 n2 n3 model [params] + model = nn.back (); + nn.pop_back (); + } + + } else if (nn.size () >= 3) { + + if (try_read_value (nn.back (), value, variables)) { + + // Rname n1 n2 value + // Rname n1 n2 n3 value + nn.pop_back (); + + } else { + + // Rname n1 n2 value model [params] + // Rname n1 n2 n3 value model [params] + model = nn.back (); + nn.pop_back (); + if (! try_read_value (nn.back (), value, variables)) { + error (tl::to_string (tr ("Can't find a value for a R, C or L device"))); + } else { + nn.pop_back (); + } + + } + + } + + } else { + + // others: n-terminal devices with a model (last node) + + if (nn.empty ()) { + error (tl::sprintf (tl::to_string (tr ("No model name given for element '%s'")), element)); + } + + model = nn.back (); + nn.pop_back (); + + if (element == "M") { + if (nn.size () != 4) { + error (tl::to_string (tr ("'M' element must have four nodes"))); + } + } else if (element == "Q") { + if (nn.size () != 3 && nn.size () != 4) { + error (tl::to_string (tr ("'Q' element must have three or four nodes"))); + } + } else if (element == "D") { + if (nn.size () != 2) { + error (tl::to_string (tr ("'D' element must have two nodes"))); + } + } + + // TODO: other devices? + + } +} + +bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map &pv) +{ + std::map params = pv; + std::vector terminal_order; + + double mult = 1.0; + auto mp = params.find ("M"); + if (mp != params.end ()) { + mult = mp->second.to_double (); + } + + if (mult < 1e-10) { + error (tl::sprintf (tl::to_string (tr ("Invalid multiplier value (M=%.12g) - must not be zero or negative")), mult)); + } + + std::string cn = model; + db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (cn); + + if (element == "R") { + + if (nets.size () == 2) { + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a resistor device class as required by 'R' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "RES"; + } + cls = make_device_class (circuit, cn); + } + } else if (nets.size () == 3) { + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal resistor device class as required by 'R' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "RES3"; + } + cls = make_device_class (circuit, cn); + } + } else { + error (tl::to_string (tr ("A 'R' element requires two or three nets"))); + } + + // Apply multiplier + value /= mult; + + } else if (element == "L") { + + if (nets.size () == 2) { + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a inductor device class as required by 'L' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "IND"; + } + cls = make_device_class (circuit, cn); + } + } else { + error (tl::to_string (tr ("A 'L' element requires two nets"))); + } + + // Apply multiplier + value /= mult; + + } else if (element == "C") { + + if (nets.size () == 2) { + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a capacitor device class as required by 'C' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "CAP"; + } + cls = make_device_class (circuit, cn); + } + } else if (nets.size () == 3) { + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal capacitor device class as required by 'C' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "CAP3"; + } + cls = make_device_class (circuit, cn); + } + } else { + error (tl::to_string (tr ("A 'C' element requires two or three nets"))); + } + + // Apply multiplier + value *= mult; + + } else if (element == "D") { + + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a diode device class as required by 'D' element")), cn)); + } + } else { + if (cn.empty ()) { + cn = "DIODE"; + } + cls = make_device_class (circuit, cn); + } + + // Apply multiplier to "A" + auto p = params.find ("A"); + if (p != params.end ()) { + p->second = tl::Variant (p->second.to_double () * mult); + } + + } else if (element == "Q") { + + if (nets.size () != 3 && nets.size () != 4) { + error (tl::to_string (tr ("'Q' element needs to have 3 or 4 terminals"))); + } else if (cls) { + if (nets.size () == 3) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a 3-terminal BJT device class as required by 'Q' element")), cn)); + } + } else { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal BJT device class as required by 'Q' element")), cn)); + } + } + } else { + if (nets.size () == 3) { + if (cn.empty ()) { + cn = "BJT3"; + } + cls = make_device_class (circuit, cn); + } else { + if (cn.empty ()) { + cn = "BJT4"; + } + cls = make_device_class (circuit, cn); + } + } + + // Apply multiplier to "AE" + auto p = params.find ("AE"); + if (p != params.end ()) { + p->second = tl::Variant (p->second.to_double () * mult); + } + + } else if (element == "M") { + + if (cls) { + if (! dynamic_cast(cls)) { + error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal MOS device class as required by 'M' element")), cn)); + } + } else { + if (nets.size () == 4) { + if (cn.empty ()) { + cn = "MOS4"; + } + cls = make_device_class (circuit, cn); + } else { + error (tl::to_string (tr ("'M' element needs to have 4 terminals"))); + } + } + + // Apply multiplier to "W" + auto p = params.find ("W"); + if (p != params.end ()) { + p->second = tl::Variant (p->second.to_double () * mult); + } + + // issue #1304 + terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_D); + terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_G); + terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_S); + terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_B); + + } else { + error (tl::sprintf (tl::to_string (tr ("Not a known element type: '%s'")), element)); + } + + const std::vector &td = cls->terminal_definitions (); + if (td.size () != nets.size ()) { + error (tl::sprintf (tl::to_string (tr ("Wrong number of terminals: class '%s' expects %d, but %d are given")), cn, int (td.size ()), int (nets.size ()))); + } + + db::Device *device = new db::Device (cls, name); + circuit->add_device (device); + + if (terminal_order.empty ()) { + for (auto t = td.begin (); t != td.end (); ++t) { + device->connect_terminal (t->id (), nets [t - td.begin ()]); + } + } else { + for (auto t = terminal_order.begin (); t != terminal_order.end (); ++t) { + device->connect_terminal (*t, nets [t - terminal_order.begin ()]); + } + } + + + size_t defp = std::numeric_limits::max (); + if (dynamic_cast (cls)) { + defp = db::DeviceClassCapacitor::param_id_C; + } else if (dynamic_cast (cls)) { + defp = db::DeviceClassResistor::param_id_R; + } else if (dynamic_cast (cls)) { + defp = db::DeviceClassInductor::param_id_L; + } + + std::vector &pd = cls->parameter_definitions_non_const (); + for (std::vector::iterator i = pd.begin (); i != pd.end (); ++i) { + auto v = params.find (i->name ()); + if (v != params.end ()) { + device->set_parameter_value (i->id (), v->second.to_double () / i->si_scaling ()); + } else if (i->id () == defp) { + device->set_parameter_value (i->id (), value / i->si_scaling ()); + } + } + + return true; +} + +tl::Variant +NetlistSpiceReaderDelegate::read_value (tl::Extractor &ex, const std::map &variables) +{ + NetlistSpiceReaderExpressionParser parser (&variables); + return parser.read (ex); +} + +bool +NetlistSpiceReaderDelegate::try_read_value (const std::string &s, double &v, const std::map &variables) +{ + NetlistSpiceReaderExpressionParser parser (&variables); + + tl::Variant vv; + tl::Extractor ex (s.c_str ()); + bool res = parser.try_read (ex, vv); + + if (res && ! vv.can_convert_to_double ()) { + res = false; + } + if (res) { + v = vv.to_double (); + } + + return res; +} + +} diff --git a/src/db/db/dbNetlistSpiceReaderDelegate.h b/src/db/db/dbNetlistSpiceReaderDelegate.h new file mode 100644 index 000000000..521773a3b --- /dev/null +++ b/src/db/db/dbNetlistSpiceReaderDelegate.h @@ -0,0 +1,169 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2023 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#ifndef HDR_dbNetlistSpiceReaderDelegate +#define HDR_dbNetlistSpiceReaderDelegate + +#include "dbCommon.h" +#include "tlStream.h" +#include "tlException.h" + +#include +#include +#include + +namespace db +{ + +class Netlist; +class Net; +class Circuit; +class DeviceClass; +class Device; + +/** + * @brief A delegate to handle various forms of devices and translates them + * + * The reader delegate can be configured to receive subcircuit elements too. + * In this case, parameters are allowed. + * For receiving subcircuit elements, the delegate needs to indicate + * this by returning true upon "wants_subcircuit". + */ +class DB_PUBLIC NetlistSpiceReaderDelegate + : public tl::Object +{ +public: + NetlistSpiceReaderDelegate (); + virtual ~NetlistSpiceReaderDelegate (); + + /** + * @brief Called when the netlist reading starts + */ + virtual void start (db::Netlist *netlist); + + /** + * @brief Called when the netlist reading ends + */ + virtual void finish (db::Netlist *netlist); + + /** + * @brief Called when an unknown control statement is encountered + * + * Returns true if the statement is understood. + */ + virtual bool control_statement (const std::string &line); + + /** + * @brief Returns true, if the delegate wants subcircuit elements with this name + * + * The name is always upper case. + */ + virtual bool wants_subcircuit (const std::string &circuit_name); + + /** + * @brief This method translates a raw net name to a valid net name + * + * The default implementation will unescape backslash sequences into plain characters. + */ + virtual std::string translate_net_name (const std::string &nn); + + /** + * @brief Makes a device from an element line + * + * @param circuit The circuit that is currently read. + * @param element The upper-case element code ("M", "R", ...). + * @param name The element's name. + * @param model The upper-case model name (may be empty). + * @param value The default value (e.g. resistance for resistors) and may be zero. + * @param nets The nets given in the element line. + * @param parameters The parameters of the element statement (parameter names are upper case). + * + * The default implementation will create corresponding devices for + * some known elements using the Spice writer's parameter conventions. + * + * This method returns true, if the element was read. + */ + virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms); + + /** + * @brief Parses an element from a line + * + * @param s The line to parse (the part after the element and name) + * @param model Out parameter: the model name if given + * @param value Out parameter: the value if given (for R, L, C) + * @param nn Out parameter: the net names + * @param pv Out parameter: the parameter values (key/value pairs) + */ + virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, std::map &pv, const std::map ¶ms); + + /** + * @brief Produces an error with the given message + */ + virtual void error (const std::string &msg); + + /** + * @brief Reads a set of string components and parameters from the string + * A special key "param:" is recognized for starting a parameter list. + */ + void parse_element_components (const std::string &s, std::vector &strings, std::map &pv, const std::map &variables); + + /** + * @brief Reads a value from the extractor (with formula evaluation) + */ + static tl::Variant read_value(tl::Extractor &ex, const std::map &variables); + + /** + * @brief Tries to read a value from the extractor (with formula evaluation) + */ + static bool try_read_value (const std::string &s, double &v, const std::map &variables); + + /** + * @brief External interface for start + */ + void do_start () + { + start (mp_netlist); + } + + /** + * @brief External interface for finish + */ + void do_finish () + { + finish (mp_netlist); + } + + /** + * @brief Sets the netlist + */ + void set_netlist (db::Netlist *netlist) + { + mp_netlist = netlist; + } + +private: + db::Netlist *mp_netlist; +}; + +} + +#endif diff --git a/src/db/db/dbNetlistSpiceReaderExpressionParser.cc b/src/db/db/dbNetlistSpiceReaderExpressionParser.cc new file mode 100644 index 000000000..364a11ebe --- /dev/null +++ b/src/db/db/dbNetlistSpiceReaderExpressionParser.cc @@ -0,0 +1,556 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2023 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#include "dbNetlistSpiceReaderExpressionParser.h" +#include "dbNetlistSpiceReader.h" + +#include + +namespace db +{ + +// ------------------------------------------------------------------------------------------------------ + +static bool to_bool (const tl::Variant &v) +{ + if (v.is_bool ()) { + return v.to_bool (); + } else if (v.is_nil ()) { + return false; + } else if (v.can_convert_to_double ()) { + return v.to_double () != 0.0; + } else { + return true; + } +} +// ------------------------------------------------------------------------------------------------------ + +NetlistSpiceReaderExpressionParser::NetlistSpiceReaderExpressionParser (const variables_type *vars) +{ + static variables_type empty_variables; + mp_variables = vars ? vars : &empty_variables; +} + +// expression syntax taken from ngspice: +// https://nmg.gitlab.io/ngspice-manual/circuitdescription/paramparametricnetlists/syntaxofexpressions.html + +static double sqrt_f (double v) { return sqrt (v); } +static double sin_f (double v) { return sin (v); } +static double cos_f (double v) { return cos (v); } +static double tan_f (double v) { return tan (v); } +static double sinh_f (double v) { return sinh (v); } +static double cosh_f (double v) { return cosh (v); } +static double tanh_f (double v) { return tanh (v); } +static double asin_f (double v) { return asin (v); } +static double acos_f (double v) { return acos (v); } +static double atan_f (double v) { return atan (v); } +static double asinh_f (double v) { return asinh (v); } +static double acosh_f (double v) { return acosh (v); } +static double atanh_f (double v) { return atanh (v); } +static double exp_f (double v) { return exp (v); } +static double ln_f (double v) { return log (v); } +static double log_f (double v) { return log10 (v); } +static double abs_f (double v) { return abs (v); } +static double nint_f (double v) { return nearbyint (v); } // we basically should we the rounding mode before ... +static double floor_f (double v) { return floor (v); } +static double ceil_f (double v) { return ceil (v); } +static double sgn_f (double v) { return v == 0.0 ? 0.0 : (v < 0.0 ? -1.0 : 1.0); } +static double int_f (double v) { return sgn_f (v) * floor (sgn_f (v) * v); } + +tl::Variant +NetlistSpiceReaderExpressionParser::eval_func (const std::string &name, const std::vector ¶ms, bool * /*status*/) const +{ + double (*f) (double) = 0; + + if (name == "SQRT") { f = sqrt_f; } else + if (name == "SIN") { f = sin_f; } else + if (name == "COS") { f = cos_f; } else + if (name == "TAN") { f = tan_f; } else + if (name == "SINH") { f = sinh_f; } else + if (name == "COSH") { f = cosh_f; } else + if (name == "TANH") { f = tanh_f; } else + if (name == "ASIN") { f = asin_f; } else + if (name == "ACOS") { f = acos_f; } else + if (name == "ATAN" || name == "arctan") { f = atan_f; } else + if (name == "ASINH") { f = asinh_f; } else + if (name == "ACOSH") { f = acosh_f; } else + if (name == "ATANH") { f = atanh_f; } else + if (name == "EXP") { f = exp_f; } else + if (name == "LN") { f = ln_f; } else + if (name == "LOG") { f = log_f; } else + if (name == "ABS") { f = abs_f; } else + if (name == "NINT") { f = nint_f; } else + if (name == "FLOOR") { f = floor_f; } else + if (name == "CEIL") { f = ceil_f; } else + if (name == "SGN") { f = sgn_f; } else + if (name == "INT") { f = int_f; } + + if (f != 0) { + + if (params.size () < 1 || ! params.front ().can_convert_to_double ()) { + return tl::Variant (); + } else { + return tl::Variant ((*f) (params.front ().to_double ())); + } + + } else if (name == "PWR" || name == "POW") { + + if (params.size () < 2 || ! params [0].can_convert_to_double () || ! params [1].can_convert_to_double ()) { + return tl::Variant (); + } else { + return tl::Variant (pow (params [0].to_double (), params [1].to_double ())); + } + + } else if (name == "TERNERY_FCN") { + + if (params.size () < 3) { + return tl::Variant (); + } else { + return to_bool (params [0]) ? params [1] : params [2]; + } + + } else if (name == "MIN") { + + if (params.size () < 1) { + return tl::Variant (); + } + + tl::Variant v = params [0]; + for (size_t i = 1; i < params.size (); ++i) { + if (params [i] < v) { + v = params [i]; + } + } + return v; + + } else if (name == "MAX") { + + if (params.size () < 1) { + return tl::Variant (); + } + + tl::Variant v = params [0]; + for (size_t i = 1; i < params.size (); ++i) { + if (v < params [i]) { + v = params [i]; + } + } + return v; + + } else { + + return tl::Variant (); + + } +} + +tl::Variant +NetlistSpiceReaderExpressionParser::read_atomic_value (tl::Extractor &ex, bool *status) const +{ + double vd = 0.0; + std::string var; + + if (ex.test ("-")) { + + tl::Variant v = read_atomic_value (ex, status); + if (v.can_convert_to_double ()) { + return tl::Variant (-v.to_double ()); + } else { + return tl::Variant (); + } + + } else if (ex.test ("!")) { + + tl::Variant v = read_atomic_value (ex, status); + return tl::Variant (! to_bool (v)); + + } else if (ex.test ("(")) { + + tl::Variant v = read_tl_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (status) { + *status = ex.test (")"); + } else { + ex.expect (")"); + } + return v; + + } else if (ex.try_read (vd)) { + + if (status) { + *status = true; + } + + double f = 1.0; + if (*ex == 't' || *ex == 'T') { + f = 1e12; + } else if (*ex == 'g' || *ex == 'G') { + f = 1e9; + } else if (*ex == 'k' || *ex == 'K') { + f = 1e3; + } else if (*ex == 'm' || *ex == 'M') { + f = 1e-3; + if (ex.test_without_case ("meg")) { + f = 1e6; + } + } else if (*ex == 'u' || *ex == 'U') { + f = 1e-6; + } else if (*ex == 'n' || *ex == 'N') { + f = 1e-9; + } else if (*ex == 'p' || *ex == 'P') { + f = 1e-12; + } else if (*ex == 'f' || *ex == 'F') { + f = 1e-15; + } else if (*ex == 'a' || *ex == 'A') { + f = 1e-18; + } + while (*ex && isalpha (*ex)) { + ++ex; + } + + vd *= f; + return tl::Variant (vd); + + } else if (ex.try_read_word (var)) { + + var = tl::to_upper_case (var); + + if (ex.test ("(")) { + + // a function + + std::vector params; + if (! ex.test (")")) { + while (! ex.at_end ()) { + params.push_back (read_tl_expr (ex, status)); + if (status && !*status) { + return tl::Variant (); + } + if (! ex.test (",")) { + break; + } + } + if (status && ! ex.test (")")) { + *status = false; + return tl::Variant (); + } else { + ex.expect (")"); + } + } + + return eval_func (var, params, status); + + } else { + + auto vi = mp_variables->find (var); + if (vi != mp_variables->end ()) { + return vi->second; + } else { + // keep word as string value + return tl::Variant (var); + } + + } + + } else { + + if (status) { + *status = false; + } else { + throw tl::Exception (tl::sprintf (tl::to_string (tr ("Expected number of variable name here: '...%s'")), ex.get ())); + } + + return tl::Variant (); + + } +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_pwr_expr (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_atomic_value (ex, status); + if (status && !*status) { + return tl::Variant (); + } + while (true) { + if (ex.test ("**") || ex.test ("^")) { + tl::Variant vv = read_atomic_value (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = tl::Variant (pow (v.to_double (), vv.to_double ())); + } + } else { + break; + } + } + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_dot_expr (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_pwr_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + while (true) { + if (ex.test ("*")) { + tl::Variant vv = read_pwr_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = v.to_double () * vv.to_double (); + } + } else if (ex.test ("/")) { + tl::Variant vv = read_pwr_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = v.to_double () / vv.to_double (); + } + } else if (ex.test ("%")) { + tl::Variant vv = read_pwr_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = tl::Variant ((long int) v.to_double () % (long int) vv.to_double ()); + } + } else { + break; + } + } + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_bar_expr (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_dot_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + while (true) { + if (ex.test ("+")) { + tl::Variant vv = read_dot_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = v.to_double () + vv.to_double (); + } + } else if (ex.test ("-")) { + tl::Variant vv = read_dot_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) { + v = tl::Variant (); + } else { + v = v.to_double () - vv.to_double (); + } + } else { + break; + } + } + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_compare_expr (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + while (true) { + if (ex.test ("==")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (v == vv); + } else if (ex.test ("!=")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (!(v == vv)); + } else if (ex.test ("<=")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (v < vv || v == vv); + } else if (ex.test ("<")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (v < vv); + } else if (ex.test (">=")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (vv < v || v == vv); + } else if (ex.test (">")) { + tl::Variant vv = read_bar_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (vv < v); + } else { + break; + } + } + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_logical_op (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_compare_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + while (true) { + if (ex.test ("&&")) { + tl::Variant vv = read_compare_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (to_bool (v) && to_bool (vv)); + } else if (ex.test ("||")) { + tl::Variant vv = read_compare_expr (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = tl::Variant (to_bool (v) || to_bool (vv)); + } else { + break; + } + } + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_ternary_op (tl::Extractor &ex, bool *status) const +{ + tl::Variant v = read_logical_op (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (ex.test ("?")) { + tl::Variant vv1 = read_logical_op (ex, status); + if (status && !*status) { + return tl::Variant (); + } + if (! ex.test (":")) { + if (status) { + *status = false; + } else { + ex.expect (":"); + } + } + tl::Variant vv2 = read_logical_op (ex, status); + if (status && !*status) { + return tl::Variant (); + } + v = to_bool (v) ? vv1 : vv2; + } + + return v; +} + +tl::Variant NetlistSpiceReaderExpressionParser::read_tl_expr (tl::Extractor &ex, bool *status) const +{ + return read_ternary_op (ex, status); +} + +static const char *start_quote (tl::Extractor &ex) +{ + if (ex.test ("'")) { + return "'"; + } else if (ex.test ("\"")) { + return "\""; + } else if (ex.test ("{")) { + return "}"; + } else { + return 0; + } +} + +tl::Variant NetlistSpiceReaderExpressionParser::read (const std::string &s) const +{ + tl::Extractor ex (s.c_str ()); + return read (ex); +} + +tl::Variant NetlistSpiceReaderExpressionParser::read (tl::Extractor &ex) const +{ + tl::Variant res; + + const char *endquote = start_quote (ex); + res = read_tl_expr (ex, 0); + if (endquote) { + ex.test (endquote); + } + + return res; +} + +bool NetlistSpiceReaderExpressionParser::try_read (const std::string &s, tl::Variant &value) const +{ + tl::Extractor ex (s.c_str ()); + return try_read (ex, value); +} + +bool NetlistSpiceReaderExpressionParser::try_read (tl::Extractor &ex, tl::Variant &value) const +{ + tl::Extractor ex_saved = ex; + + bool status = false; + const char *endquote = start_quote (ex); + value = read_tl_expr (ex, &status); + if (endquote && ! ex.test (endquote)) { + status = false; + } + if (! status) { + value = tl::Variant (); + ex = ex_saved; + } + + return status; +} + +} diff --git a/src/db/db/dbNetlistSpiceReaderExpressionParser.h b/src/db/db/dbNetlistSpiceReaderExpressionParser.h new file mode 100644 index 000000000..18c1fd8d0 --- /dev/null +++ b/src/db/db/dbNetlistSpiceReaderExpressionParser.h @@ -0,0 +1,70 @@ + +/* + + KLayout Layout Viewer + Copyright (C) 2006-2023 Matthias Koefferlein + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +*/ + +#ifndef HDR_dbNetlistSpiceReaderExpressionParser +#define HDR_dbNetlistSpiceReaderExpressionParser + +#include "dbCommon.h" +#include "tlStream.h" +#include "tlVariant.h" +#include "tlString.h" + +#include +#include +#include + +namespace db +{ + +/** + * @brief A class implementing the expression parser + * + * This class is exposed mainly for testing purposes. + */ +class DB_PUBLIC NetlistSpiceReaderExpressionParser +{ +public: + typedef std::map variables_type; + + NetlistSpiceReaderExpressionParser (const variables_type *vars); + + tl::Variant read (tl::Extractor &ex) const; + tl::Variant read (const std::string &s) const; + bool try_read (tl::Extractor &ex, tl::Variant &v) const; + bool try_read (const std::string &s, tl::Variant &v) const; + +private: + const variables_type *mp_variables; + + tl::Variant read_atomic_value (tl::Extractor &ex, bool *status) const; + tl::Variant read_dot_expr (tl::Extractor &ex, bool *status) const; + tl::Variant read_bar_expr (tl::Extractor &ex, bool *status) const; + tl::Variant read_pwr_expr (tl::Extractor &ex, bool *status) const; + tl::Variant read_compare_expr (tl::Extractor &ex, bool *status) const; + tl::Variant read_logical_op (tl::Extractor &ex, bool *status) const; + tl::Variant read_ternary_op (tl::Extractor &ex, bool *status) const; + tl::Variant read_tl_expr (tl::Extractor &ex, bool *status) const; + tl::Variant eval_func (const std::string &name, const std::vector ¶ms, bool *status) const; +}; +} + +#endif diff --git a/src/db/db/dbNetlistSpiceWriter.cc b/src/db/db/dbNetlistSpiceWriter.cc index dd6818478..233cb5054 100644 --- a/src/db/db/dbNetlistSpiceWriter.cc +++ b/src/db/db/dbNetlistSpiceWriter.cc @@ -160,12 +160,21 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const os << "M"; os << format_name (dev.expanded_name ()); - os << format_terminals (dev); + + // issue #1304 + os << " "; + os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_D)); + os << " "; + os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_G)); + os << " "; + os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_S)); + os << " "; if (! mos4) { // we assume for the MOS3 type the bulk is connected to Source - os << " "; os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_S)); + } else { + os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS4Transistor::terminal_id_B)); } // Use device class name for the model diff --git a/src/db/db/gsiDeclDbNetlist.cc b/src/db/db/gsiDeclDbNetlist.cc index c083786ac..636684007 100644 --- a/src/db/db/gsiDeclDbNetlist.cc +++ b/src/db/db/gsiDeclDbNetlist.cc @@ -26,6 +26,7 @@ #include "dbNetlistSpiceWriter.h" #include "dbNetlistReader.h" #include "dbNetlistSpiceReader.h" +#include "dbNetlistSpiceReaderDelegate.h" #include "tlException.h" #include "tlInternational.h" #include "tlStream.h" @@ -2417,15 +2418,15 @@ public: const std::vector &net_names () const { return m_net_names; } std::vector &net_names_nc () { return m_net_names; } void set_net_names (const std::vector &nn) { m_net_names = nn; } - const std::map ¶meters () const { return m_parameters; } - std::map ¶meters_nc () { return m_parameters; } - void set_parameters (const std::map ¶meters) { m_parameters = parameters; } + const db::NetlistSpiceReader::parameters_type ¶meters () const { return m_parameters; } + db::NetlistSpiceReader::parameters_type ¶meters_nc () { return m_parameters; } + void set_parameters (const db::NetlistSpiceReader::parameters_type ¶meters) { m_parameters = parameters; } private: std::string m_model; double m_value; std::vector m_net_names; - std::map m_parameters; + db::NetlistSpiceReader::parameters_type m_parameters; }; /** @@ -2439,13 +2440,13 @@ public: const std::vector &strings () const { return m_strings; } std::vector &strings_nc () { return m_strings; } void set_strings (const std::vector &nn) { m_strings = nn; } - const std::map ¶meters () const { return m_parameters; } - std::map ¶meters_nc () { return m_parameters; } - void set_parameters (const std::map ¶meters) { m_parameters = parameters; } + const db::NetlistSpiceReader::parameters_type ¶meters () const { return m_parameters; } + db::NetlistSpiceReader::parameters_type ¶meters_nc () { return m_parameters; } + void set_parameters (const db::NetlistSpiceReader::parameters_type ¶meters) { m_parameters = parameters; } private: std::vector m_strings; - std::map m_parameters; + db::NetlistSpiceReader::parameters_type m_parameters; }; /** @@ -2456,7 +2457,7 @@ class NetlistSpiceReaderDelegateImpl { public: NetlistSpiceReaderDelegateImpl () - : db::NetlistSpiceReaderDelegate () + : db::NetlistSpiceReaderDelegate (), mp_variables (0) { // .. nothing yet .. } @@ -2566,15 +2567,16 @@ public: ParseElementData parse_element_helper (const std::string &s, const std::string &element) { ParseElementData data; - db::NetlistSpiceReaderDelegate::parse_element (s, element, data.model_name_nc (), data.value_nc (), data.net_names_nc (), data.parameters_nc ()); + db::NetlistSpiceReaderDelegate::parse_element (s, element, data.model_name_nc (), data.value_nc (), data.net_names_nc (), data.parameters_nc (), variables ()); return data; } - virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, std::map &pv) + virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector &nn, db::NetlistSpiceReader::parameters_type &pv, const db::NetlistSpiceReader::parameters_type &variables) { try { m_error.clear (); + mp_variables = &variables; ParseElementData data; if (cb_parse_element.can_issue ()) { @@ -2588,21 +2590,27 @@ public: nn = data.net_names (); pv = data.parameters (); + mp_variables = 0; + } catch (tl::Exception &) { + mp_variables = 0; if (! m_error.empty ()) { db::NetlistSpiceReaderDelegate::error (m_error); } else { throw; } + } catch (...) { + mp_variables = 0; + throw; } } - virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms) + virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const db::NetlistSpiceReader::parameters_type ¶ms) { try { m_error.clear (); if (cb_element.can_issue ()) { - return cb_element.issue &, const std::map &> (&db::NetlistSpiceReaderDelegate::element, circuit, element, name, model, value, nets, params); + return cb_element.issue &, const db::NetlistSpiceReader::parameters_type &> (&db::NetlistSpiceReaderDelegate::element, circuit, element, name, model, value, nets, params); } else { return db::NetlistSpiceReaderDelegate::element (circuit, element, name, model, value, nets, params); } @@ -2616,6 +2624,12 @@ public: } } + const db::NetlistSpiceReader::parameters_type &variables () const + { + static db::NetlistSpiceReader::parameters_type empty; + return mp_variables ? *mp_variables : empty; + } + gsi::Callback cb_start; gsi::Callback cb_finish; gsi::Callback cb_control_statement; @@ -2626,6 +2640,7 @@ public: private: std::string m_error; + const db::NetlistSpiceReader::parameters_type *mp_variables; }; static void start_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Netlist *netlist) @@ -2653,7 +2668,7 @@ static std::string translate_net_name_fb (NetlistSpiceReaderDelegateImpl *delega return delegate->db::NetlistSpiceReaderDelegate::translate_net_name (name); } -static bool element_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms) +static bool element_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const db::NetlistSpiceReader::parameters_type ¶ms) { return delegate->db::NetlistSpiceReaderDelegate::element (circuit, element, name, model, value, nets, params); } @@ -2663,41 +2678,43 @@ static ParseElementData parse_element_fb (NetlistSpiceReaderDelegateImpl *delega return delegate->parse_element_helper (s, element); } -static tl::Variant value_from_string (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s) +static tl::Variant value_from_string (NetlistSpiceReaderDelegateImpl * /*delegate*/, const std::string &s, const db::NetlistSpiceReader::parameters_type &variables) { tl::Variant res; double v = 0.0; - if (delegate->try_read_value (s, v)) { + if (db::NetlistSpiceReaderDelegate::try_read_value (s, v, variables)) { res = v; } return res; } -static ParseElementComponentsData parse_element_components (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s) +static ParseElementComponentsData parse_element_components (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s, const db::NetlistSpiceReader::parameters_type &variables) { ParseElementComponentsData data; - delegate->parse_element_components (s, data.strings_nc (), data.parameters_nc ()); + delegate->parse_element_components (s, data.strings_nc (), data.parameters_nc (), variables); return data; } Class db_ParseElementComponentsData ("db", "ParseElementComponentsData", gsi::method ("strings", &ParseElementComponentsData::strings, - "@brief Gets the string parameters\n" + "@brief Gets the (unnamed) string parameters\n" + "These parameters are typically net names or model name." ) + gsi::method ("strings=", &ParseElementComponentsData::set_strings, gsi::arg ("list"), - "@brief Sets the string parameters\n" + "@brief Sets the (unnamed) string parameters\n" ) + gsi::method ("parameters", &ParseElementComponentsData::parameters, - "@brief Gets the (named) numerical parameters\n" + "@brief Gets the (named) parameters\n" + "Named parameters are typically (but not neccessarily) numerical, like 'w=0.15u'." ) + gsi::method ("parameters=", &ParseElementComponentsData::set_parameters, gsi::arg ("dict"), - "@brief Sets the (named) numerical parameters\n" + "@brief Sets the (named) parameters\n" ), "@brief Supplies the return value for \\NetlistSpiceReaderDelegate#parse_element_components.\n" "This is a structure with two members: 'strings' for the string arguments and 'parameters' for the " - "named numerical arguments.\n" + "named arguments.\n" "\n" - "This helper class has been introduced in version 0.27.1.\n" + "This helper class has been introduced in version 0.27.1. Starting with version 0.28.6, named parameters can be string types too.\n" ); Class db_ParseElementData ("db", "ParseElementData", @@ -2720,16 +2737,16 @@ Class db_ParseElementData ("db", "ParseElementData", "@brief Sets the net names\n" ) + gsi::method ("parameters", &ParseElementData::parameters, - "@brief Gets the (named) numerical parameters\n" + "@brief Gets the (named) parameters\n" ) + gsi::method ("parameters=", &ParseElementData::set_parameters, gsi::arg ("dict"), - "@brief Sets the (named) numerical parameters\n" + "@brief Sets the (named) parameters\n" ), "@brief Supplies the return value for \\NetlistSpiceReaderDelegate#parse_element.\n" "This is a structure with four members: 'model_name' for the model name, 'value' for the default numerical value, 'net_names' for the net names and 'parameters' for the " - "named numerical parameters.\n" + "named parameters.\n" "\n" - "This helper class has been introduced in version 0.27.1.\n" + "This helper class has been introduced in version 0.27.1. Starting with version 0.28.6, named parameters can be string types too.\n" ); Class db_NetlistSpiceReaderDelegate ("db", "NetlistSpiceReaderDelegate", @@ -2765,6 +2782,13 @@ Class db_NetlistSpiceReaderDelegate ("db", "Netl "\n" "This method has been introduced in version 0.27.1\n" ) + + gsi::method ("variables", &NetlistSpiceReaderDelegateImpl::variables, + "@brief Gets the variables defined inside the SPICE file during execution of 'parse_element'\n" + "In order to evaluate formulas, this method allows accessing the variables that are " + "present during the execution of the SPICE reader.\n" + "\n" + "This method has been introduced in version 0.28.6." + ) + gsi::callback ("parse_element", &NetlistSpiceReaderDelegateImpl::parse_element_helper, &NetlistSpiceReaderDelegateImpl::cb_parse_element, gsi::arg ("s"), gsi::arg ("element"), "@brief Parses an element card\n" @@ -2795,27 +2819,33 @@ Class db_NetlistSpiceReaderDelegate ("db", "Netl "some known elements using the Spice writer's parameter conventions.\n" "\n" "The method must return true, if the element was was understood and false otherwise.\n" + "\n" + "Starting with version 0.28.6, the parameter values can be strings too." ) + gsi::method ("error", &NetlistSpiceReaderDelegateImpl::error, gsi::arg ("msg"), "@brief Issues an error with the given message.\n" "Use this method to generate an error." ) + - gsi::method_ext ("value_from_string", &value_from_string, gsi::arg ("s"), + gsi::method_ext ("value_from_string", &value_from_string, gsi::arg ("s"), gsi::arg ("variables", db::NetlistSpiceReader::parameters_type (), "{}"), "@brief Translates a string into a value\n" "This function simplifies the implementation of SPICE readers by providing a translation of a unit-annotated string " "into double values. For example, '1k' is translated to 1000.0. In addition, simple formula evaluation is supported, e.g " "'(1+3)*2' is translated into 8.0.\n" "\n" - "This method has been introduced in version 0.27.1\n" + "The variables dictionary defines named variables with the given values.\n" + "\n" + "This method has been introduced in version 0.27.1. The variables argument has been added in version 0.28.6.\n" ) + - gsi::method_ext ("parse_element_components", &parse_element_components, gsi::arg ("s"), + gsi::method_ext ("parse_element_components", &parse_element_components, gsi::arg ("s"), gsi::arg ("variables", db::NetlistSpiceReader::parameters_type (), "{}"), "@brief Parses a string into string and parameter components.\n" "This method is provided to simplify the implementation of 'parse_element'. It takes a string and splits it into " "string arguments and parameter values. For example, 'a b c=6' renders two string arguments in 'nn' and one parameter ('C'->6.0). " "It returns data \\ParseElementComponentsData object with the strings and parameters.\n" "The parameter names are already translated to upper case.\n" "\n" - "This method has been introduced in version 0.27.1\n" + "The variables dictionary defines named variables with the given values.\n" + "\n" + "This method has been introduced in version 0.27.1. The variables argument has been added in version 0.28.6.\n" ), "@brief Provides a delegate for the SPICE reader for translating device statements\n" "Supply a customized class to provide a specialized reading scheme for devices. " diff --git a/src/db/unit_tests/dbNetlistReaderTests.cc b/src/db/unit_tests/dbNetlistReaderTests.cc index 4b1fbf70b..c4934c252 100644 --- a/src/db/unit_tests/dbNetlistReaderTests.cc +++ b/src/db/unit_tests/dbNetlistReaderTests.cc @@ -21,6 +21,8 @@ */ #include "dbNetlistSpiceReader.h" +#include "dbNetlistSpiceReaderDelegate.h" +#include "dbNetlistSpiceReaderExpressionParser.h" #include "dbNetlist.h" #include "dbNetlistDeviceClasses.h" @@ -167,33 +169,49 @@ TEST(4_ReaderWithUnconnectedPins) " subcircuit INV2 $2 ('1'='7','2'='4','3'='6','4'='3','5'='2','6'='1');\n" "end;\n" "circuit INV2 ('1'='1','2'='2','3'='3','4'='4','5'='5','6'='6');\n" - " device PMOS $1 (S='3',G='2',D='5',B='1') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" - " device NMOS $3 (S='3',G='2',D='4',B='6') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" + " device PMOS $1 (S='5',G='2',D='3',B='1') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" + " device NMOS $3 (S='4',G='2',D='3',B='6') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n" "end;\n" ); } TEST(5_CircuitParameters) { - db::Netlist nl; - std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader5.cir"); db::NetlistSpiceReader reader; + reader.set_strict (true); + + try { + db::Netlist nl; + tl::InputStream is (path); + reader.read (is, nl); + // strict mode makes this sample fail + EXPECT_EQ (true, false); + } catch (...) { + // .. + } + + db::Netlist nl; + reader.set_strict (false); tl::InputStream is (path); reader.read (is, nl); EXPECT_EQ (nl.to_string (), "circuit SUBCKT ($1=$1,'A[5]<1>'='A[5]<1>','V42(%)'='V42(%)',Z=Z,GND=GND,GND$1=GND$1);\n" - " subcircuit HVPMOS D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n" - " subcircuit HVPMOS D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n" - " subcircuit HVNMOS D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n" - " subcircuit HVNMOS D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n" - " subcircuit HVNMOS D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n" + " subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n" + " subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n" + " subcircuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n" + " subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n" + " subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n" "end;\n" - "circuit HVPMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n" + "circuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" "end;\n" - "circuit HVNMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n" + "circuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" + "end;\n" + "circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" + "end;\n" + "circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" "end;\n" ); } @@ -209,7 +227,7 @@ public: return circuit_name == "HVNMOS" || circuit_name == "HVPMOS"; } - bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms) + bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector &nets, const std::map ¶ms) { if (element == "X") { @@ -235,9 +253,9 @@ public: const std::vector &td = cls->parameter_definitions (); for (std::vector::const_iterator i = td.begin (); i != td.end (); ++i) { - std::map::const_iterator pi = params.find (i->name ()); + auto pi = params.find (i->name ()); if (pi != params.end ()) { - device->set_parameter_value (i->id (), pi->second * 1.5); + device->set_parameter_value (i->id (), pi->second.to_double () * 1.5); } } @@ -262,6 +280,9 @@ TEST(6_ReaderWithDelegate) reader.read (is, nl); EXPECT_EQ (nl.to_string (), + "circuit .TOP ();\n" + " subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);\n" + "end;\n" "circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1);\n" " device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n" " device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n" @@ -270,9 +291,6 @@ TEST(6_ReaderWithDelegate) " device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);\n" " device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);\n" "end;\n" - "circuit .TOP ();\n" - " subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);\n" - "end;\n" ); } @@ -378,8 +396,8 @@ TEST(9_DeviceMultipliers) " device RMODEL2 $6 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" " device RMODEL2 $7 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" " device RES3 $8 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" - " device NMOS $1 (S='1',G='2',D='3',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n" - " device PMOS $2 (S='1',G='2',D='3',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $1 (S='3',G='2',D='1',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $2 (S='3',G='2',D='1',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n" " device CAP $1 (A='1',B='2') (C=2e-09,A=0,P=0);\n" " device CAP $2 (A='3',B='4') (C=1e-09,A=0,P=0);\n" " device CMODEL $3 (A='1',B='2') (C=2e-09,A=0,P=0);\n" @@ -423,8 +441,8 @@ TEST(9_DeviceMultipliers) " device RMODEL2 $6 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" " device RMODEL2 $7 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" " device RES3 $8 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n" - " device NMOS $1 (S='1',G='2',D='3',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n" - " device PMOS $2 (S='1',G='2',D='3',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $1 (S='3',G='2',D='1',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $2 (S='3',G='2',D='1',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n" " device CAP $1 (A='1',B='2') (C=2e-09,A=0,P=0);\n" " device CAP $2 (A='3',B='4') (C=1e-09,A=0,P=0);\n" " device CMODEL $3 (A='1',B='2') (C=2e-09,A=0,P=0);\n" @@ -527,16 +545,16 @@ TEST(13_NoGlobalNetsIfNotUsed) " subcircuit C3 '3' (VDD=VDD,GND=GND);\n" " subcircuit C4 '4' (VDD=VDD,GND=GND);\n" "end;\n" + "circuit C1 (VDD=VDD,GND=GND);\n" + " subcircuit FILLER_CAP '1' (VDD=VDD,GND=GND);\n" + " subcircuit DUMMY '2' ();\n" + "end;\n" "circuit FILLER_CAP (VDD=VDD,GND=GND);\n" " device NMOS '1' (S=GND,G=VDD,D=GND,B=GND) (L=10,W=10,AS=0,AD=0,PS=0,PD=0);\n" "end;\n" "circuit DUMMY ();\n" " device NMOS '1' (S=A,G=A,D=A,B=B) (L=1,W=1,AS=0,AD=0,PS=0,PD=0);\n" "end;\n" - "circuit C1 (VDD=VDD,GND=GND);\n" - " subcircuit FILLER_CAP '1' (VDD=VDD,GND=GND);\n" - " subcircuit DUMMY '2' ();\n" - "end;\n" "circuit C2 ();\n" " subcircuit DUMMY '1' ();\n" "end;\n" @@ -578,15 +596,19 @@ TEST(15_ContinuationWithBlanks) EXPECT_EQ (nl.to_string (), "circuit SUBCKT ($1=$1,'A[5]<1>'='A[5]<1>','V42(%)'='V42(%)',Z=Z,GND=GND,GND$1=GND$1);\n" - " subcircuit HVPMOS D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n" - " subcircuit HVPMOS D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n" - " subcircuit HVNMOS D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n" - " subcircuit HVNMOS D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n" - " subcircuit HVNMOS D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n" + " subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n" + " subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n" + " subcircuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n" + " subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n" + " subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n" "end;\n" - "circuit HVPMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n" + "circuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" "end;\n" - "circuit HVNMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n" + "circuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" + "end;\n" + "circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" + "end;\n" + "circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n" "end;\n" ); } @@ -611,3 +633,198 @@ TEST(16_issue898) "end;\n" ); } + +TEST(17_RecursiveExpansion) +{ + db::Netlist nl, nl2; + + { + std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader17.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl); + } + + EXPECT_EQ (nl.to_string (), + "circuit .TOP ();\n" + " subcircuit 'SUB1(L=0.15,W=1.5)' SUB1A (N1=A,N2=B,N3=C);\n" + " subcircuit 'SUB1(L=0.25,W=3)' SUB1B (N1=A,N2=B,N3=C);\n" + "end;\n" + "circuit 'SUB1(L=0.15,W=1.5)' (N1=N1,N2=N2,N3=N3);\n" + " subcircuit 'SUB2(L=0.15,M=1,W=1.5)' SUB2A (N1=N1,N2=N2,N3=N3);\n" + " subcircuit 'SUB2(L=0.15,M=2,W=1.5)' SUB2B (N1=N1,N2=N2,N3=N3);\n" + "end;\n" + "circuit 'SUB2(L=0.15,M=1,W=1.5)' (N1=N1,N2=N2,N3=N3);\n" + " device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=150000,W=1500000,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + "circuit 'SUB2(L=0.15,M=2,W=1.5)' (N1=N1,N2=N2,N3=N3);\n" + " device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=150000,W=3000000,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + "circuit 'SUB1(L=0.25,W=3)' (N1=N1,N2=N2,N3=N3);\n" + " subcircuit 'SUB2(L=0.25,M=1,W=3)' SUB2A (N1=N1,N2=N2,N3=N3);\n" + " subcircuit 'SUB2(L=0.25,M=2,W=3)' SUB2B (N1=N1,N2=N2,N3=N3);\n" + "end;\n" + "circuit 'SUB2(L=0.25,M=1,W=3)' (N1=N1,N2=N2,N3=N3);\n" + " device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=250000,W=3000000,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + "circuit 'SUB2(L=0.25,M=2,W=3)' (N1=N1,N2=N2,N3=N3);\n" + " device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=250000,W=6000000,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + ); + + { + std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader17b.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl2); + } + + EXPECT_EQ (nl2.to_string (), nl.to_string ()); +} + +TEST(18_XSchemOutput) +{ + db::Netlist nl; + + std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader18.cir"); + + db::NetlistSpiceReader reader; + tl::InputStream is (path); + reader.read (is, nl); + + EXPECT_EQ (nl.to_string (), + "circuit .TOP ();\n" + " subcircuit 'PMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' XPMOS (D=Q,G=I,S=VDD,B=VDD);\n" + " subcircuit 'NMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' XNMOS (D=Q,G=I,S=VSS,B=VSS);\n" + " subcircuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY0 (D=VSS,G=VSS,S=VSS,B=VSS);\n" + " subcircuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY1 (D=VSS,G=VSS,S=VSS,B=VSS);\n" + " subcircuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY2 (D=VDD,G=VDD,S=VDD,B=VDD);\n" + " subcircuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY3 (D=VDD,G=VDD,S=VDD,B=VDD);\n" + "end;\n" + "circuit 'PMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' (D=D,G=G,S=S,B=B);\n" + " device SKY130_FD_PR__PFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=6,AS=0.32625,AD=0.2175,PS=2.685,PD=1.79);\n" + "end;\n" + "circuit 'NMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' (D=D,G=G,S=S,B=B);\n" + " device SKY130_FD_PR__NFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=6,AS=0.32625,AD=0.2175,PS=2.685,PD=1.79);\n" + "end;\n" + "circuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' (D=D,G=G,S=S,B=B);\n" + " device SKY130_FD_PR__NFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=3,AS=0.435,AD=0.2175,PS=3.58,PD=1.79);\n" + "end;\n" + "circuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' (D=D,G=G,S=S,B=B);\n" + " device SKY130_FD_PR__PFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=3,AS=0.435,AD=0.2175,PS=3.58,PD=1.79);\n" + "end;\n" + ); +} + +TEST(100_ExpressionParser) +{ + std::map vars; + vars["A"] = 17.5; + vars["B"] = 42; + vars["S"] = "string"; + + tl::Variant v; + + db::NetlistSpiceReaderExpressionParser parser (&vars); + + EXPECT_EQ (parser.read ("1.75").to_string (), "1.75"); + EXPECT_EQ (parser.read ("-1.75").to_string (), "-1.75"); + EXPECT_EQ (parser.read ("-a*0.1").to_string (), "-1.75"); + EXPECT_EQ (parser.read ("-A*0.1").to_string (), "-1.75"); + EXPECT_EQ (parser.read ("b/6").to_string (), "7"); + EXPECT_EQ (parser.read ("B/6").to_string (), "7"); + EXPECT_EQ (parser.read ("s").to_string (), "string"); + EXPECT_EQ (parser.read ("S").to_string (), "string"); + EXPECT_EQ (parser.read ("!0").to_string (), "true"); + EXPECT_EQ (parser.read ("!1").to_string (), "false"); + EXPECT_EQ (parser.read ("4*2+1").to_string (), "9"); + EXPECT_EQ (parser.read ("4*2-1").to_string (), "7"); + EXPECT_EQ (parser.read ("4/2-1").to_string (), "1"); + EXPECT_EQ (parser.read ("4%2-1").to_string (), "-1"); + EXPECT_EQ (parser.read ("5%2-1").to_string (), "0"); + EXPECT_EQ (parser.read ("2**2*2+1").to_string (), "9"); + EXPECT_EQ (parser.read ("2**2*(2+1)").to_string (), "12"); + EXPECT_EQ (parser.read ("pow(2,2)*(2+1)").to_string (), "12"); + EXPECT_EQ (parser.read ("POW(2,2)*(2+1)").to_string (), "12"); + EXPECT_EQ (parser.read ("pwr(2,2)*(2+1)").to_string (), "12"); + EXPECT_EQ (parser.read ("PWR(2,2)*(2+1)").to_string (), "12"); + EXPECT_EQ (parser.read ("3==2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("4==2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("3!=2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("4!=2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("2<2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("3<2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("4<2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("2<=2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("3<=2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("4<=2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("2>2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("3>2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("4>2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("2>=2+1").to_string (), "false"); + EXPECT_EQ (parser.read ("3>=2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("4>=2+1").to_string (), "true"); + EXPECT_EQ (parser.read ("1==2||2==2").to_string (), "true"); + EXPECT_EQ (parser.read ("1==2||3==2").to_string (), "false"); + EXPECT_EQ (parser.read ("1==2&&2==2").to_string (), "false"); + EXPECT_EQ (parser.read ("1==1&&2==2").to_string (), "true"); + EXPECT_EQ (parser.read ("1==2?2:3").to_string (), "3"); + EXPECT_EQ (parser.read ("ternery_fcn(1==2,2,3)").to_string (), "3"); + EXPECT_EQ (parser.read ("1==1?2:3").to_string (), "2"); + EXPECT_EQ (parser.read ("ternery_fcn(1==1,2,3)").to_string (), "2"); + + EXPECT_EQ (parser.read ("sin(0)").to_string (), "0"); + EXPECT_EQ (parser.read ("sin(atan(1.0)*2)").to_string (), "1"); + EXPECT_EQ (parser.read ("cos(0)").to_string (), "1"); + EXPECT_EQ (parser.read ("cos(atan(1.0)*2)").to_string (), "0"); + EXPECT_EQ (parser.read ("tan(0)").to_string (), "0"); + EXPECT_EQ (parser.read ("tan(atan(1.0))").to_string (), "1"); + EXPECT_EQ (parser.read ("sin(asin(0.5))").to_string (), "0.5"); + EXPECT_EQ (parser.read ("cos(acos(0.5))").to_string (), "0.5"); + EXPECT_EQ (parser.read ("ln(exp(0.5))").to_string (), "0.5"); + EXPECT_EQ (parser.read ("exp(0.0)").to_string (), "1"); + EXPECT_EQ (parser.read ("log(10**0.5)").to_string (), "0.5"); + EXPECT_EQ (parser.read ("int(-0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("int(-1.5)").to_string (), "-1"); + EXPECT_EQ (parser.read ("int(0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("int(1.5)").to_string (), "1"); + EXPECT_EQ (parser.read ("floor(-0.5)").to_string (), "-1"); + EXPECT_EQ (parser.read ("floor(-1.5)").to_string (), "-2"); + EXPECT_EQ (parser.read ("floor(0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("floor(1.5)").to_string (), "1"); + EXPECT_EQ (parser.read ("ceil(-0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("ceil(-1.5)").to_string (), "-1"); + EXPECT_EQ (parser.read ("ceil(0.5)").to_string (), "1"); + EXPECT_EQ (parser.read ("ceil(1.5)").to_string (), "2"); + EXPECT_EQ (parser.read ("nint(-0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("nint(-1.5)").to_string (), "-2"); + EXPECT_EQ (parser.read ("nint(0.5)").to_string (), "0"); + EXPECT_EQ (parser.read ("nint(1.5)").to_string (), "2"); + EXPECT_EQ (parser.read ("min(4,1,3)").to_string (), "1"); + EXPECT_EQ (parser.read ("min(4,3)").to_string (), "3"); + EXPECT_EQ (parser.read ("min(4)").to_string (), "4"); + EXPECT_EQ (parser.read ("max(1,4,3)").to_string (), "4"); + EXPECT_EQ (parser.read ("max(4,3)").to_string (), "4"); + EXPECT_EQ (parser.read ("max(4)").to_string (), "4"); + EXPECT_EQ (parser.read ("max(a,b)").to_string (), "42"); + + EXPECT_EQ (parser.try_read ("a syntax error", v), false); + v = tl::Variant (); + EXPECT_EQ (parser.try_read ("1+2*(2+1)-1", v), true); + EXPECT_EQ (v.to_string (), "6"); + EXPECT_EQ (parser.try_read ("{1+2*(2+1)-1)", v), false); + EXPECT_EQ (parser.try_read ("'1+2*(2+1)-1)", v), false); + EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1)", v), false); + EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1'", v), false); + v = tl::Variant (); + EXPECT_EQ (parser.try_read ("{1+2*(2+1)-1}", v), true); + EXPECT_EQ (v.to_string (), "6"); + v = tl::Variant (); + EXPECT_EQ (parser.try_read ("'1+2*(2+1)-1'", v), true); + EXPECT_EQ (v.to_string (), "6"); + v = tl::Variant (); + EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1\"", v), true); + EXPECT_EQ (v.to_string (), "6"); +} diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc index a794575fa..7fb2b8ae4 100644 --- a/src/lvs/unit_tests/lvsSimpleTests.cc +++ b/src/lvs/unit_tests/lvsSimpleTests.cc @@ -159,6 +159,7 @@ TEST(11_device_scaling) TEST(12_simple_dmos) { run_test (_this, "ringo_simple_dmos", "ringo.gds"); + run_test (_this, "ringo_simple_dmos_fixed", "ringo_fixed_sources.gds"); } TEST(13_simple_ringo_device_subcircuits) diff --git a/src/lvs/unit_tests/lvsTests.cc b/src/lvs/unit_tests/lvsTests.cc index b3eb9c7f6..18c0810bf 100644 --- a/src/lvs/unit_tests/lvsTests.cc +++ b/src/lvs/unit_tests/lvsTests.cc @@ -142,7 +142,7 @@ TEST(16_private) TEST(17_private) { test_is_long_runner (); - run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_3.lvsdb"); + run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_4.lvsdb"); } TEST(18_private) @@ -160,12 +160,12 @@ TEST(19_private) TEST(20_private) { // test_is_long_runner (); - run_test (_this, "test_20.lylvs", "test_20.cir.gz", "test_20.gds.gz", true, "test_20b_3.lvsdb"); + run_test (_this, "test_20.lylvs", "test_20.cir.gz", "test_20.gds.gz", true, "test_20_4.lvsdb"); } TEST(21_private) { - run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21.lvsdb"); + run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21_2.lvsdb"); } // issue #1021 diff --git a/src/tl/tl/tlVariant.cc b/src/tl/tl/tlVariant.cc index 58de50779..2360b9ee7 100644 --- a/src/tl/tl/tlVariant.cc +++ b/src/tl/tl/tlVariant.cc @@ -27,6 +27,7 @@ #include #include +#include #if defined(HAVE_QT) @@ -1054,6 +1055,18 @@ normalized_type (Variant::type type1, Variant::type type2) } } +static const double epsilon = 1e-13; + +static inline bool fequal (double a, double b) +{ + double avg = 0.5 * (fabs (a) + fabs (b)); + return fabs (a - b) <= epsilon * avg; +} + +static inline bool fless (double a, double b) +{ + return fequal (a, b) ? false : a < b; +} bool Variant::operator== (const tl::Variant &d) const @@ -1083,7 +1096,7 @@ Variant::operator== (const tl::Variant &d) const } else if (t == t_id) { return m_var.m_id == d.m_var.m_id; } else if (t == t_double) { - return to_double () == d.to_double (); + return fequal (to_double (), d.to_double ()); } else if (t == t_string) { return strcmp (to_string (), d.to_string ()) == 0; } else if (t == t_bytearray) { @@ -1139,7 +1152,7 @@ Variant::operator< (const tl::Variant &d) const } else if (t == t_id) { return m_var.m_id < d.m_var.m_id; } else if (t == t_double) { - return to_double () < d.to_double (); + return fless (to_double (), d.to_double ()); } else if (t == t_string) { return strcmp (to_string (), d.to_string ()) < 0; } else if (t == t_bytearray) { diff --git a/src/tl/unit_tests/tlVariantTests.cc b/src/tl/unit_tests/tlVariantTests.cc index cb6687d97..2a0a62a99 100644 --- a/src/tl/unit_tests/tlVariantTests.cc +++ b/src/tl/unit_tests/tlVariantTests.cc @@ -1059,7 +1059,35 @@ TEST(5) EXPECT_EQ (m [" 3"], 0); } +// fuzzy compare of doubles +TEST(6) +{ + volatile double a = 10.0; + EXPECT_EQ (tl::Variant (0.0) == tl::Variant (0.0), true); + + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (1.0 / a), true); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1e-14)), true); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 0.9e-13)), true); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1.1e-13)), false); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1e-12)), false); + EXPECT_EQ (tl::Variant (-0.1) == tl::Variant (-0.1 * (1.0 + 0.9e-13)), true); + EXPECT_EQ (tl::Variant (-0.1) == tl::Variant (-0.1 * (1.0 + 1.1e-13)), false); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (-0.1 * (1.0 + 0.9e-13)), false); + EXPECT_EQ (tl::Variant (0.1) == tl::Variant (-0.1 * (1.0 + 1.1e-13)), false); + + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (1.0 / a), false); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1e-14)), false); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 0.9e-13)), false); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1.1e-13)), true); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1e-12)), true); + EXPECT_EQ (tl::Variant (-0.1) < tl::Variant (-0.1 * (1.0 + 0.9e-13)), false); + EXPECT_EQ (tl::Variant (-0.1) < tl::Variant (-0.1 * (1.0 + 1.1e-13)), false); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (-0.1 * (1.0 + 0.9e-13)), false); + EXPECT_EQ (tl::Variant (0.1) < tl::Variant (-0.1 * (1.0 + 1.1e-13)), false); + EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 0.9e-13)) < tl::Variant (-0.1), false); + EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 1.1e-13)) < tl::Variant (-0.1), true); + EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 0.9e-13)) < tl::Variant (0.1), true); + EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 1.1e-13)) < tl::Variant (0.1), true); } - - +} diff --git a/testdata/algo/lvs_test1_au.lvsdb.1 b/testdata/algo/lvs_test1_au.lvsdb.1 index 5a39ce9f2..dab36afd2 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.1 +++ b/testdata/algo/lvs_test1_au.lvsdb.1 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/algo/lvs_test1_au.lvsdb.2 b/testdata/algo/lvs_test1_au.lvsdb.2 index 20cf60f64..eb03fd506 100644 --- a/testdata/algo/lvs_test1_au.lvsdb.2 +++ b/testdata/algo/lvs_test1_au.lvsdb.2 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.1 b/testdata/algo/lvs_test1b_au.lvsdb.1 index 677076a96..cd1225bf0 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.1 +++ b/testdata/algo/lvs_test1b_au.lvsdb.1 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/algo/lvs_test1b_au.lvsdb.2 b/testdata/algo/lvs_test1b_au.lvsdb.2 index a842f1785..5ca795b84 100644 --- a/testdata/algo/lvs_test1b_au.lvsdb.2 +++ b/testdata/algo/lvs_test1b_au.lvsdb.2 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/algo/lvs_test2_au.lvsdb.1 b/testdata/algo/lvs_test2_au.lvsdb.1 index e126c6a69..a24505189 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.1 +++ b/testdata/algo/lvs_test2_au.lvsdb.1 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) @@ -497,6 +497,37 @@ reference( pin(5 1) ) + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + ) circuit(RINGO @@ -567,37 +598,6 @@ reference( ) ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) ) # Cross reference diff --git a/testdata/algo/lvs_test2_au.lvsdb.2 b/testdata/algo/lvs_test2_au.lvsdb.2 index b6eb7da64..969594ebe 100644 --- a/testdata/algo/lvs_test2_au.lvsdb.2 +++ b/testdata/algo/lvs_test2_au.lvsdb.2 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) @@ -497,6 +497,37 @@ reference( pin(5 1) ) + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + ) circuit(RINGO @@ -567,37 +598,6 @@ reference( ) ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) ) # Cross reference diff --git a/testdata/algo/lvs_test2b_au.lvsdb.1 b/testdata/algo/lvs_test2b_au.lvsdb.1 index 1bec1de6c..ee2bd4020 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.1 +++ b/testdata/algo/lvs_test2b_au.lvsdb.1 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) @@ -497,6 +497,37 @@ reference( pin(5 1) ) + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + ) circuit(RINGO @@ -567,37 +598,6 @@ reference( ) ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) ) # Cross reference diff --git a/testdata/algo/lvs_test2b_au.lvsdb.2 b/testdata/algo/lvs_test2b_au.lvsdb.2 index 23f1b8b03..47e45e369 100644 --- a/testdata/algo/lvs_test2b_au.lvsdb.2 +++ b/testdata/algo/lvs_test2b_au.lvsdb.2 @@ -447,9 +447,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 5) terminal(G 2) - terminal(D 5) + terminal(D 3) terminal(B 1) ) device(2 NMOS @@ -460,9 +460,9 @@ reference( param(AD 1.4) param(PS 6.85) param(PD 6.85) - terminal(S 3) + terminal(S 4) terminal(G 2) - terminal(D 4) + terminal(D 3) terminal(B 6) ) @@ -497,6 +497,37 @@ reference( pin(5 1) ) + ) + circuit(INV2PAIRX + + # Nets + net(1 name('1')) + net(2 name('2')) + net(3 name('3')) + net(4 name('4')) + net(5 name('5')) + net(6 name('6')) + net(7 name('7')) + + # Outgoing pins and their connections to nets + pin(1 name('1')) + pin(2 name('2')) + pin(3 name('3')) + pin(4 name('4')) + pin(5 name('5')) + pin(6 name('6')) + pin(7 name('7')) + + # Subcircuits and their connections + circuit(1 INV2 name($2) + pin(0 7) + pin(1 4) + pin(2 6) + pin(3 3) + pin(4 2) + pin(5 1) + ) + ) circuit(RINGO @@ -567,37 +598,6 @@ reference( ) ) - circuit(INV2PAIRX - - # Nets - net(1 name('1')) - net(2 name('2')) - net(3 name('3')) - net(4 name('4')) - net(5 name('5')) - net(6 name('6')) - net(7 name('7')) - - # Outgoing pins and their connections to nets - pin(1 name('1')) - pin(2 name('2')) - pin(3 name('3')) - pin(4 name('4')) - pin(5 name('5')) - pin(6 name('6')) - pin(7 name('7')) - - # Subcircuits and their connections - circuit(1 INV2 name($2) - pin(0 7) - pin(1 4) - pin(2 6) - pin(3 3) - pin(4 2) - pin(5 1) - ) - - ) ) # Cross reference diff --git a/testdata/algo/nreader1.cir b/testdata/algo/nreader1.cir index d27c27f3f..c833a5b59 100644 --- a/testdata/algo/nreader1.cir +++ b/testdata/algo/nreader1.cir @@ -13,5 +13,5 @@ R$2 3 1 7650 * device instance $3 4.665,0.335 RES R$3 3 2 2670 * device instance $4 1.765,7.485 HVPMOS -M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U +M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U .ENDS TOP diff --git a/testdata/algo/nreader17.cir b/testdata/algo/nreader17.cir new file mode 100644 index 000000000..42ebb0aaf --- /dev/null +++ b/testdata/algo/nreader17.cir @@ -0,0 +1,15 @@ + +* recursive expansion of parametrized subcircuits + +Xsub1a a b c sub1 w=1.5 l=0.15 +Xsub1b a b c sub1 w=3.0 l=0.25 + +.subckt sub1 n1 n2 n3 w=1.0 l=0.5 + Xsub2a n1 n2 n3 sub2 w l m=1 + Xsub2b n1 n2 n3 sub2 w l m=2 +.ends + +.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0 + Mnmos n1 n2 n3 n1 nmos w=w l=l m=m +.ends + diff --git a/testdata/algo/nreader17b.cir b/testdata/algo/nreader17b.cir new file mode 100644 index 000000000..0c2c62722 --- /dev/null +++ b/testdata/algo/nreader17b.cir @@ -0,0 +1,24 @@ + +* recursive expansion of parametrized subcircuits + +.param w1 1.5 w2 {w1*2} +.param l1 0.15 l2 'l1+0.1' + +Xsub1a a b c sub1 w=w1 l=l1 +Xsub1b a b c sub1 w=w2 l=l2 + +.subckt sub1 n1 n2 n3 w l + * declares w and l parameters instead of nodes: + w = 1.0 + l = 1.0 + .param w1 = w + .param l1 = l + Xsub2a n1 n2 n3 sub2 w=w1 l=l1 m=1 + .param w2 "w+0.0" l2 l*(0.5+0.5) + Xsub2b n1 n2 n3 sub2 w=w2 l=l2 m=2 +.ends + +.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0 + Mnmos n1 n2 n3 n1 nmos w=w l=l m=m +.ends + diff --git a/testdata/algo/nreader18.cir b/testdata/algo/nreader18.cir new file mode 100644 index 000000000..f2b61b9da --- /dev/null +++ b/testdata/algo/nreader18.cir @@ -0,0 +1,59 @@ +** sch_path: +*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/inverter1_generated_sky130_fd_pr/inverter1/inverter1.sch +**.subckt inverter1 I Q VDD VSS +*.ipin I +*.opin Q +*.iopin VDD +*.iopin VSS +XXpmos Q I VDD VDD pmos4_standard w=1.5u l=150n nf=4 +XXnmos Q I VSS VSS nmos4_standard w=1.5u l=150n nf=4 +XXDUMMY0 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2 +XXDUMMY1 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2 +XXDUMMY2 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2 +XXDUMMY3 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2 +**.ends + +* expanding symbol: BAG_prim/pmos4_standard/pmos4_standard.sym # of pins=4 +** sym_path: +*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sym +** sch_path: +*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sch +.subckt pmos4_standard D G S B model w l nf +w=100n +l=18n +nf=4 +model=pmos4_standard +spiceprefix=X + +*.iopin D +*.iopin G +*.iopin S +*.iopin B +MM1 D G S B sky130_fd_pr__pfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u' ++ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W' ++ sa=0 sb=0 sd=0 mult=1 m=nf +.ends + + +* expanding symbol: BAG_prim/nmos4_standard/nmos4_standard.sym # of pins=4 +** sym_path: +*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sym +** sch_path: +*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sch +.subckt nmos4_standard D G S B model w l nf +w=100n +l=18n +nf=4 +model=nmos4_standard +spiceprefix=X + +*.iopin D +*.iopin G +*.iopin S +*.iopin B +MM1 D G S B sky130_fd_pr__nfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u' ++ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W' ++ sa=0 sb=0 sd=0 mult=1 m=nf +.ends + +.end diff --git a/testdata/algo/nreader1b.cir b/testdata/algo/nreader1b.cir index 041d22c26..a46df8d02 100644 --- a/testdata/algo/nreader1b.cir +++ b/testdata/algo/nreader1b.cir @@ -13,5 +13,5 @@ R$2 3 1 7650 M2 * device instance $3 4.665,0.335 RES, model M3 R$3 3 2 2670 M3 * device instance $4 1.765,7.485 HVPMOS -M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U +M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U .ENDS TOP diff --git a/testdata/algo/nreader2.cir b/testdata/algo/nreader2.cir index 32e7dfc09..537af4996 100644 --- a/testdata/algo/nreader2.cir +++ b/testdata/algo/nreader2.cir @@ -54,13 +54,13 @@ X$12 12 13 15 12 11 15 INVX1 * net 6 A * net 7 BULK * device instance $1 0.85,5.8 LVPMOS -M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 1.55,5.8 LVPMOS -M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 0.85,2.135 LVNMOS -M$3 3 6 8 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 1.55,2.135 LVNMOS -M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 * cell INVX1 @@ -77,7 +77,7 @@ M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U * net 5 IN * net 6 BULK * device instance $1 0.85,5.8 LVPMOS -M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 0.85,2.135 LVNMOS -M$2 3 5 2 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 diff --git a/testdata/algo/nreader3.cir b/testdata/algo/nreader3.cir index b9aaf131a..37929474f 100644 --- a/testdata/algo/nreader3.cir +++ b/testdata/algo/nreader3.cir @@ -1,13 +1,13 @@ .subckt INVX1 1 2 3 4 5 6 - m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um - m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um + m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um + m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um .ends .subckt ND2X1 1 2 3 4 5 6 7 - m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um - m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um - m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um - m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um + m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um + m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um + m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um + m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um .ends ND2X1 .subckt RINGO 11 12 13 14 15 diff --git a/testdata/algo/nreader7.cir b/testdata/algo/nreader7.cir index 210af361c..d8d8c4493 100644 --- a/testdata/algo/nreader7.cir +++ b/testdata/algo/nreader7.cir @@ -19,13 +19,13 @@ X$12 OUT FB INVX1 .ENDS RINGO .SUBCKT ND2X1 OUT B A -M$1 OUT A VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U -M$2 VDD B OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U -M$3 VSS A INT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U -M$4 INT B OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$1 VDD A OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 OUT B VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 INT A VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$4 OUT B INT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 .SUBCKT INVX1 OUT IN -M$1 VDD IN OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U -M$2 VSS IN OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$1 OUT IN VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 OUT IN VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 diff --git a/testdata/algo/nreader8b.cir b/testdata/algo/nreader8b.cir index ddd4bee8c..4c3898635 100644 --- a/testdata/algo/nreader8b.cir +++ b/testdata/algo/nreader8b.cir @@ -1,8 +1,8 @@ .subckt ND2X1 1 2 3 4 5 6 7 - m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um - m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um - m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um - m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um + m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um + m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um + m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um + m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um .ends ND2X1 diff --git a/testdata/algo/nreader8x.cir b/testdata/algo/nreader8x.cir index f3a8e9ced..e4691630b 100644 --- a/testdata/algo/nreader8x.cir +++ b/testdata/algo/nreader8x.cir @@ -1,3 +1,3 @@ -m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um -m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um +m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um +m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um diff --git a/testdata/algo/nwriter11_au.txt b/testdata/algo/nwriter11_au.txt index b97ae9991..2571c4846 100644 --- a/testdata/algo/nwriter11_au.txt +++ b/testdata/algo/nwriter11_au.txt @@ -28,7 +28,7 @@ XSC2 3 7 4 3 C1 * net 4 n4 * net 5 n5 * device instance $1 r0 *1 0,0 M4CLS -M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U +M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U * device instance $2 r0 *1 0,0 M4CLS -M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U +M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U .ENDS C1 diff --git a/testdata/algo/nwriter11b_au.txt b/testdata/algo/nwriter11b_au.txt index a1e95a4df..a9310b9cd 100644 --- a/testdata/algo/nwriter11b_au.txt +++ b/testdata/algo/nwriter11b_au.txt @@ -18,7 +18,7 @@ XSC2 n3 nc_12 n4 n3 C1 * pin p4 .SUBCKT C1 n1 n2 n4 n5 * device instance $1 r0 *1 0,0 M4CLS -M$1 n1 n4 n3 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U +M$1 n3 n4 n1 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U * device instance $2 r0 *1 0,0 M4CLS -M$2 n3 n4 n2 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U +M$2 n2 n4 n3 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U .ENDS C1 diff --git a/testdata/algo/nwriter5_au.txt b/testdata/algo/nwriter5_au.txt index 4c6c38a22..8f4dd36d0 100644 --- a/testdata/algo/nwriter5_au.txt +++ b/testdata/algo/nwriter5_au.txt @@ -10,7 +10,7 @@ * net 3 n3 * net 4 n4 * device instance $1 r0 *1 0,0 M3CLS -M$1 1 4 3 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U +M$1 3 4 1 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U * device instance $2 r0 *1 0,0 M3CLS -M$2 3 4 2 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U +M$2 2 4 3 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U .ENDS C1 diff --git a/testdata/algo/nwriter6_au.txt b/testdata/algo/nwriter6_au.txt index f552187d0..79033a8e4 100644 --- a/testdata/algo/nwriter6_au.txt +++ b/testdata/algo/nwriter6_au.txt @@ -12,7 +12,7 @@ * net 4 n4 * net 5 n5 * device instance $1 r0 *1 0,0 M4CLS -M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U +M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U * device instance $2 r0 *1 0,0 M4CLS -M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U +M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U .ENDS C1 diff --git a/testdata/algo/nwriter8_au.txt b/testdata/algo/nwriter8_au.txt index f9f770877..cd1d755c1 100644 --- a/testdata/algo/nwriter8_au.txt +++ b/testdata/algo/nwriter8_au.txt @@ -28,7 +28,7 @@ XSC2 3 2 4 3 C1 * net 4 n4 * net 5 n5 * device instance $1 r0 *1 0,0 M4CLS -M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U +M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U * device instance $2 r0 *1 0,0 M4CLS -M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U +M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U .ENDS C1 diff --git a/testdata/lvs/double_height.cir b/testdata/lvs/double_height.cir index f2def2326..6c6f92e17 100644 --- a/testdata/lvs/double_height.cir +++ b/testdata/lvs/double_height.cir @@ -10,8 +10,8 @@ X$2 VSS VDD A1 Q1 INV .ENDS INV2 .SUBCKT INV \$1 \$2 \$3 \$4 -M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U -M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U .ENDS INV diff --git a/testdata/lvs/double_height2.cir b/testdata/lvs/double_height2.cir index 882e59444..82158ccf0 100644 --- a/testdata/lvs/double_height2.cir +++ b/testdata/lvs/double_height2.cir @@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV .ENDS INV2 .SUBCKT INV \$1 \$2 \$3 \$4 -M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U -M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U .ENDS INV diff --git a/testdata/lvs/double_height2_texts.cir b/testdata/lvs/double_height2_texts.cir index 882e59444..82158ccf0 100644 --- a/testdata/lvs/double_height2_texts.cir +++ b/testdata/lvs/double_height2_texts.cir @@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV .ENDS INV2 .SUBCKT INV \$1 \$2 \$3 \$4 -M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U -M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U .ENDS INV diff --git a/testdata/lvs/floating.cir b/testdata/lvs/floating.cir index edd64b16f..9acc99ffe 100644 --- a/testdata/lvs/floating.cir +++ b/testdata/lvs/floating.cir @@ -44,7 +44,7 @@ X$2 3 5 2 6 INVX1 * net 3 IN * net 4 VSS * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 diff --git a/testdata/lvs/floating.lvsdb b/testdata/lvs/floating.lvsdb index da867a055..3822292b2 100644 --- a/testdata/lvs/floating.lvsdb +++ b/testdata/lvs/floating.lvsdb @@ -284,9 +284,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 2) terminal(B 3) ) device(2 PMOS @@ -297,9 +297,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 4) terminal(G 1) - terminal(D 4) + terminal(D 2) terminal(B 4) ) diff --git a/testdata/lvs/inv.lvsdb b/testdata/lvs/inv.lvsdb index 246a05b96..0c4e3258a 100644 --- a/testdata/lvs/inv.lvsdb +++ b/testdata/lvs/inv.lvsdb @@ -197,9 +197,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 3) terminal(G 2) - terminal(D 3) + terminal(D 6) terminal(B 4) ) device(2 NMOS @@ -210,9 +210,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 1) terminal(G 2) - terminal(D 1) + terminal(D 3) terminal(B 5) ) diff --git a/testdata/lvs/inv2.lvsdb b/testdata/lvs/inv2.lvsdb index 3e799862b..0be15142a 100644 --- a/testdata/lvs/inv2.lvsdb +++ b/testdata/lvs/inv2.lvsdb @@ -167,9 +167,9 @@ H( E(AD 0) E(PS 0) E(PD 0) - T(S 4) + T(S 3) T(G 2) - T(D 3) + T(D 4) T(B 4) ) D(2 NMOS @@ -180,9 +180,9 @@ H( E(AD 0) E(PS 0) E(PD 0) - T(S 3) + T(S 1) T(G 2) - T(D 1) + T(D 3) T(B 1) ) ) diff --git a/testdata/lvs/inv2_layout.cir b/testdata/lvs/inv2_layout.cir index f55adc82a..d15ed1a1d 100644 --- a/testdata/lvs/inv2_layout.cir +++ b/testdata/lvs/inv2_layout.cir @@ -7,7 +7,7 @@ * net 3 OUT * net 4 VSS * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 2 1 3 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U +M$1 3 1 2 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U * device instance $2 r0 *1 1.025,0.65 NMOS -M$2 4 1 3 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U +M$2 3 1 4 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U .ENDS INVERTER_WITH_DIODES diff --git a/testdata/lvs/inv_layout.cir b/testdata/lvs/inv_layout.cir index c75dde3e8..c8170f2c9 100644 --- a/testdata/lvs/inv_layout.cir +++ b/testdata/lvs/inv_layout.cir @@ -9,7 +9,7 @@ * net 5 NWELL * net 6 SUBSTRATE * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 3 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U +M$1 4 1 3 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U * device instance $2 r0 *1 1.025,0.65 NMOS -M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U +M$2 4 1 2 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U .ENDS INVERTER diff --git a/testdata/lvs/invchain_cheat.cir.1 b/testdata/lvs/invchain_cheat.cir.1 index f4bef3947..95fe6cd10 100644 --- a/testdata/lvs/invchain_cheat.cir.1 +++ b/testdata/lvs/invchain_cheat.cir.1 @@ -18,8 +18,8 @@ X$2 \$I2 \$I4 \$I5 \$I7 INV .ENDS INV2 .SUBCKT INV \$1 \$2 \$3 \$4 -M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U -M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U +M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U + PD=3.45U .ENDS INV diff --git a/testdata/lvs/nand2_split_gate.cir.1 b/testdata/lvs/nand2_split_gate.cir.1 index 5c739a1a4..d29fe761c 100644 --- a/testdata/lvs/nand2_split_gate.cir.1 +++ b/testdata/lvs/nand2_split_gate.cir.1 @@ -13,11 +13,11 @@ * net 5 VDD * net 6 VSS * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U +M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U * device instance $2 r0 *1 1.775,4.95 PMOS -M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U +M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U * device instance $3 r0 *1 1.025,2 NMOS -M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U +M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U * device instance $4 r0 *1 1.775,2 NMOS -M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U +M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U .ENDS NAND2_WITH_DIODES diff --git a/testdata/lvs/nand2_split_gate.cir.2 b/testdata/lvs/nand2_split_gate.cir.2 index 6bceb7353..3d5aa4d5f 100644 --- a/testdata/lvs/nand2_split_gate.cir.2 +++ b/testdata/lvs/nand2_split_gate.cir.2 @@ -13,11 +13,11 @@ * net 5 VDD * net 6 VSS * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U +M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U * device instance $2 r0 *1 1.775,4.95 PMOS -M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U +M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U * device instance $3 r0 *1 1.025,0.65 NMOS -M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U +M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U * device instance $4 r0 *1 1.775,0.65 NMOS -M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U +M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U .ENDS NAND2_WITH_DIODES diff --git a/testdata/lvs/nand2_split_gate.cir.3 b/testdata/lvs/nand2_split_gate.cir.3 new file mode 100644 index 000000000..3d5aa4d5f --- /dev/null +++ b/testdata/lvs/nand2_split_gate.cir.3 @@ -0,0 +1,23 @@ +* Extracted by KLayout + +* cell NAND2_WITH_DIODES +* pin B +* pin A +* pin OUT +* pin VDD +* pin VSS +.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6 +* net 1 B +* net 2 A +* net 4 OUT +* net 5 VDD +* net 6 VSS +* device instance $1 r0 *1 1.025,4.95 PMOS +M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U +* device instance $2 r0 *1 1.775,4.95 PMOS +M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U +* device instance $3 r0 *1 1.025,0.65 NMOS +M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U +* device instance $4 r0 *1 1.775,0.65 NMOS +M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U +.ENDS NAND2_WITH_DIODES diff --git a/testdata/lvs/nand2_split_gate.lvsdb.1 b/testdata/lvs/nand2_split_gate.lvsdb.1 index e0d758a88..0ade4db56 100644 --- a/testdata/lvs/nand2_split_gate.lvsdb.1 +++ b/testdata/lvs/nand2_split_gate.lvsdb.1 @@ -335,9 +335,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 2) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(2 PMOS @@ -348,9 +348,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(3 NMOS @@ -361,9 +361,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 6) terminal(G 2) - terminal(D 6) + terminal(D 4) terminal(B 4) ) device(4 NMOS @@ -374,9 +374,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 6) terminal(B 4) ) diff --git a/testdata/lvs/nand2_split_gate.lvsdb.2 b/testdata/lvs/nand2_split_gate.lvsdb.2 index 4742977a2..0c99205ab 100644 --- a/testdata/lvs/nand2_split_gate.lvsdb.2 +++ b/testdata/lvs/nand2_split_gate.lvsdb.2 @@ -335,9 +335,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 2) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(2 PMOS @@ -348,9 +348,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(3 NMOS @@ -361,9 +361,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 6) terminal(G 2) - terminal(D 6) + terminal(D 4) terminal(B 4) ) device(4 NMOS @@ -374,9 +374,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 6) terminal(B 4) ) diff --git a/testdata/lvs/nand2_split_gate_early.cir.1 b/testdata/lvs/nand2_split_gate_early.cir.1 index 5c739a1a4..d29fe761c 100644 --- a/testdata/lvs/nand2_split_gate_early.cir.1 +++ b/testdata/lvs/nand2_split_gate_early.cir.1 @@ -13,11 +13,11 @@ * net 5 VDD * net 6 VSS * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U +M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U * device instance $2 r0 *1 1.775,4.95 PMOS -M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U +M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U * device instance $3 r0 *1 1.025,2 NMOS -M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U +M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U * device instance $4 r0 *1 1.775,2 NMOS -M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U +M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U .ENDS NAND2_WITH_DIODES diff --git a/testdata/lvs/nand2_split_gate_early.cir.2 b/testdata/lvs/nand2_split_gate_early.cir.2 index 6bceb7353..3d5aa4d5f 100644 --- a/testdata/lvs/nand2_split_gate_early.cir.2 +++ b/testdata/lvs/nand2_split_gate_early.cir.2 @@ -13,11 +13,11 @@ * net 5 VDD * net 6 VSS * device instance $1 r0 *1 1.025,4.95 PMOS -M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U +M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U * device instance $2 r0 *1 1.775,4.95 PMOS -M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U +M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U * device instance $3 r0 *1 1.025,0.65 NMOS -M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U +M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U * device instance $4 r0 *1 1.775,0.65 NMOS -M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U +M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U .ENDS NAND2_WITH_DIODES diff --git a/testdata/lvs/nand2_split_gate_early.lvsdb.1 b/testdata/lvs/nand2_split_gate_early.lvsdb.1 index e0d758a88..0ade4db56 100644 --- a/testdata/lvs/nand2_split_gate_early.lvsdb.1 +++ b/testdata/lvs/nand2_split_gate_early.lvsdb.1 @@ -335,9 +335,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 2) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(2 PMOS @@ -348,9 +348,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(3 NMOS @@ -361,9 +361,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 6) terminal(G 2) - terminal(D 6) + terminal(D 4) terminal(B 4) ) device(4 NMOS @@ -374,9 +374,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 6) terminal(B 4) ) diff --git a/testdata/lvs/nand2_split_gate_early.lvsdb.2 b/testdata/lvs/nand2_split_gate_early.lvsdb.2 index 4742977a2..0c99205ab 100644 --- a/testdata/lvs/nand2_split_gate_early.lvsdb.2 +++ b/testdata/lvs/nand2_split_gate_early.lvsdb.2 @@ -335,9 +335,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 2) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(2 PMOS @@ -348,9 +348,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 5) terminal(B 5) ) device(3 NMOS @@ -361,9 +361,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 6) terminal(G 2) - terminal(D 6) + terminal(D 4) terminal(B 4) ) device(4 NMOS @@ -374,9 +374,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 3) terminal(G 1) - terminal(D 3) + terminal(D 6) terminal(B 4) ) diff --git a/testdata/lvs/ringo.cir b/testdata/lvs/ringo.cir index 13d6d09f5..2850f0094 100644 --- a/testdata/lvs/ringo.cir +++ b/testdata/lvs/ringo.cir @@ -16,12 +16,12 @@ X$12 VDD OUT VSS VDD FB VSS INVX1 .SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U -M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U -M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U -M$4 1 B OUT BULK NMOS L=0.25U W=0.95U +M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U +M$3 1 A VSS BULK NMOS L=0.25U W=0.95U +M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U .ENDS ND2X1 .SUBCKT INVX1 VDD OUT VSS NWELL IN BULK -M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U -M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U +M$1 OUT IN VDD NWELL PMOS L=0.25U W=1.5U +M$2 OUT IN VSS BULK NMOS L=0.25U W=0.95U .ENDS INVX1 diff --git a/testdata/lvs/ringo_device_subcircuits.cir b/testdata/lvs/ringo_device_subcircuits.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_device_subcircuits.cir +++ b/testdata/lvs/ringo_device_subcircuits.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_fixed_sources.gds b/testdata/lvs/ringo_fixed_sources.gds new file mode 100644 index 000000000..2c6d93de5 Binary files /dev/null and b/testdata/lvs/ringo_fixed_sources.gds differ diff --git a/testdata/lvs/ringo_layout_var.cir b/testdata/lvs/ringo_layout_var.cir index 93b5336ec..aa3dbd07e 100644 --- a/testdata/lvs/ringo_layout_var.cir +++ b/testdata/lvs/ringo_layout_var.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1B * cell INVX1 @@ -71,9 +71,9 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_layout_var.lvsdb.1 b/testdata/lvs/ringo_layout_var.lvsdb.1 index 7385ada3b..0346c3a17 100644 --- a/testdata/lvs/ringo_layout_var.lvsdb.1 +++ b/testdata/lvs/ringo_layout_var.lvsdb.1 @@ -692,9 +692,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_layout_var.lvsdb.2 b/testdata/lvs/ringo_layout_var.lvsdb.2 index 3264fd8a0..fbe29c86e 100644 --- a/testdata/lvs/ringo_layout_var.lvsdb.2 +++ b/testdata/lvs/ringo_layout_var.lvsdb.2 @@ -692,9 +692,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_mixed_hierarchy.cir b/testdata/lvs/ringo_mixed_hierarchy.cir index e82ebea9b..6a8f50780 100644 --- a/testdata/lvs/ringo_mixed_hierarchy.cir +++ b/testdata/lvs/ringo_mixed_hierarchy.cir @@ -35,13 +35,13 @@ X$15 3 12 16 3 11 16 INVX1 * cell instance $16 r0 *1 18.6,0 X$16 3 13 16 3 12 16 INVX1 * device instance $1 r0 *1 2.65,5.8 PMOS -M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 3 2 4 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 3.35,5.8 PMOS -M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 4 1 3 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 2.65,2.135 NMOS -M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 15 2 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 3.35,2.135 NMOS -M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS RINGO * cell INVX1 @@ -58,7 +58,7 @@ M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 diff --git a/testdata/lvs/ringo_mixed_hierarchy.lvsdb b/testdata/lvs/ringo_mixed_hierarchy.lvsdb index f97da3336..35c7fd126 100644 --- a/testdata/lvs/ringo_mixed_hierarchy.lvsdb +++ b/testdata/lvs/ringo_mixed_hierarchy.lvsdb @@ -616,9 +616,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 4) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple.cir b/testdata/lvs/ringo_simple.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_simple.cir +++ b/testdata/lvs/ringo_simple.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple.lvsdb.1 b/testdata/lvs/ringo_simple.lvsdb.1 index aab318d16..b5a1aabcb 100644 --- a/testdata/lvs/ringo_simple.lvsdb.1 +++ b/testdata/lvs/ringo_simple.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple.lvsdb.2 b/testdata/lvs/ringo_simple.lvsdb.2 index 3a8a977fb..4bfcca0be 100644 --- a/testdata/lvs/ringo_simple.lvsdb.2 +++ b/testdata/lvs/ringo_simple.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_compare2.cir b/testdata/lvs/ringo_simple_compare2.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_simple_compare2.cir +++ b/testdata/lvs/ringo_simple_compare2.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_compare2.lvsdb.1 b/testdata/lvs/ringo_simple_compare2.lvsdb.1 index aab318d16..b5a1aabcb 100644 --- a/testdata/lvs/ringo_simple_compare2.lvsdb.1 +++ b/testdata/lvs/ringo_simple_compare2.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_compare2.lvsdb.2 b/testdata/lvs/ringo_simple_compare2.lvsdb.2 index 3a8a977fb..4bfcca0be 100644 --- a/testdata/lvs/ringo_simple_compare2.lvsdb.2 +++ b/testdata/lvs/ringo_simple_compare2.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_device_scaling.cir b/testdata/lvs/ringo_simple_device_scaling.cir index 44196cb11..ca7679d38 100644 --- a/testdata/lvs/ringo_simple_device_scaling.cir +++ b/testdata/lvs/ringo_simple_device_scaling.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U +M$1 2 5 1 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U +M$2 2 5 3 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U +M$1 1 6 2 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U +M$2 2 5 1 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U +M$3 8 6 3 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U +M$4 2 5 8 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 index 3a6b7972c..6cb29d488 100644 --- a/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 index 36a0dc190..d77d08cb2 100644 --- a/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 +++ b/testdata/lvs/ringo_simple_device_scaling.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_dmos.cir b/testdata/lvs/ringo_simple_dmos.cir index d517e69ba..c7c75b754 100644 --- a/testdata/lvs/ringo_simple_dmos.cir +++ b/testdata/lvs/ringo_simple_dmos.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 7 A * net 8 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 7 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 6 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$3 3 7 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 4 6 2 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.1 b/testdata/lvs/ringo_simple_dmos.lvsdb.1 index 1c92dfcf0..59c0c5194 100644 --- a/testdata/lvs/ringo_simple_dmos.lvsdb.1 +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.1 @@ -609,9 +609,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -851,62 +851,36 @@ xref( ) ) circuit(ND2X1 ND2X1 nomatch + log( + entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.')) + entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0')) + entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.')) + ) xref( - net(4 8 mismatch) - net(5 4 mismatch) + net(5 4 match) + net(4 3 mismatch) net(7 6 match) net(6 5 match) - net(2 2 mismatch) + net(2 2 match) net(8 7 mismatch) - net(1 1 mismatch) - net(3 3 mismatch) + net(1 1 match) + net(3 8 mismatch) + pin(() 2 mismatch) pin(3 3 match) pin(5 5 match) pin(4 4 match) pin(1 1 match) pin(6 6 match) pin(0 0 match) - pin(2 2 match) - device(3 3 mismatch) - device(4 4 match) + pin(2 () mismatch) + device(3 3 match) + device(4 4 mismatch) + device(1 1 match) device(2 2 match) - device(1 1 mismatch) ) ) - circuit(RINGO RINGO match + circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1') xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_dmos.lvsdb.2 b/testdata/lvs/ringo_simple_dmos.lvsdb.2 index 15b294dcf..94072e582 100644 --- a/testdata/lvs/ringo_simple_dmos.lvsdb.2 +++ b/testdata/lvs/ringo_simple_dmos.lvsdb.2 @@ -609,9 +609,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -851,62 +851,36 @@ xref( ) ) circuit(ND2X1 ND2X1 nomatch + log( + entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.')) + entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0')) + entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.')) + ) xref( - net(4 8 mismatch) - net(5 4 mismatch) + net(5 4 match) + net(4 3 mismatch) net(7 6 match) net(6 5 match) - net(2 2 mismatch) + net(2 2 match) net(8 7 mismatch) - net(1 1 mismatch) - net(3 3 mismatch) + net(1 1 match) + net(3 8 mismatch) + pin(() 2 mismatch) pin(3 3 match) pin(5 5 match) pin(4 4 match) pin(1 1 match) pin(6 6 match) pin(0 0 match) - pin(2 2 match) - device(3 3 mismatch) - device(4 4 match) + pin(2 () mismatch) + device(3 3 match) + device(4 4 mismatch) + device(1 1 match) device(2 2 match) - device(1 1 mismatch) ) ) - circuit(RINGO RINGO match + circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1') xref( - net(1 6 match) - net(10 15 match) - net(2 7 match) - net(3 8 match) - net(4 9 match) - net(5 10 match) - net(6 11 match) - net(7 12 match) - net(8 13 match) - net(9 14 match) - net(14 4 match) - net(11 3 match) - net(13 5 match) - net(12 2 match) - net(15 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(4 4 match) - circuit(5 5 match) - circuit(6 6 match) - circuit(7 7 match) - circuit(8 8 match) - circuit(9 9 match) - circuit(10 10 match) - circuit(11 11 match) - circuit(12 12 match) - circuit(1 1 match) ) ) ) diff --git a/testdata/lvs/ringo_simple_dmos_fixed.cir.1 b/testdata/lvs/ringo_simple_dmos_fixed.cir.1 new file mode 100644 index 000000000..48a2ac028 --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos_fixed.cir.1 @@ -0,0 +1,83 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 11 12 13 14 15 +* net 11 FB +* net 12 VDD +* net 13 OUT +* net 14 ENABLE +* net 15 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 12 1 15 12 11 14 15 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 12 2 15 12 1 15 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 12 3 15 12 2 15 INVX1 +* cell instance $4 r0 *1 7.8,0 +X$4 12 4 15 12 3 15 INVX1 +* cell instance $5 r0 *1 9.6,0 +X$5 12 5 15 12 4 15 INVX1 +* cell instance $6 r0 *1 11.4,0 +X$6 12 6 15 12 5 15 INVX1 +* cell instance $7 r0 *1 13.2,0 +X$7 12 7 15 12 6 15 INVX1 +* cell instance $8 r0 *1 15,0 +X$8 12 8 15 12 7 15 INVX1 +* cell instance $9 r0 *1 16.8,0 +X$9 12 9 15 12 8 15 INVX1 +* cell instance $10 r0 *1 18.6,0 +X$10 12 10 15 12 9 15 INVX1 +* cell instance $11 r0 *1 20.4,0 +X$11 12 11 15 12 10 15 INVX1 +* cell instance $12 r0 *1 22.2,0 +X$12 12 13 15 12 11 15 INVX1 +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 5 6 7 8 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 6 B +* net 7 A +* net 8 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 0.85,2.135 NMOS +M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U +* device instance $4 r0 *1 1.55,2.135 NMOS +M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dmos_fixed.cir.2 b/testdata/lvs/ringo_simple_dmos_fixed.cir.2 new file mode 100644 index 000000000..7247bf435 --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos_fixed.cir.2 @@ -0,0 +1,83 @@ +* Extracted by KLayout + +* cell RINGO +* pin FB +* pin VDD +* pin OUT +* pin ENABLE +* pin VSS +.SUBCKT RINGO 11 12 13 14 15 +* net 11 FB +* net 12 VDD +* net 13 OUT +* net 14 ENABLE +* net 15 VSS +* cell instance $1 r0 *1 1.8,0 +X$1 12 1 15 12 11 14 15 ND2X1 +* cell instance $2 r0 *1 4.2,0 +X$2 12 2 15 12 1 15 INVX1 +* cell instance $3 r0 *1 6,0 +X$3 12 3 15 12 2 15 INVX1 +* cell instance $4 r0 *1 7.8,0 +X$4 12 4 15 12 3 15 INVX1 +* cell instance $5 r0 *1 9.6,0 +X$5 12 5 15 12 4 15 INVX1 +* cell instance $6 r0 *1 11.4,0 +X$6 12 6 15 12 5 15 INVX1 +* cell instance $7 r0 *1 13.2,0 +X$7 12 7 15 12 6 15 INVX1 +* cell instance $8 r0 *1 15,0 +X$8 12 8 15 12 7 15 INVX1 +* cell instance $9 r0 *1 16.8,0 +X$9 12 9 15 12 8 15 INVX1 +* cell instance $10 r0 *1 18.6,0 +X$10 12 10 15 12 9 15 INVX1 +* cell instance $11 r0 *1 20.4,0 +X$11 12 11 15 12 10 15 INVX1 +* cell instance $12 r0 *1 22.2,0 +X$12 12 13 15 12 11 15 INVX1 +.ENDS RINGO + +* cell INVX1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin IN +* pin SUBSTRATE +.SUBCKT INVX1 1 2 3 4 5 6 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 5 IN +* net 6 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +* device instance $2 r0 *1 0.85,2.135 NMOS +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +.ENDS INVX1 + +* cell ND2X1 +* pin VDD +* pin OUT +* pin VSS +* pin +* pin B +* pin A +* pin SUBSTRATE +.SUBCKT ND2X1 1 2 3 5 6 7 8 +* net 1 VDD +* net 2 OUT +* net 3 VSS +* net 6 B +* net 7 A +* net 8 SUBSTRATE +* device instance $1 r0 *1 0.85,5.8 PMOS +M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $2 r0 *1 1.55,5.8 PMOS +M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +* device instance $3 r0 *1 1.55,2.135 NMOS +M$3 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U +* device instance $4 r0 *1 0.85,2.135 NMOS +M$4 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U +.ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dmos_fixed.lvs b/testdata/lvs/ringo_simple_dmos_fixed.lvs new file mode 100644 index 000000000..5f375e95f --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos_fixed.lvs @@ -0,0 +1,83 @@ + +source($lvs_test_source, "RINGO") + +report_lvs($lvs_test_target_lvsdb, true) + +target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout") + +schematic("ringo.cir") + +deep + +# Drawing layers + +nwell = input(1, 0) +active = input(2, 0) +pplus = input(3, 0) +nplus = input(4, 0) +poly = input(5, 0) +contact = input(8, 0) +metal1 = input(9, 0) +via1 = input(10, 0) +metal2 = input(11, 0) +source = input(14, 0) + +# Bulk layer for terminal provisioning + +bulk = polygon_layer + +# Computed layers + +active_in_nwell = active & nwell +pactive = active_in_nwell & pplus +pgate = pactive & poly +psd = pactive - pgate +ps = psd & source +pd = psd - source +ntie = active_in_nwell & nplus + +active_outside_nwell = active - nwell +nactive = active_outside_nwell & nplus +ngate = nactive & poly +nsd = nactive - ngate +ns = nsd & source +nd = nsd - source +ptie = active_outside_nwell & pplus + +# Device extraction + +# PMOS transistor device extraction +extract_devices(dmos4("PMOS"), { "S" => ps, "D" => pd, "G" => pgate, "W" => nwell, + "tS" => ps, "tD" => pd, "tG" => poly, "tW" => nwell }) + +# NMOS transistor device extraction +extract_devices(dmos4("NMOS"), { "S" => ns, "D" => nd, "G" => ngate, "W" => bulk, + "tS" => ns, "tD" => nd, "tG" => poly, "tW" => bulk }) + +# Define connectivity for netlist extraction + +# Inter-layer +connect(ps, pd) +connect(ns, nd) +connect(ps, contact) +connect(pd, contact) +connect(ns, contact) +connect(nd, contact) +connect(poly, contact) +connect(ntie, contact) +connect(nwell, ntie) +connect(ptie, contact) +connect(contact, metal1) +connect(metal1, via1) +connect(via1, metal2) + +# Global +connect_global(bulk, "SUBSTRATE") +connect_global(ptie, "SUBSTRATE") + +# Compare section + +netlist.simplify + +compare + diff --git a/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.1 b/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.1 new file mode 100644 index 000000000..f5a1b048e --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.1 @@ -0,0 +1,918 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l4 '1/0') + layer(l5 '5/0') + layer(l10 '8/0') + layer(l13 '9/0') + layer(l14 '10/0') + layer(l15 '11/0') + layer(l9) + layer(l3) + layer(l1) + layer(l11) + layer(l8) + layer(l6) + layer(l12) + + # Mask layer connectivity + connect(l4 l4 l11) + connect(l5 l5 l10) + connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) + connect(l13 l10 l13 l14) + connect(l14 l13 l14 l15) + connect(l15 l14 l15) + connect(l9 l9) + connect(l3 l10 l3 l1) + connect(l1 l10 l3 l1) + connect(l11 l4 l10 l11) + connect(l8 l10 l8 l6) + connect(l6 l10 l8 l6) + connect(l12 l10 l12) + + # Global nets and connectivity + global(l9 SUBSTRATE) + global(l12 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l3 (125 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (-550 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l3 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l3 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (233 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l8 (-342 -475) (217 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -790) (300 1700)) + rect(l13 (-1350 0) (2400 800)) + rect(l13 (-1150 -400) (0 0)) + rect(l3 (-275 -2150) (425 1500)) + rect(l3 (-400 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1810 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-1580 3760) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (1220 920) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l13 (-110 1390) (300 1400)) + polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l13 (-140 -500) (0 0)) + rect(l13 (-1750 1100) (300 1400)) + rect(l13 (1100 -1700) (300 300)) + rect(l13 (-300 0) (300 1400)) + rect(l1 (-1750 -1450) (425 1500)) + rect(l1 (950 -1500) (425 1500)) + rect(l6 (-192 -4890) (192 950)) + rect(l6 (-425 -950) (233 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (2400 800)) + rect(l13 (-1150 -400) (0 0)) + rect(l8 (-950 860) (208 950)) + rect(l8 (0 -950) (217 950)) + ) + net(4 + rect(l8 (1208 1660) (192 950)) + rect(l8 (-192 -950) (217 950)) + rect(l6 (-425 -950) (208 950)) + rect(l6 (-233 -950) (233 950)) + ) + net(5 + rect(l4 (-100 4500) (2600 3500)) + ) + net(6 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-285 1050) (180 180)) + rect(l13 (-70 -90) (0 0)) + rect(l13 (-170 -150) (300 300)) + ) + net(7 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-265 150) (180 180)) + rect(l13 (-90 -90) (0 0)) + rect(l13 (-150 -150) (300 300)) + ) + net(8 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(5) + pin(6 name(B)) + pin(7 name(A)) + pin(8 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 7) + terminal(D 2) + terminal(B 5) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 5) + ) + device(3 D$NMOS + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.22135) + param(PS 2.75) + param(PD 2.366) + terminal(S 3) + terminal(G 7) + terminal(D 4) + terminal(B 8) + ) + device(4 D$NMOS$1 + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.20615) + param(AD 0.40375) + param(PS 2.334) + param(PD 2.75) + terminal(S 4) + terminal(G 6) + terminal(D 2) + terminal(B 8) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (410 6260) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -240) (300 1400)) + rect(l13 (-650 300) (1800 800)) + rect(l13 (-1450 -1100) (300 300)) + rect(l13 (300 400) (0 0)) + rect(l3 (-650 -2150) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -4120) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -790) (300 4790)) + rect(l13 (-150 -2500) (0 0)) + rect(l1 (-225 1050) (425 1500)) + rect(l6 (-192 -4890) (192 950)) + rect(l6 (-425 -950) (233 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (1800 800)) + rect(l13 (-850 -400) (0 0)) + rect(l8 (-650 860) (208 950)) + rect(l8 (0 -950) (217 950)) + ) + net(4 + rect(l4 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-465 150) (180 180)) + rect(l13 (-90 -90) (0 0)) + rect(l13 (-150 -150) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l13 (4040 2950) (610 300)) + ) + net(2 + rect(l13 (5550 2950) (900 300)) + ) + net(3 + rect(l13 (7350 2950) (900 300)) + ) + net(4 + rect(l13 (9150 2950) (900 300)) + ) + net(5 + rect(l13 (10950 2950) (900 300)) + ) + net(6 + rect(l13 (12750 2950) (900 300)) + ) + net(7 + rect(l13 (14550 2950) (900 300)) + ) + net(8 + rect(l13 (16350 2950) (900 300)) + ) + net(9 + rect(l13 (18150 2950) (900 300)) + ) + net(10 + rect(l13 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l13 (21750 2950) (900 300)) + rect(l13 (-19530 590) (320 320)) + rect(l13 (17820 -320) (320 320)) + rect(l14 (-18400 -260) (200 200)) + rect(l14 (17940 -200) (200 200)) + rect(l15 (-18040 -300) (17740 400)) + rect(l15 (-17920 -200) (0 0)) + rect(l15 (-220 -200) (400 400)) + rect(l15 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l4 (500 4500) (1400 3500)) + rect(l4 (-1900 -3500) (600 3500)) + rect(l4 (23300 -3500) (1400 3500)) + rect(l4 (-100 -3500) (600 3500)) + rect(l10 (-24690 -1240) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l13 (-21740 860) (0 0)) + rect(l13 (-2350 -450) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-100 -350) (0 0)) + rect(l13 (-1250 -400) (600 800)) + rect(l13 (23400 -800) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-100 -350) (0 0)) + rect(l13 (550 -400) (600 800)) + rect(l11 (-24850 -1500) (500 1500)) + rect(l11 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l13 (23440 3840) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-100 -100) (0 0)) + rect(l15 (-200 -200) (400 400)) + ) + net(14 name(ENABLE) + rect(l13 (2440 2940) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-100 -100) (0 0)) + rect(l15 (-200 -200) (400 400)) + ) + net(15 name(VSS) + rect(l10 (1110 1610) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-21740 -390) (0 0)) + rect(l13 (-1900 -400) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-550 -400) (0 0)) + rect(l13 (-1250 -400) (600 800)) + rect(l13 (23850 -750) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-550 -400) (0 0)) + rect(l13 (550 -400) (600 800)) + rect(l12 (-24850 -800) (500 1500)) + rect(l12 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(4 8 match) + net(5 4 match) + net(7 6 match) + net(6 5 match) + net(2 2 match) + net(8 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(3 3 match) + device(4 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.2 b/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.2 new file mode 100644 index 000000000..65550776c --- /dev/null +++ b/testdata/lvs/ringo_simple_dmos_fixed.lvsdb.2 @@ -0,0 +1,918 @@ +#%lvsdb-klayout + +# Layout +layout( + top(RINGO) + unit(0.001) + + # Layer section + # This section lists the mask layers (drawing or derived) and their connections. + + # Mask layers + layer(l4 '1/0') + layer(l5 '5/0') + layer(l10 '8/0') + layer(l13 '9/0') + layer(l14 '10/0') + layer(l15 '11/0') + layer(l9) + layer(l3) + layer(l1) + layer(l11) + layer(l8) + layer(l6) + layer(l12) + + # Mask layer connectivity + connect(l4 l4 l11) + connect(l5 l5 l10) + connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12) + connect(l13 l10 l13 l14) + connect(l14 l13 l14 l15) + connect(l15 l14 l15) + connect(l9 l9) + connect(l3 l10 l3 l1) + connect(l1 l10 l3 l1) + connect(l11 l4 l10 l11) + connect(l8 l10 l8 l6) + connect(l6 l10 l8 l6) + connect(l12 l10 l12) + + # Global nets and connectivity + global(l9 SUBSTRATE) + global(l12 SUBSTRATE) + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Device abstracts section + # Device abstracts list the pin shapes of the devices. + device(D$PMOS PMOS + terminal(S + rect(l3 (125 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (-550 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$1 PMOS + terminal(S + rect(l3 (-575 -750) (450 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$PMOS$2 PMOS + terminal(S + rect(l3 (-550 -750) (425 1500)) + ) + terminal(G + rect(l5 (-125 -750) (250 1500)) + ) + terminal(D + rect(l1 (125 -750) (425 1500)) + ) + terminal(B + rect(l4 (-125 -750) (250 1500)) + ) + ) + device(D$NMOS NMOS + terminal(S + rect(l8 (-342 -475) (217 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$1 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (233 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + device(D$NMOS$2 NMOS + terminal(S + rect(l8 (-550 -475) (425 950)) + ) + terminal(G + rect(l5 (-125 -475) (250 950)) + ) + terminal(D + rect(l6 (125 -475) (425 950)) + ) + terminal(B + rect(l9 (-125 -475) (250 950)) + ) + ) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Circuit boundary + rect((-100 400) (2600 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -790) (300 1700)) + rect(l13 (-1350 0) (2400 800)) + rect(l13 (-1150 -400) (0 0)) + rect(l3 (-250 -2150) (425 1500)) + rect(l3 (-450 -1500) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1810 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-1580 3760) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (1220 920) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) + rect(l13 (-110 1390) (300 1400)) + polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) + rect(l13 (-140 -500) (0 0)) + rect(l13 (-1750 1100) (300 1400)) + rect(l13 (1100 -1700) (300 300)) + rect(l13 (-300 0) (300 1400)) + rect(l1 (-1750 -1450) (425 1500)) + rect(l1 (950 -1500) (425 1500)) + rect(l6 (-192 -4890) (192 950)) + rect(l6 (-425 -950) (233 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (2400 800)) + rect(l13 (-1150 -400) (0 0)) + rect(l8 (-950 860) (208 950)) + rect(l8 (0 -950) (217 950)) + ) + net(4 + rect(l8 (1208 1660) (192 950)) + rect(l8 (-192 -950) (217 950)) + rect(l6 (-425 -950) (208 950)) + rect(l6 (-233 -950) (233 950)) + ) + net(5 + rect(l4 (-100 4500) (2600 3500)) + ) + net(6 name(B) + rect(l5 (1425 2860) (250 1940)) + rect(l5 (-345 -950) (300 300)) + rect(l5 (-205 650) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-285 1050) (180 180)) + rect(l13 (-70 -90) (0 0)) + rect(l13 (-170 -150) (300 300)) + ) + net(7 name(A) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-325 -1850) (300 300)) + rect(l5 (-225 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-265 150) (180 180)) + rect(l13 (-90 -90) (0 0)) + rect(l13 (-150 -150) (300 300)) + ) + net(8 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(5) + pin(6 name(B)) + pin(7 name(A)) + pin(8 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 7) + terminal(D 2) + terminal(B 5) + ) + device(2 D$PMOS$1 + location(1550 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.3375) + param(AD 0.6375) + param(PS 1.95) + param(PD 3.85) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 5) + ) + device(3 D$NMOS + location(1550 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.20615) + param(AD 0.40375) + param(PS 2.334) + param(PD 2.75) + terminal(S 4) + terminal(G 6) + terminal(D 2) + terminal(B 8) + ) + device(4 D$NMOS$1 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.22135) + param(PS 2.75) + param(PD 2.366) + terminal(S 3) + terminal(G 7) + terminal(D 4) + terminal(B 8) + ) + + ) + circuit(INVX1 + + # Circuit boundary + rect((-100 400) (2000 7600)) + + # Nets with their geometries + net(1 name(VDD) + rect(l10 (410 6260) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l13 (-240 -240) (300 1400)) + rect(l13 (-650 300) (1800 800)) + rect(l13 (-1450 -1100) (300 300)) + rect(l13 (300 400) (0 0)) + rect(l3 (-650 -2150) (425 1500)) + ) + net(2 name(OUT) + rect(l10 (1110 5160) (180 180)) + rect(l10 (-180 920) (180 180)) + rect(l10 (-180 -730) (180 180)) + rect(l10 (-180 -4120) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -790) (300 4790)) + rect(l13 (-150 -2500) (0 0)) + rect(l1 (-225 1050) (425 1500)) + rect(l6 (-192 -4890) (192 950)) + rect(l6 (-425 -950) (233 950)) + ) + net(3 name(VSS) + rect(l10 (410 1770) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-240 -1300) (300 1360)) + rect(l13 (-650 -2160) (1800 800)) + rect(l13 (-850 -400) (0 0)) + rect(l8 (-650 860) (208 950)) + rect(l8 (0 -950) (217 950)) + ) + net(4 + rect(l4 (-100 4500) (2000 3500)) + ) + net(5 name(IN) + rect(l5 (725 2860) (250 1940)) + rect(l5 (-525 -1850) (300 300)) + rect(l5 (-25 1550) (250 2000)) + rect(l5 (-250 -2000) (250 2000)) + rect(l5 (-250 -5390) (250 1450)) + rect(l10 (-465 150) (180 180)) + rect(l13 (-90 -90) (0 0)) + rect(l13 (-150 -150) (300 300)) + ) + net(6 name(SUBSTRATE)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4) + pin(5 name(IN)) + pin(6 name(SUBSTRATE)) + + # Devices and their connections + device(1 D$PMOS$2 + location(850 5800) + param(L 0.25) + param(W 1.5) + param(AS 0.6375) + param(AD 0.6375) + param(PS 3.85) + param(PD 3.85) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 D$NMOS$2 + location(850 2135) + param(L 0.25) + param(W 0.95) + param(AS 0.40375) + param(AD 0.40375) + param(PS 2.75) + param(PD 2.75) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Circuit boundary + rect((0 350) (25800 7650)) + + # Nets with their geometries + net(1 + rect(l13 (4040 2950) (610 300)) + ) + net(2 + rect(l13 (5550 2950) (900 300)) + ) + net(3 + rect(l13 (7350 2950) (900 300)) + ) + net(4 + rect(l13 (9150 2950) (900 300)) + ) + net(5 + rect(l13 (10950 2950) (900 300)) + ) + net(6 + rect(l13 (12750 2950) (900 300)) + ) + net(7 + rect(l13 (14550 2950) (900 300)) + ) + net(8 + rect(l13 (16350 2950) (900 300)) + ) + net(9 + rect(l13 (18150 2950) (900 300)) + ) + net(10 + rect(l13 (19950 2950) (900 300)) + ) + net(11 name(FB) + rect(l13 (21750 2950) (900 300)) + rect(l13 (-19530 590) (320 320)) + rect(l13 (17820 -320) (320 320)) + rect(l14 (-18400 -260) (200 200)) + rect(l14 (17940 -200) (200 200)) + rect(l15 (-18040 -300) (17740 400)) + rect(l15 (-17920 -200) (0 0)) + rect(l15 (-220 -200) (400 400)) + rect(l15 (17740 -400) (400 400)) + ) + net(12 name(VDD) + rect(l4 (500 4500) (1400 3500)) + rect(l4 (-1900 -3500) (600 3500)) + rect(l4 (23300 -3500) (1400 3500)) + rect(l4 (-100 -3500) (600 3500)) + rect(l10 (-24690 -1240) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l13 (-21740 860) (0 0)) + rect(l13 (-2350 -450) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-100 -350) (0 0)) + rect(l13 (-1250 -400) (600 800)) + rect(l13 (23400 -800) (1200 800)) + rect(l13 (-750 -1450) (300 1400)) + rect(l13 (-100 -350) (0 0)) + rect(l13 (550 -400) (600 800)) + rect(l11 (-24850 -1500) (500 1500)) + rect(l11 (22900 -1500) (500 1500)) + ) + net(13 name(OUT) + rect(l13 (23440 3840) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-100 -100) (0 0)) + rect(l15 (-200 -200) (400 400)) + ) + net(14 name(ENABLE) + rect(l13 (2440 2940) (320 320)) + rect(l14 (-260 -260) (200 200)) + rect(l15 (-100 -100) (0 0)) + rect(l15 (-200 -200) (400 400)) + ) + net(15 name(VSS) + rect(l10 (1110 1610) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l10 (23220 370) (180 180)) + rect(l10 (-180 -1280) (180 180)) + rect(l10 (-180 370) (180 180)) + rect(l13 (-21740 -390) (0 0)) + rect(l13 (-1900 -400) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-550 -400) (0 0)) + rect(l13 (-1250 -400) (600 800)) + rect(l13 (23850 -750) (300 1400)) + rect(l13 (-750 -1450) (1200 800)) + rect(l13 (-550 -400) (0 0)) + rect(l13 (550 -400) (600 800)) + rect(l12 (-24850 -800) (500 1500)) + rect(l12 (22900 -1500) (500 1500)) + ) + + # Outgoing pins and their connections to nets + pin(11 name(FB)) + pin(12 name(VDD)) + pin(13 name(OUT)) + pin(14 name(ENABLE)) + pin(15 name(VSS)) + + # Subcircuits and their connections + circuit(1 ND2X1 location(1800 0) + pin(0 12) + pin(1 1) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 14) + pin(6 15) + ) + circuit(2 INVX1 location(4200 0) + pin(0 12) + pin(1 2) + pin(2 15) + pin(3 12) + pin(4 1) + pin(5 15) + ) + circuit(3 INVX1 location(6000 0) + pin(0 12) + pin(1 3) + pin(2 15) + pin(3 12) + pin(4 2) + pin(5 15) + ) + circuit(4 INVX1 location(7800 0) + pin(0 12) + pin(1 4) + pin(2 15) + pin(3 12) + pin(4 3) + pin(5 15) + ) + circuit(5 INVX1 location(9600 0) + pin(0 12) + pin(1 5) + pin(2 15) + pin(3 12) + pin(4 4) + pin(5 15) + ) + circuit(6 INVX1 location(11400 0) + pin(0 12) + pin(1 6) + pin(2 15) + pin(3 12) + pin(4 5) + pin(5 15) + ) + circuit(7 INVX1 location(13200 0) + pin(0 12) + pin(1 7) + pin(2 15) + pin(3 12) + pin(4 6) + pin(5 15) + ) + circuit(8 INVX1 location(15000 0) + pin(0 12) + pin(1 8) + pin(2 15) + pin(3 12) + pin(4 7) + pin(5 15) + ) + circuit(9 INVX1 location(16800 0) + pin(0 12) + pin(1 9) + pin(2 15) + pin(3 12) + pin(4 8) + pin(5 15) + ) + circuit(10 INVX1 location(18600 0) + pin(0 12) + pin(1 10) + pin(2 15) + pin(3 12) + pin(4 9) + pin(5 15) + ) + circuit(11 INVX1 location(20400 0) + pin(0 12) + pin(1 11) + pin(2 15) + pin(3 12) + pin(4 10) + pin(5 15) + ) + circuit(12 INVX1 location(22200 0) + pin(0 12) + pin(1 13) + pin(2 15) + pin(3 12) + pin(4 11) + pin(5 15) + ) + + ) +) + +# Reference netlist +reference( + + # Device class section + class(PMOS MOS4) + class(NMOS MOS4) + + # Circuit section + # Circuits are the hierarchical building blocks of the netlist. + circuit(ND2X1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(B)) + net(6 name(A)) + net(7 name(BULK)) + net(8 name('1')) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(B)) + pin(6 name(A)) + pin(7 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 6) + terminal(D 2) + terminal(B 4) + ) + device(2 PMOS + name($2) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(3 NMOS + name($3) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 6) + terminal(D 8) + terminal(B 7) + ) + device(4 NMOS + name($4) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 8) + terminal(G 5) + terminal(D 2) + terminal(B 7) + ) + + ) + circuit(INVX1 + + # Nets + net(1 name(VDD)) + net(2 name(OUT)) + net(3 name(VSS)) + net(4 name(NWELL)) + net(5 name(IN)) + net(6 name(BULK)) + + # Outgoing pins and their connections to nets + pin(1 name(VDD)) + pin(2 name(OUT)) + pin(3 name(VSS)) + pin(4 name(NWELL)) + pin(5 name(IN)) + pin(6 name(BULK)) + + # Devices and their connections + device(1 PMOS + name($1) + param(L 0.25) + param(W 1.5) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 1) + terminal(G 5) + terminal(D 2) + terminal(B 4) + ) + device(2 NMOS + name($2) + param(L 0.25) + param(W 0.95) + param(AS 0) + param(AD 0) + param(PS 0) + param(PD 0) + terminal(S 3) + terminal(G 5) + terminal(D 2) + terminal(B 6) + ) + + ) + circuit(RINGO + + # Nets + net(1 name(VSS)) + net(2 name(VDD)) + net(3 name(FB)) + net(4 name(ENABLE)) + net(5 name(OUT)) + net(6 name('1')) + net(7 name('2')) + net(8 name('3')) + net(9 name('4')) + net(10 name('5')) + net(11 name('6')) + net(12 name('7')) + net(13 name('8')) + net(14 name('9')) + net(15 name('10')) + + # Outgoing pins and their connections to nets + pin(1 name(VSS)) + pin(2 name(VDD)) + pin(3 name(FB)) + pin(4 name(ENABLE)) + pin(5 name(OUT)) + + # Subcircuits and their connections + circuit(1 ND2X1 name($1) + pin(0 2) + pin(1 6) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 4) + pin(6 1) + ) + circuit(2 INVX1 name($2) + pin(0 2) + pin(1 7) + pin(2 1) + pin(3 2) + pin(4 6) + pin(5 1) + ) + circuit(3 INVX1 name($3) + pin(0 2) + pin(1 8) + pin(2 1) + pin(3 2) + pin(4 7) + pin(5 1) + ) + circuit(4 INVX1 name($4) + pin(0 2) + pin(1 9) + pin(2 1) + pin(3 2) + pin(4 8) + pin(5 1) + ) + circuit(5 INVX1 name($5) + pin(0 2) + pin(1 10) + pin(2 1) + pin(3 2) + pin(4 9) + pin(5 1) + ) + circuit(6 INVX1 name($6) + pin(0 2) + pin(1 11) + pin(2 1) + pin(3 2) + pin(4 10) + pin(5 1) + ) + circuit(7 INVX1 name($7) + pin(0 2) + pin(1 12) + pin(2 1) + pin(3 2) + pin(4 11) + pin(5 1) + ) + circuit(8 INVX1 name($8) + pin(0 2) + pin(1 13) + pin(2 1) + pin(3 2) + pin(4 12) + pin(5 1) + ) + circuit(9 INVX1 name($9) + pin(0 2) + pin(1 14) + pin(2 1) + pin(3 2) + pin(4 13) + pin(5 1) + ) + circuit(10 INVX1 name($10) + pin(0 2) + pin(1 15) + pin(2 1) + pin(3 2) + pin(4 14) + pin(5 1) + ) + circuit(11 INVX1 name($11) + pin(0 2) + pin(1 3) + pin(2 1) + pin(3 2) + pin(4 15) + pin(5 1) + ) + circuit(12 INVX1 name($12) + pin(0 2) + pin(1 5) + pin(2 1) + pin(3 2) + pin(4 3) + pin(5 1) + ) + + ) +) + +# Cross reference +xref( + circuit(INVX1 INVX1 match + xref( + net(4 4 match) + net(5 5 match) + net(2 2 match) + net(6 6 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(4 4 match) + pin(1 1 match) + pin(5 5 match) + pin(0 0 match) + pin(2 2 match) + device(2 2 match) + device(1 1 match) + ) + ) + circuit(ND2X1 ND2X1 match + xref( + net(4 8 match) + net(5 4 match) + net(7 6 match) + net(6 5 match) + net(2 2 match) + net(8 7 match) + net(1 1 match) + net(3 3 match) + pin(3 3 match) + pin(5 5 match) + pin(4 4 match) + pin(1 1 match) + pin(6 6 match) + pin(0 0 match) + pin(2 2 match) + device(4 3 match) + device(3 4 match) + device(1 1 match) + device(2 2 match) + ) + ) + circuit(RINGO RINGO match + xref( + net(1 6 match) + net(10 15 match) + net(2 7 match) + net(3 8 match) + net(4 9 match) + net(5 10 match) + net(6 11 match) + net(7 12 match) + net(8 13 match) + net(9 14 match) + net(14 4 match) + net(11 3 match) + net(13 5 match) + net(12 2 match) + net(15 1 match) + pin(3 3 match) + pin(0 2 match) + pin(2 4 match) + pin(1 1 match) + pin(4 0 match) + circuit(2 2 match) + circuit(3 3 match) + circuit(4 4 match) + circuit(5 5 match) + circuit(6 6 match) + circuit(7 7 match) + circuit(8 8 match) + circuit(9 9 match) + circuit(10 10 match) + circuit(11 11 match) + circuit(12 12 match) + circuit(1 1 match) + ) + ) +) diff --git a/testdata/lvs/ringo_simple_dummy_device.cir b/testdata/lvs/ringo_simple_dummy_device.cir index 9b5fe15e2..9bf76086a 100644 --- a/testdata/lvs/ringo_simple_dummy_device.cir +++ b/testdata/lvs/ringo_simple_dummy_device.cir @@ -54,9 +54,9 @@ M$1 16 1 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -75,11 +75,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 index 7c990189a..0bb5af8f8 100644 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.1 @@ -609,8 +609,8 @@ layout( reference( # Device class section - class(NMOS MOS4) class(PMOS MOS4) + class(NMOS MOS4) # Circuit section # Circuits are the hierarchical building blocks of the netlist. @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -657,9 +657,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -670,9 +670,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -683,9 +683,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -730,9 +730,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 index bc6aa1a53..a6f463150 100644 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 +++ b/testdata/lvs/ringo_simple_dummy_device.lvsdb.2 @@ -609,8 +609,8 @@ layout( reference( # Device class section - class(NMOS MOS4) class(PMOS MOS4) + class(NMOS MOS4) # Circuit section # Circuits are the hierarchical building blocks of the netlist. @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -657,9 +657,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -670,9 +670,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -683,9 +683,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -730,9 +730,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 b/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 deleted file mode 100644 index 84267cce5..000000000 --- a/testdata/lvs/ringo_simple_dummy_device.lvsdb.3 +++ /dev/null @@ -1,965 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l2 (-275 -2150) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-140 -500) (0 0)) - rect(l11 (-1750 1100) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l6 (-950 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-70 -90) (0 0)) - rect(l11 (-170 -150) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS$1 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$2 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (300 400) (0 0)) - rect(l2 (-650 -2150) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-150 -2500) (0 0)) - rect(l2 (-225 1050) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-850 -400) (0 0)) - rect(l6 (-650 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((0 350) (27600 7650)) - - # Nets with their geometries - net(1 - rect(l4 (26050 2800) (525 550)) - rect(l4 (-525 -300) (300 300)) - rect(l4 (-25 -2000) (250 1450)) - rect(l8 (-465 310) (180 180)) - rect(l11 (-240 -240) (300 300)) - ) - net(2 - rect(l11 (4040 2950) (610 300)) - ) - net(3 - rect(l11 (5550 2950) (900 300)) - ) - net(4 - rect(l11 (7350 2950) (900 300)) - ) - net(5 - rect(l11 (9150 2950) (900 300)) - ) - net(6 - rect(l11 (10950 2950) (900 300)) - ) - net(7 - rect(l11 (12750 2950) (900 300)) - ) - net(8 - rect(l11 (14550 2950) (900 300)) - ) - net(9 - rect(l11 (16350 2950) (900 300)) - ) - net(10 - rect(l11 (18150 2950) (900 300)) - ) - net(11 - rect(l11 (19950 2950) (900 300)) - ) - net(12 name(FB) - rect(l11 (21750 2950) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17920 -200) (0 0)) - rect(l13 (-220 -200) (400 400)) - rect(l13 (17740 -400) (400 400)) - ) - net(13 name(VDD) - rect(l3 (500 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l3 (0 -3500) (600 3500)) - rect(l8 (-26490 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-21740 860) (0 0)) - rect(l11 (-2350 -450) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l9 (-26650 -1500) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(14 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(15 name(ENABLE) - rect(l11 (2440 2940) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(16 name(VSS) - rect(l8 (26010 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (520 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-25780 -890) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (1260 -40) (300 1360)) - rect(l11 (400 -1360) (300 1360)) - rect(l11 (-24000 -1710) (0 0)) - rect(l11 (-1900 -400) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l11 (0 -800) (600 800)) - rect(l6 (-1025 400) (425 950)) - rect(l6 (-1100 -950) (425 950)) - rect(l10 (-25375 -2150) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - - # Outgoing pins and their connections to nets - pin(12 name(FB)) - pin(13 name(VDD)) - pin(14 name(OUT)) - pin(15 name(ENABLE)) - pin(16 name(VSS)) - - # Devices and their connections - device(1 D$NMOS - location(26450 2075) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 16) - terminal(G 1) - terminal(D 16) - terminal(B 16) - ) - - # Subcircuits and their connections - circuit(3 ND2X1 location(1800 0) - pin(0 13) - pin(1 2) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 15) - pin(6 16) - ) - circuit(4 INVX1 location(4200 0) - pin(0 13) - pin(1 3) - pin(2 16) - pin(3 13) - pin(4 2) - pin(5 16) - ) - circuit(5 INVX1 location(6000 0) - pin(0 13) - pin(1 4) - pin(2 16) - pin(3 13) - pin(4 3) - pin(5 16) - ) - circuit(6 INVX1 location(7800 0) - pin(0 13) - pin(1 5) - pin(2 16) - pin(3 13) - pin(4 4) - pin(5 16) - ) - circuit(7 INVX1 location(9600 0) - pin(0 13) - pin(1 6) - pin(2 16) - pin(3 13) - pin(4 5) - pin(5 16) - ) - circuit(8 INVX1 location(11400 0) - pin(0 13) - pin(1 7) - pin(2 16) - pin(3 13) - pin(4 6) - pin(5 16) - ) - circuit(9 INVX1 location(13200 0) - pin(0 13) - pin(1 8) - pin(2 16) - pin(3 13) - pin(4 7) - pin(5 16) - ) - circuit(10 INVX1 location(15000 0) - pin(0 13) - pin(1 9) - pin(2 16) - pin(3 13) - pin(4 8) - pin(5 16) - ) - circuit(11 INVX1 location(16800 0) - pin(0 13) - pin(1 10) - pin(2 16) - pin(3 13) - pin(4 9) - pin(5 16) - ) - circuit(12 INVX1 location(18600 0) - pin(0 13) - pin(1 11) - pin(2 16) - pin(3 13) - pin(4 10) - pin(5 16) - ) - circuit(13 INVX1 location(20400 0) - pin(0 13) - pin(1 12) - pin(2 16) - pin(3 13) - pin(4 11) - pin(5 16) - ) - circuit(14 INVX1 location(22200 0) - pin(0 13) - pin(1 14) - pin(2 16) - pin(3 13) - pin(4 12) - pin(5 16) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(NMOS MOS4) - class(PMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - net(16 name(DUMMY)) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Devices and their connections - device(1 NMOS - name($1) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 16) - terminal(D 1) - terminal(B 1) - ) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX1 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(2 6 match) - net(11 15 match) - net(3 7 match) - net(4 8 match) - net(5 9 match) - net(6 10 match) - net(7 11 match) - net(8 12 match) - net(9 13 match) - net(10 14 match) - net(1 16 match) - net(15 4 match) - net(12 3 match) - net(14 5 match) - net(13 2 match) - net(16 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - device(1 1 match) - circuit(4 2 match) - circuit(5 3 match) - circuit(6 4 match) - circuit(7 5 match) - circuit(8 6 match) - circuit(9 7 match) - circuit(10 8 match) - circuit(11 9 match) - circuit(12 10 match) - circuit(13 11 match) - circuit(14 12 match) - circuit(3 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_implicit_connections.cir b/testdata/lvs/ringo_simple_implicit_connections.cir index 767bb737c..4e8b7a5a3 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.cir +++ b/testdata/lvs/ringo_simple_implicit_connections.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 index d3d97f200..179fe4455 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 @@ -624,9 +624,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 index 959964f06..6ae8d34f4 100644 --- a/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 +++ b/testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 @@ -624,9 +624,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_io.cir.1 b/testdata/lvs/ringo_simple_io.cir.1 index 579c421ec..4d7ccf791 100644 --- a/testdata/lvs/ringo_simple_io.cir.1 +++ b/testdata/lvs/ringo_simple_io.cir.1 @@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1 .ENDS RINGO .SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE -M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U -M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U +M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U + PD=2.75U .ENDS INVX1 .SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE -M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U -M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U -M$3 VSS A \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U +M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 \$I3 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U + PD=1.4U -M$4 \$I3 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U +M$4 OUT B \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U + PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_io.cir.2 b/testdata/lvs/ringo_simple_io.cir.2 index 3b02b848c..3f2524e11 100644 --- a/testdata/lvs/ringo_simple_io.cir.2 +++ b/testdata/lvs/ringo_simple_io.cir.2 @@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1 .ENDS RINGO .SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE -M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U -M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U +M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U + PD=2.75U .ENDS INVX1 .SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE -M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U -M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U -M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U +M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 \$I5 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U + PD=1.4U -M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U +M$4 OUT B \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U + PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_io.lvsdb.1 b/testdata/lvs/ringo_simple_io.lvsdb.1 index cc99cf3db..b57fc7c54 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io.lvsdb.1 @@ -546,9 +546,9 @@ H( E(AD 0) E(PS 0) E(PD 0) - T(S 2) + T(S 1) T(G 6) - T(D 1) + T(D 2) T(B 4) ) D(2 PMOS diff --git a/testdata/lvs/ringo_simple_io.lvsdb.2 b/testdata/lvs/ringo_simple_io.lvsdb.2 index 5a8273d4f..d3768aef4 100644 --- a/testdata/lvs/ringo_simple_io.lvsdb.2 +++ b/testdata/lvs/ringo_simple_io.lvsdb.2 @@ -546,9 +546,9 @@ H( E(AD 0) E(PS 0) E(PD 0) - T(S 2) + T(S 1) T(G 6) - T(D 1) + T(D 2) T(B 4) ) D(2 PMOS diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.1 b/testdata/lvs/ringo_simple_io2.lvsdb.1 index aab318d16..b5a1aabcb 100644 --- a/testdata/lvs/ringo_simple_io2.lvsdb.1 +++ b/testdata/lvs/ringo_simple_io2.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_io2.lvsdb.2 b/testdata/lvs/ringo_simple_io2.lvsdb.2 index 3a8a977fb..4bfcca0be 100644 --- a/testdata/lvs/ringo_simple_io2.lvsdb.2 +++ b/testdata/lvs/ringo_simple_io2.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir index f5506f8c1..2ced58e22 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INV * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INV * cell nd2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS nd2X1 diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 index af99b469c..f88be0bc7 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 index f85823972..e500fb5a3 100644 --- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 +++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_pin_swapping.cir b/testdata/lvs/ringo_simple_pin_swapping.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.cir +++ b/testdata/lvs/ringo_simple_pin_swapping.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 index 8190cddd7..e383b2490 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 5) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 6) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 5) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 6) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 index 04c3053f3..b06039efe 100644 --- a/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 +++ b/testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 5) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 6) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 5) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 6) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_same_device_classes.cir.1 b/testdata/lvs/ringo_simple_same_device_classes.cir.1 index 9b08c4543..577bc3ef4 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.cir.1 +++ b/testdata/lvs/ringo_simple_same_device_classes.cir.1 @@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1 .ENDS RINGO .SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE -M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U -M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U +M$1 OUT IN VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 OUT IN VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U + PD=2.75U .ENDS INVX1 .SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE -M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U -M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U -M$3 VSS A \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U +M$1 VDD A OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 OUT B VDD \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 \$I3 A VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U + PD=1.4U -M$4 \$I3 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U +M$4 OUT B \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U + PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_same_device_classes.cir.2 b/testdata/lvs/ringo_simple_same_device_classes.cir.2 index 13074cc9c..20ac90c01 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.cir.2 +++ b/testdata/lvs/ringo_simple_same_device_classes.cir.2 @@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1 .ENDS RINGO .SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE -M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U -M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U +M$1 OUT IN VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$2 OUT IN VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U + PD=2.75U .ENDS INVX1 .SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE -M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U -M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U -M$3 VSS A \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U +M$1 VDD A OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$2 OUT B VDD \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$3 \$I5 A VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U + PD=1.4U -M$4 \$I5 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U +M$4 OUT B \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U + PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 index 5fe96aee2..a6570c9a6 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.1 @@ -607,9 +607,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 index be3084317..55dbc29ba 100644 --- a/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 +++ b/testdata/lvs/ringo_simple_same_device_classes.lvsdb.2 @@ -607,9 +607,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS diff --git a/testdata/lvs/ringo_simple_simplification.cir b/testdata/lvs/ringo_simple_simplification.cir index c24088217..00c2f73be 100644 --- a/testdata/lvs/ringo_simple_simplification.cir +++ b/testdata/lvs/ringo_simple_simplification.cir @@ -52,9 +52,9 @@ X$21 6 11 9 6 15 9 INVX1 * net 4 VSS * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U +M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U +M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U .ENDS INVX2 * cell INVX1 @@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.1 b/testdata/lvs/ringo_simple_simplification.lvsdb.1 index ddf531dcf..cf50d6703 100644 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.1 +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.1 @@ -727,9 +727,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -740,9 +740,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -753,9 +753,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -766,9 +766,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -800,9 +800,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -813,9 +813,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) @@ -847,9 +847,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -860,9 +860,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.2 b/testdata/lvs/ringo_simple_simplification.lvsdb.2 index ed9919a88..475506d1f 100644 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.2 +++ b/testdata/lvs/ringo_simple_simplification.lvsdb.2 @@ -727,9 +727,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -740,9 +740,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -753,9 +753,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -766,9 +766,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -800,9 +800,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -813,9 +813,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) @@ -847,9 +847,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -860,9 +860,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_simplification.lvsdb.3 b/testdata/lvs/ringo_simple_simplification.lvsdb.3 deleted file mode 100644 index 907d3ad3f..000000000 --- a/testdata/lvs/ringo_simple_simplification.lvsdb.3 +++ /dev/null @@ -1,1095 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l2 (-275 -2150) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-140 -500) (0 0)) - rect(l11 (-1750 1100) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l6 (-950 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-70 -90) (0 0)) - rect(l11 (-170 -150) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (300 400) (0 0)) - rect(l2 (-650 -2150) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-150 -2500) (0 0)) - rect(l2 (-225 1050) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-850 -400) (0 0)) - rect(l6 (-650 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1100 400) (0 0)) - rect(l11 (800 -2100) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-150 -2500) (0 0)) - rect(l2 (-225 1050) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1100 -1760) (0 0)) - rect(l6 (725 860) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l11 (4040 2950) (610 300)) - ) - net(2 - rect(l11 (5550 2950) (900 300)) - ) - net(3 - rect(l11 (18150 2950) (900 300)) - ) - net(4 - rect(l11 (19950 2950) (900 300)) - ) - net(5 name(FB) - rect(l11 (21750 2950) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17920 -200) (0 0)) - rect(l13 (-220 -200) (400 400)) - rect(l13 (17740 -400) (400 400)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22340 860) (0 0)) - rect(l11 (-1750 -450) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l9 (-24850 -1500) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(8 name(ENABLE) - rect(l11 (2440 2940) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22340 -390) (0 0)) - rect(l11 (-1300 -400) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l10 (-24850 -800) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l11 (7350 2950) (900 300)) - ) - net(11 - rect(l11 (16350 2950) (900 300)) - ) - net(12 - rect(l11 (9150 2950) (900 300)) - ) - net(13 - rect(l11 (10950 2950) (900 300)) - ) - net(14 - rect(l11 (12750 2950) (900 300)) - ) - net(15 - rect(l11 (14550 2950) (900 300)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(17 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(18 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(19 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(20 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(21 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(17 4 match) - circuit(18 5 match) - circuit(19 6 match) - circuit(20 7 match) - circuit(21 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.cir b/testdata/lvs/ringo_simple_simplification_with_align.cir index 3af85ddd7..4996f57fa 100644 --- a/testdata/lvs/ringo_simple_simplification_with_align.cir +++ b/testdata/lvs/ringo_simple_simplification_with_align.cir @@ -52,9 +52,9 @@ X$17 6 11 9 6 15 9 INVX1 * net 4 VSS * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U +M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U +M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U .ENDS INVX2 * cell INVX1 @@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 index 50e5303d3..acb6dfc04 100644 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.1 @@ -727,9 +727,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -740,9 +740,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -753,9 +753,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -766,9 +766,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -800,9 +800,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -813,9 +813,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) @@ -847,9 +847,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -860,9 +860,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 index 65093a30b..650cb1b5a 100644 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 +++ b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.2 @@ -727,9 +727,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -740,9 +740,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -753,9 +753,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -766,9 +766,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -800,9 +800,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -813,9 +813,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) @@ -847,9 +847,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -860,9 +860,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 b/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 deleted file mode 100644 index c6d878db4..000000000 --- a/testdata/lvs/ringo_simple_simplification_with_align.lvsdb.3 +++ /dev/null @@ -1,1095 +0,0 @@ -#%lvsdb-klayout - -# Layout -layout( - top(RINGO) - unit(0.001) - - # Layer section - # This section lists the mask layers (drawing or derived) and their connections. - - # Mask layers - layer(l3 '1/0') - layer(l4 '5/0') - layer(l8 '8/0') - layer(l11 '9/0') - layer(l12 '10/0') - layer(l13 '11/0') - layer(l7) - layer(l2) - layer(l9) - layer(l6) - layer(l10) - - # Mask layer connectivity - connect(l3 l3 l9) - connect(l4 l4 l8) - connect(l8 l4 l8 l11 l2 l9 l6 l10) - connect(l11 l8 l11 l12) - connect(l12 l11 l12 l13) - connect(l13 l12 l13) - connect(l7 l7) - connect(l2 l8 l2) - connect(l9 l3 l8 l9) - connect(l6 l8 l6) - connect(l10 l8 l10) - - # Global nets and connectivity - global(l7 SUBSTRATE) - global(l10 SUBSTRATE) - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Device abstracts section - # Device abstracts list the pin shapes of the devices. - device(D$PMOS PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (450 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$1 PMOS - terminal(S - rect(l2 (-575 -750) (450 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$PMOS$2 PMOS - terminal(S - rect(l2 (-550 -750) (425 1500)) - ) - terminal(G - rect(l4 (-125 -750) (250 1500)) - ) - terminal(D - rect(l2 (125 -750) (425 1500)) - ) - terminal(B - rect(l3 (-125 -750) (250 1500)) - ) - ) - device(D$NMOS NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (450 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$1 NMOS - terminal(S - rect(l6 (-575 -475) (450 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - device(D$NMOS$2 NMOS - terminal(S - rect(l6 (-550 -475) (425 950)) - ) - terminal(G - rect(l4 (-125 -475) (250 950)) - ) - terminal(D - rect(l6 (125 -475) (425 950)) - ) - terminal(B - rect(l7 (-125 -475) (250 950)) - ) - ) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -790) (300 1700)) - rect(l11 (-1350 0) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l2 (-275 -2150) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1810 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-1580 3760) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090)) - rect(l11 (-110 1390) (300 1400)) - polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300)) - rect(l11 (-140 -500) (0 0)) - rect(l11 (-1750 1100) (300 1400)) - rect(l11 (1100 -1700) (300 300)) - rect(l11 (-300 0) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-1150 -400) (0 0)) - rect(l6 (-950 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2600 3500)) - ) - net(5 name(B) - rect(l4 (1425 2860) (250 1940)) - rect(l4 (-345 -950) (300 300)) - rect(l4 (-205 650) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-285 1050) (180 180)) - rect(l11 (-70 -90) (0 0)) - rect(l11 (-170 -150) (300 300)) - ) - net(6 name(A) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-325 -1850) (300 300)) - rect(l4 (-225 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-265 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(7 name(SUBSTRATE)) - net(8 - rect(l6 (975 1660) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.3375) - param(PS 3.85) - param(PD 1.95) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 D$PMOS$1 - location(1550 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.3375) - param(AD 0.6375) - param(PS 1.95) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 D$NMOS - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.21375) - param(PS 2.75) - param(PD 1.4) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 D$NMOS$1 - location(1550 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.21375) - param(AD 0.40375) - param(PS 1.4) - param(PD 2.75) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Circuit boundary - rect((-100 400) (2000 7600)) - - # Nets with their geometries - net(1 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-240 -240) (300 1400)) - rect(l11 (-650 300) (1800 800)) - rect(l11 (-1450 -1100) (300 300)) - rect(l11 (300 400) (0 0)) - rect(l2 (-650 -2150) (425 1500)) - ) - net(2 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-150 -2500) (0 0)) - rect(l2 (-225 1050) (425 1500)) - rect(l6 (-425 -4890) (425 950)) - ) - net(3 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -1300) (300 1360)) - rect(l11 (-650 -2160) (1800 800)) - rect(l11 (-850 -400) (0 0)) - rect(l6 (-650 860) (425 950)) - ) - net(4 - rect(l3 (-100 4500) (2000 3500)) - ) - net(5 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-525 -1850) (300 300)) - rect(l4 (-25 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-250 -5390) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4) - pin(5 name(IN)) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS$2 - location(850 5800) - param(L 0.25) - param(W 1.5) - param(AS 0.6375) - param(AD 0.6375) - param(PS 3.85) - param(PD 3.85) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 D$NMOS$2 - location(850 2135) - param(L 0.25) - param(W 0.95) - param(AS 0.40375) - param(AD 0.40375) - param(PS 2.75) - param(PD 2.75) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Circuit boundary - rect((-100 400) (2600 7600)) - - # Nets with their geometries - net(1 name(IN) - rect(l4 (725 2860) (250 1940)) - rect(l4 (-225 -1300) (675 450)) - rect(l4 (0 -1100) (250 1950)) - rect(l4 (-1225 -1850) (300 300)) - rect(l4 (675 1550) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (-950 -2000) (250 2000)) - rect(l4 (-250 -2000) (250 2000)) - rect(l4 (450 -5390) (250 1450)) - rect(l4 (-950 -1450) (250 1450)) - rect(l8 (-465 150) (180 180)) - rect(l11 (-90 -90) (0 0)) - rect(l11 (-150 -150) (300 300)) - ) - net(2 name(VDD) - rect(l8 (410 6260) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (1220 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l11 (-1640 -240) (300 1400)) - rect(l11 (-650 300) (2400 800)) - rect(l11 (-2050 -1100) (300 300)) - rect(l11 (1100 -300) (300 300)) - rect(l11 (-1100 400) (0 0)) - rect(l11 (800 -2100) (300 1400)) - rect(l2 (-1750 -1450) (425 1500)) - rect(l2 (950 -1500) (425 1500)) - ) - net(3 name(OUT) - rect(l8 (1110 5160) (180 180)) - rect(l8 (-180 920) (180 180)) - rect(l8 (-180 -730) (180 180)) - rect(l8 (-180 -4120) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-240 -790) (300 4790)) - rect(l11 (-150 -2500) (0 0)) - rect(l2 (-225 1050) (425 1500)) - rect(l2 (-400 -1500) (425 1500)) - rect(l6 (-450 -4890) (425 950)) - rect(l6 (-400 -950) (425 950)) - ) - net(4 name(VSS) - rect(l8 (410 1770) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (1220 -730) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-1640 -1300) (300 1360)) - rect(l11 (-650 -2160) (2400 800)) - rect(l11 (-650 0) (300 1360)) - rect(l11 (-1100 -1760) (0 0)) - rect(l6 (725 860) (425 950)) - rect(l6 (-1800 -950) (425 950)) - ) - net(5 - rect(l3 (-100 4500) (2600 3500)) - ) - net(6 name(SUBSTRATE)) - - # Outgoing pins and their connections to nets - pin(1 name(IN)) - pin(2 name(VDD)) - pin(3 name(OUT)) - pin(4 name(VSS)) - pin(5) - pin(6 name(SUBSTRATE)) - - # Devices and their connections - device(1 D$PMOS - device(D$PMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 5800) - param(L 0.25) - param(W 3) - param(AS 0.975) - param(AD 0.975) - param(PS 5.8) - param(PD 5.8) - terminal(S 2) - terminal(G 1) - terminal(D 3) - terminal(B 5) - ) - device(3 D$NMOS - device(D$NMOS$1 location(700 0)) - connect(0 S S) - connect(1 S D) - connect(0 G G) - connect(1 G G) - connect(0 D D) - connect(1 D S) - connect(0 B B) - connect(1 B B) - location(850 2135) - param(L 0.25) - param(W 1.9) - param(AS 0.6175) - param(AD 0.6175) - param(PS 4.15) - param(PD 4.15) - terminal(S 4) - terminal(G 1) - terminal(D 3) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Circuit boundary - rect((600 350) (25800 7650)) - - # Nets with their geometries - net(1 - rect(l11 (4040 2950) (610 300)) - ) - net(2 - rect(l11 (5550 2950) (900 300)) - ) - net(3 - rect(l11 (18150 2950) (900 300)) - ) - net(4 - rect(l11 (19950 2950) (900 300)) - ) - net(5 name(FB) - rect(l11 (21750 2950) (900 300)) - rect(l11 (-19530 590) (320 320)) - rect(l11 (17820 -320) (320 320)) - rect(l12 (-18400 -260) (200 200)) - rect(l12 (17940 -200) (200 200)) - rect(l13 (-18040 -300) (17740 400)) - rect(l13 (-17920 -200) (0 0)) - rect(l13 (-220 -200) (400 400)) - rect(l13 (17740 -400) (400 400)) - ) - net(6 name(VDD) - rect(l3 (1100 4500) (1400 3500)) - rect(l3 (-1900 -3500) (600 3500)) - rect(l3 (23300 -3500) (1400 3500)) - rect(l3 (-100 -3500) (600 3500)) - rect(l8 (-24690 -1240) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l11 (-22340 860) (0 0)) - rect(l11 (-1750 -450) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23400 -800) (1200 800)) - rect(l11 (-750 -1450) (300 1400)) - rect(l11 (-100 -350) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l9 (-24850 -1500) (500 1500)) - rect(l9 (22900 -1500) (500 1500)) - ) - net(7 name(OUT) - rect(l11 (23440 3840) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(8 name(ENABLE) - rect(l11 (2440 2940) (320 320)) - rect(l12 (-260 -260) (200 200)) - rect(l13 (-100 -100) (0 0)) - rect(l13 (-200 -200) (400 400)) - ) - net(9 name(VSS) - rect(l8 (1710 1610) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l8 (23220 370) (180 180)) - rect(l8 (-180 -1280) (180 180)) - rect(l8 (-180 370) (180 180)) - rect(l11 (-22340 -390) (0 0)) - rect(l11 (-1300 -400) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (-1250 -400) (600 800)) - rect(l11 (23850 -750) (300 1400)) - rect(l11 (-750 -1450) (1200 800)) - rect(l11 (-550 -400) (0 0)) - rect(l11 (550 -400) (600 800)) - rect(l10 (-24850 -800) (500 1500)) - rect(l10 (22900 -1500) (500 1500)) - ) - net(10 - rect(l11 (7350 2950) (900 300)) - ) - net(11 - rect(l11 (16350 2950) (900 300)) - ) - net(12 - rect(l11 (9150 2950) (900 300)) - ) - net(13 - rect(l11 (10950 2950) (900 300)) - ) - net(14 - rect(l11 (12750 2950) (900 300)) - ) - net(15 - rect(l11 (14550 2950) (900 300)) - ) - - # Outgoing pins and their connections to nets - pin(5 name(FB)) - pin(6 name(VDD)) - pin(7 name(OUT)) - pin(8 name(ENABLE)) - pin(9 name(VSS)) - - # Subcircuits and their connections - circuit(1 ND2X1 location(1800 0) - pin(0 6) - pin(1 1) - pin(2 9) - pin(3 6) - pin(4 5) - pin(5 8) - pin(6 9) - ) - circuit(2 INVX1 location(4200 0) - pin(0 6) - pin(1 2) - pin(2 9) - pin(3 6) - pin(4 1) - pin(5 9) - ) - circuit(3 INVX1 location(6000 0) - pin(0 6) - pin(1 10) - pin(2 9) - pin(3 6) - pin(4 2) - pin(5 9) - ) - circuit(4 INVX1 location(16800 0) - pin(0 6) - pin(1 3) - pin(2 9) - pin(3 6) - pin(4 11) - pin(5 9) - ) - circuit(5 INVX1 location(18600 0) - pin(0 6) - pin(1 4) - pin(2 9) - pin(3 6) - pin(4 3) - pin(5 9) - ) - circuit(6 INVX1 location(20400 0) - pin(0 6) - pin(1 5) - pin(2 9) - pin(3 6) - pin(4 4) - pin(5 9) - ) - circuit(7 INVX2 location(22200 0) - pin(0 5) - pin(1 6) - pin(2 7) - pin(3 9) - pin(4 6) - pin(5 9) - ) - circuit(13 INVX1 location(7800 0) - pin(0 6) - pin(1 12) - pin(2 9) - pin(3 6) - pin(4 10) - pin(5 9) - ) - circuit(14 INVX1 location(9600 0) - pin(0 6) - pin(1 13) - pin(2 9) - pin(3 6) - pin(4 12) - pin(5 9) - ) - circuit(15 INVX1 location(11400 0) - pin(0 6) - pin(1 14) - pin(2 9) - pin(3 6) - pin(4 13) - pin(5 9) - ) - circuit(16 INVX1 location(13200 0) - pin(0 6) - pin(1 15) - pin(2 9) - pin(3 6) - pin(4 14) - pin(5 9) - ) - circuit(17 INVX1 location(15000 0) - pin(0 6) - pin(1 11) - pin(2 9) - pin(3 6) - pin(4 15) - pin(5 9) - ) - - ) -) - -# Reference netlist -reference( - - # Device class section - class(PMOS MOS4) - class(NMOS MOS4) - - # Circuit section - # Circuits are the hierarchical building blocks of the netlist. - circuit(ND2X1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(B)) - net(6 name(A)) - net(7 name(BULK)) - net(8 name('1')) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(B)) - pin(6 name(A)) - pin(7 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 2) - terminal(G 6) - terminal(D 1) - terminal(B 4) - ) - device(2 PMOS - name($2) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(3 NMOS - name($3) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 6) - terminal(D 8) - terminal(B 7) - ) - device(4 NMOS - name($4) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 8) - terminal(G 5) - terminal(D 2) - terminal(B 7) - ) - - ) - circuit(INVX1 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 1.5) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 0.95) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(INVX2 - - # Nets - net(1 name(VDD)) - net(2 name(OUT)) - net(3 name(VSS)) - net(4 name(NWELL)) - net(5 name(IN)) - net(6 name(BULK)) - - # Outgoing pins and their connections to nets - pin(1 name(VDD)) - pin(2 name(OUT)) - pin(3 name(VSS)) - pin(4 name(NWELL)) - pin(5 name(IN)) - pin(6 name(BULK)) - - # Devices and their connections - device(1 PMOS - name($1) - param(L 0.25) - param(W 3) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 1) - terminal(G 5) - terminal(D 2) - terminal(B 4) - ) - device(2 NMOS - name($2) - param(L 0.25) - param(W 1.9) - param(AS 0) - param(AD 0) - param(PS 0) - param(PD 0) - terminal(S 3) - terminal(G 5) - terminal(D 2) - terminal(B 6) - ) - - ) - circuit(RINGO - - # Nets - net(1 name(VSS)) - net(2 name(VDD)) - net(3 name(FB)) - net(4 name(ENABLE)) - net(5 name(OUT)) - net(6 name('1')) - net(7 name('2')) - net(8 name('3')) - net(9 name('4')) - net(10 name('5')) - net(11 name('6')) - net(12 name('7')) - net(13 name('8')) - net(14 name('9')) - net(15 name('10')) - - # Outgoing pins and their connections to nets - pin(1 name(VSS)) - pin(2 name(VDD)) - pin(3 name(FB)) - pin(4 name(ENABLE)) - pin(5 name(OUT)) - - # Subcircuits and their connections - circuit(1 ND2X1 name($1) - pin(0 2) - pin(1 6) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 4) - pin(6 1) - ) - circuit(2 INVX1 name($2) - pin(0 2) - pin(1 7) - pin(2 1) - pin(3 2) - pin(4 6) - pin(5 1) - ) - circuit(3 INVX1 name($3) - pin(0 2) - pin(1 8) - pin(2 1) - pin(3 2) - pin(4 7) - pin(5 1) - ) - circuit(4 INVX1 name($4) - pin(0 2) - pin(1 9) - pin(2 1) - pin(3 2) - pin(4 8) - pin(5 1) - ) - circuit(5 INVX1 name($5) - pin(0 2) - pin(1 10) - pin(2 1) - pin(3 2) - pin(4 9) - pin(5 1) - ) - circuit(6 INVX1 name($6) - pin(0 2) - pin(1 11) - pin(2 1) - pin(3 2) - pin(4 10) - pin(5 1) - ) - circuit(7 INVX1 name($7) - pin(0 2) - pin(1 12) - pin(2 1) - pin(3 2) - pin(4 11) - pin(5 1) - ) - circuit(8 INVX1 name($8) - pin(0 2) - pin(1 13) - pin(2 1) - pin(3 2) - pin(4 12) - pin(5 1) - ) - circuit(9 INVX1 name($9) - pin(0 2) - pin(1 14) - pin(2 1) - pin(3 2) - pin(4 13) - pin(5 1) - ) - circuit(10 INVX1 name($10) - pin(0 2) - pin(1 15) - pin(2 1) - pin(3 2) - pin(4 14) - pin(5 1) - ) - circuit(11 INVX1 name($11) - pin(0 2) - pin(1 3) - pin(2 1) - pin(3 2) - pin(4 15) - pin(5 1) - ) - circuit(12 INVX2 name($12) - pin(0 2) - pin(1 5) - pin(2 1) - pin(3 2) - pin(4 3) - pin(5 1) - ) - - ) -) - -# Cross reference -xref( - circuit(INVX1 INVX1 match - xref( - net(4 4 match) - net(5 5 match) - net(2 2 match) - net(6 6 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(4 4 match) - pin(1 1 match) - pin(5 5 match) - pin(0 0 match) - pin(2 2 match) - device(2 2 match) - device(1 1 match) - ) - ) - circuit(INVX2 INVX2 match - xref( - net(5 4 match) - net(1 5 match) - net(3 2 match) - net(6 6 match) - net(2 1 match) - net(4 3 match) - pin(4 3 match) - pin(0 4 match) - pin(2 1 match) - pin(5 5 match) - pin(1 0 match) - pin(3 2 match) - device(3 2 match) - device(1 1 match) - ) - ) - circuit(ND2X1 ND2X1 match - xref( - net(8 8 match) - net(4 4 match) - net(6 6 match) - net(5 5 match) - net(2 2 match) - net(7 7 match) - net(1 1 match) - net(3 3 match) - pin(3 3 match) - pin(5 5 match) - pin(4 4 match) - pin(1 1 match) - pin(6 6 match) - pin(0 0 match) - pin(2 2 match) - device(3 3 match) - device(4 4 match) - device(1 1 match) - device(2 2 match) - ) - ) - circuit(RINGO RINGO match - xref( - net(1 6 match) - net(4 15 match) - net(2 7 match) - net(10 8 match) - net(12 9 match) - net(13 10 match) - net(14 11 match) - net(15 12 match) - net(11 13 match) - net(3 14 match) - net(8 4 match) - net(5 3 match) - net(7 5 match) - net(6 2 match) - net(9 1 match) - pin(3 3 match) - pin(0 2 match) - pin(2 4 match) - pin(1 1 match) - pin(4 0 match) - circuit(2 2 match) - circuit(3 3 match) - circuit(13 4 match) - circuit(14 5 match) - circuit(15 6 match) - circuit(16 7 match) - circuit(17 8 match) - circuit(4 9 match) - circuit(5 10 match) - circuit(6 11 match) - circuit(7 12 match) - circuit(1 1 match) - ) - ) -) diff --git a/testdata/lvs/ringo_simple_with_tol.cir b/testdata/lvs/ringo_simple_with_tol.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_simple_with_tol.cir +++ b/testdata/lvs/ringo_simple_with_tol.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_with_tol.lvsdb.1 b/testdata/lvs/ringo_simple_with_tol.lvsdb.1 index a1d3399c2..628deb17f 100644 --- a/testdata/lvs/ringo_simple_with_tol.lvsdb.1 +++ b/testdata/lvs/ringo_simple_with_tol.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_with_tol.lvsdb.2 b/testdata/lvs/ringo_simple_with_tol.lvsdb.2 index ee9718b35..6316f5d39 100644 --- a/testdata/lvs/ringo_simple_with_tol.lvsdb.2 +++ b/testdata/lvs/ringo_simple_with_tol.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_with_tol_early.cir b/testdata/lvs/ringo_simple_with_tol_early.cir index 761afb771..fb393a610 100644 --- a/testdata/lvs/ringo_simple_with_tol_early.cir +++ b/testdata/lvs/ringo_simple_with_tol_early.cir @@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1 * net 5 IN * net 6 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U +M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U * device instance $2 r0 *1 0.85,2.135 NMOS -M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U +M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U .ENDS INVX1 * cell ND2X1 @@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U * net 6 A * net 7 SUBSTRATE * device instance $1 r0 *1 0.85,5.8 PMOS -M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U +M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U * device instance $2 r0 *1 1.55,5.8 PMOS -M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U +M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U * device instance $3 r0 *1 0.85,2.135 NMOS -M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U +M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U * device instance $4 r0 *1 1.55,2.135 NMOS -M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U +M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U .ENDS ND2X1 diff --git a/testdata/lvs/ringo_simple_with_tol_early.lvsdb.1 b/testdata/lvs/ringo_simple_with_tol_early.lvsdb.1 index a1d3399c2..628deb17f 100644 --- a/testdata/lvs/ringo_simple_with_tol_early.lvsdb.1 +++ b/testdata/lvs/ringo_simple_with_tol_early.lvsdb.1 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/ringo_simple_with_tol_early.lvsdb.2 b/testdata/lvs/ringo_simple_with_tol_early.lvsdb.2 index ee9718b35..6316f5d39 100644 --- a/testdata/lvs/ringo_simple_with_tol_early.lvsdb.2 +++ b/testdata/lvs/ringo_simple_with_tol_early.lvsdb.2 @@ -605,9 +605,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 1) terminal(G 6) - terminal(D 1) + terminal(D 2) terminal(B 4) ) device(2 PMOS @@ -618,9 +618,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(3 NMOS @@ -631,9 +631,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 8) terminal(G 6) - terminal(D 8) + terminal(D 3) terminal(B 7) ) device(4 NMOS @@ -644,9 +644,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 8) terminal(B 7) ) @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 1) terminal(B 4) ) device(2 NMOS @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 3) + terminal(S 2) terminal(G 5) - terminal(D 2) + terminal(D 3) terminal(B 6) ) diff --git a/testdata/lvs/test_22a.lvsdb.1 b/testdata/lvs/test_22a.lvsdb.1 index 1e64cd538..a09d71fe2 100644 --- a/testdata/lvs/test_22a.lvsdb.1 +++ b/testdata/lvs/test_22a.lvsdb.1 @@ -1873,9 +1873,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 2) terminal(B 2) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -1886,9 +1886,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 2) terminal(G 14) - terminal(D 2) + terminal(D 13) terminal(B 2) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -1899,9 +1899,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 1) terminal(B 1) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -1912,9 +1912,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 1) terminal(G 14) - terminal(D 1) + terminal(D 13) terminal(B 1) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -1925,9 +1925,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 14) terminal(G 3) - terminal(D 14) + terminal(D 5) terminal(B 1) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -1938,9 +1938,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 13) terminal(G 3) - terminal(D 13) + terminal(D 6) terminal(B 1) ) device(7 SKY130_FD_PR__PFET_01V8__MODEL @@ -1951,9 +1951,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 2) terminal(B 2) ) device(8 SKY130_FD_PR__PFET_01V8__MODEL @@ -1964,9 +1964,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 2) terminal(G 16) - terminal(D 2) + terminal(D 15) terminal(B 2) ) device(9 SKY130_FD_PR__NFET_01V8__MODEL @@ -1977,9 +1977,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 1) terminal(B 1) ) device(10 SKY130_FD_PR__NFET_01V8__MODEL @@ -1990,9 +1990,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 1) terminal(G 16) - terminal(D 1) + terminal(D 15) terminal(B 1) ) device(11 SKY130_FD_PR__NFET_01V8__MODEL @@ -2003,9 +2003,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 16) terminal(G 4) - terminal(D 16) + terminal(D 5) terminal(B 1) ) device(12 SKY130_FD_PR__NFET_01V8__MODEL @@ -2016,9 +2016,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 15) terminal(G 4) - terminal(D 15) + terminal(D 6) terminal(B 1) ) device(13 SKY130_FD_PR__PFET_01V8__MODEL @@ -2029,9 +2029,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 2) terminal(B 2) ) device(14 SKY130_FD_PR__PFET_01V8__MODEL @@ -2042,9 +2042,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 2) terminal(G 18) - terminal(D 2) + terminal(D 17) terminal(B 2) ) device(15 SKY130_FD_PR__NFET_01V8__MODEL @@ -2055,9 +2055,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 1) terminal(B 1) ) device(16 SKY130_FD_PR__NFET_01V8__MODEL @@ -2068,9 +2068,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 1) terminal(G 18) - terminal(D 1) + terminal(D 17) terminal(B 1) ) device(17 SKY130_FD_PR__NFET_01V8__MODEL @@ -2081,9 +2081,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 18) terminal(G 3) - terminal(D 18) + terminal(D 7) terminal(B 1) ) device(18 SKY130_FD_PR__NFET_01V8__MODEL @@ -2094,9 +2094,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 17) terminal(G 3) - terminal(D 17) + terminal(D 8) terminal(B 1) ) device(19 SKY130_FD_PR__PFET_01V8__MODEL @@ -2107,9 +2107,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 2) terminal(B 2) ) device(20 SKY130_FD_PR__PFET_01V8__MODEL @@ -2120,9 +2120,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 2) terminal(G 20) - terminal(D 2) + terminal(D 19) terminal(B 2) ) device(21 SKY130_FD_PR__NFET_01V8__MODEL @@ -2133,9 +2133,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 1) terminal(B 1) ) device(22 SKY130_FD_PR__NFET_01V8__MODEL @@ -2146,9 +2146,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 1) terminal(G 20) - terminal(D 1) + terminal(D 19) terminal(B 1) ) device(23 SKY130_FD_PR__NFET_01V8__MODEL @@ -2159,9 +2159,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 20) terminal(G 4) - terminal(D 20) + terminal(D 7) terminal(B 1) ) device(24 SKY130_FD_PR__NFET_01V8__MODEL @@ -2172,9 +2172,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 19) terminal(G 4) - terminal(D 19) + terminal(D 8) terminal(B 1) ) device(25 SKY130_FD_PR__PFET_01V8__MODEL @@ -2185,9 +2185,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 2) terminal(B 2) ) device(26 SKY130_FD_PR__PFET_01V8__MODEL @@ -2198,9 +2198,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 2) terminal(G 22) - terminal(D 2) + terminal(D 21) terminal(B 2) ) device(27 SKY130_FD_PR__NFET_01V8__MODEL @@ -2211,9 +2211,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 1) terminal(B 1) ) device(28 SKY130_FD_PR__NFET_01V8__MODEL @@ -2224,9 +2224,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 1) terminal(G 22) - terminal(D 1) + terminal(D 21) terminal(B 1) ) device(29 SKY130_FD_PR__NFET_01V8__MODEL @@ -2237,9 +2237,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 22) terminal(G 3) - terminal(D 22) + terminal(D 9) terminal(B 1) ) device(30 SKY130_FD_PR__NFET_01V8__MODEL @@ -2250,9 +2250,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 21) terminal(G 3) - terminal(D 21) + terminal(D 10) terminal(B 1) ) device(31 SKY130_FD_PR__PFET_01V8__MODEL @@ -2263,9 +2263,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 2) terminal(B 2) ) device(32 SKY130_FD_PR__PFET_01V8__MODEL @@ -2276,9 +2276,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 2) terminal(G 24) - terminal(D 2) + terminal(D 23) terminal(B 2) ) device(33 SKY130_FD_PR__NFET_01V8__MODEL @@ -2289,9 +2289,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 1) terminal(B 1) ) device(34 SKY130_FD_PR__NFET_01V8__MODEL @@ -2302,9 +2302,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 1) terminal(G 24) - terminal(D 1) + terminal(D 23) terminal(B 1) ) device(35 SKY130_FD_PR__NFET_01V8__MODEL @@ -2315,9 +2315,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 24) terminal(G 4) - terminal(D 24) + terminal(D 9) terminal(B 1) ) device(36 SKY130_FD_PR__NFET_01V8__MODEL @@ -2328,9 +2328,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 23) terminal(G 4) - terminal(D 23) + terminal(D 10) terminal(B 1) ) device(37 SKY130_FD_PR__PFET_01V8__MODEL @@ -2341,9 +2341,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 2) terminal(B 2) ) device(38 SKY130_FD_PR__PFET_01V8__MODEL @@ -2354,9 +2354,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 2) terminal(G 26) - terminal(D 2) + terminal(D 25) terminal(B 2) ) device(39 SKY130_FD_PR__NFET_01V8__MODEL @@ -2367,9 +2367,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 1) terminal(B 1) ) device(40 SKY130_FD_PR__NFET_01V8__MODEL @@ -2380,9 +2380,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 1) terminal(G 26) - terminal(D 1) + terminal(D 25) terminal(B 1) ) device(41 SKY130_FD_PR__NFET_01V8__MODEL @@ -2393,9 +2393,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 26) terminal(G 3) - terminal(D 26) + terminal(D 11) terminal(B 1) ) device(42 SKY130_FD_PR__NFET_01V8__MODEL @@ -2406,9 +2406,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 25) terminal(G 3) - terminal(D 25) + terminal(D 12) terminal(B 1) ) device(43 SKY130_FD_PR__PFET_01V8__MODEL @@ -2419,9 +2419,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 2) terminal(B 2) ) device(44 SKY130_FD_PR__PFET_01V8__MODEL @@ -2432,9 +2432,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 2) terminal(G 28) - terminal(D 2) + terminal(D 27) terminal(B 2) ) device(45 SKY130_FD_PR__NFET_01V8__MODEL @@ -2445,9 +2445,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 1) terminal(B 1) ) device(46 SKY130_FD_PR__NFET_01V8__MODEL @@ -2458,9 +2458,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 1) terminal(G 28) - terminal(D 1) + terminal(D 27) terminal(B 1) ) device(47 SKY130_FD_PR__NFET_01V8__MODEL @@ -2471,9 +2471,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 28) terminal(G 4) - terminal(D 28) + terminal(D 11) terminal(B 1) ) device(48 SKY130_FD_PR__NFET_01V8__MODEL @@ -2484,9 +2484,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 27) terminal(G 4) - terminal(D 27) + terminal(D 12) terminal(B 1) ) diff --git a/testdata/lvs/test_22a.lvsdb.2 b/testdata/lvs/test_22a.lvsdb.2 index df6c2ec1b..b2354cc21 100644 --- a/testdata/lvs/test_22a.lvsdb.2 +++ b/testdata/lvs/test_22a.lvsdb.2 @@ -1873,9 +1873,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 2) terminal(B 2) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -1886,9 +1886,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 2) terminal(G 14) - terminal(D 2) + terminal(D 13) terminal(B 2) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -1899,9 +1899,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 1) terminal(B 1) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -1912,9 +1912,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 1) terminal(G 14) - terminal(D 1) + terminal(D 13) terminal(B 1) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -1925,9 +1925,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 14) terminal(G 3) - terminal(D 14) + terminal(D 5) terminal(B 1) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -1938,9 +1938,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 13) terminal(G 3) - terminal(D 13) + terminal(D 6) terminal(B 1) ) device(7 SKY130_FD_PR__PFET_01V8__MODEL @@ -1951,9 +1951,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 2) terminal(B 2) ) device(8 SKY130_FD_PR__PFET_01V8__MODEL @@ -1964,9 +1964,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 2) terminal(G 16) - terminal(D 2) + terminal(D 15) terminal(B 2) ) device(9 SKY130_FD_PR__NFET_01V8__MODEL @@ -1977,9 +1977,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 1) terminal(B 1) ) device(10 SKY130_FD_PR__NFET_01V8__MODEL @@ -1990,9 +1990,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 1) terminal(G 16) - terminal(D 1) + terminal(D 15) terminal(B 1) ) device(11 SKY130_FD_PR__NFET_01V8__MODEL @@ -2003,9 +2003,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 16) terminal(G 4) - terminal(D 16) + terminal(D 5) terminal(B 1) ) device(12 SKY130_FD_PR__NFET_01V8__MODEL @@ -2016,9 +2016,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 15) terminal(G 4) - terminal(D 15) + terminal(D 6) terminal(B 1) ) device(13 SKY130_FD_PR__PFET_01V8__MODEL @@ -2029,9 +2029,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 2) terminal(B 2) ) device(14 SKY130_FD_PR__PFET_01V8__MODEL @@ -2042,9 +2042,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 2) terminal(G 18) - terminal(D 2) + terminal(D 17) terminal(B 2) ) device(15 SKY130_FD_PR__NFET_01V8__MODEL @@ -2055,9 +2055,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 1) terminal(B 1) ) device(16 SKY130_FD_PR__NFET_01V8__MODEL @@ -2068,9 +2068,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 1) terminal(G 18) - terminal(D 1) + terminal(D 17) terminal(B 1) ) device(17 SKY130_FD_PR__NFET_01V8__MODEL @@ -2081,9 +2081,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 18) terminal(G 3) - terminal(D 18) + terminal(D 7) terminal(B 1) ) device(18 SKY130_FD_PR__NFET_01V8__MODEL @@ -2094,9 +2094,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 17) terminal(G 3) - terminal(D 17) + terminal(D 8) terminal(B 1) ) device(19 SKY130_FD_PR__PFET_01V8__MODEL @@ -2107,9 +2107,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 2) terminal(B 2) ) device(20 SKY130_FD_PR__PFET_01V8__MODEL @@ -2120,9 +2120,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 2) terminal(G 20) - terminal(D 2) + terminal(D 19) terminal(B 2) ) device(21 SKY130_FD_PR__NFET_01V8__MODEL @@ -2133,9 +2133,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 1) terminal(B 1) ) device(22 SKY130_FD_PR__NFET_01V8__MODEL @@ -2146,9 +2146,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 1) terminal(G 20) - terminal(D 1) + terminal(D 19) terminal(B 1) ) device(23 SKY130_FD_PR__NFET_01V8__MODEL @@ -2159,9 +2159,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 20) terminal(G 4) - terminal(D 20) + terminal(D 7) terminal(B 1) ) device(24 SKY130_FD_PR__NFET_01V8__MODEL @@ -2172,9 +2172,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 19) terminal(G 4) - terminal(D 19) + terminal(D 8) terminal(B 1) ) device(25 SKY130_FD_PR__PFET_01V8__MODEL @@ -2185,9 +2185,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 2) terminal(B 2) ) device(26 SKY130_FD_PR__PFET_01V8__MODEL @@ -2198,9 +2198,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 2) terminal(G 22) - terminal(D 2) + terminal(D 21) terminal(B 2) ) device(27 SKY130_FD_PR__NFET_01V8__MODEL @@ -2211,9 +2211,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 1) terminal(B 1) ) device(28 SKY130_FD_PR__NFET_01V8__MODEL @@ -2224,9 +2224,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 1) terminal(G 22) - terminal(D 1) + terminal(D 21) terminal(B 1) ) device(29 SKY130_FD_PR__NFET_01V8__MODEL @@ -2237,9 +2237,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 22) terminal(G 3) - terminal(D 22) + terminal(D 9) terminal(B 1) ) device(30 SKY130_FD_PR__NFET_01V8__MODEL @@ -2250,9 +2250,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 21) terminal(G 3) - terminal(D 21) + terminal(D 10) terminal(B 1) ) device(31 SKY130_FD_PR__PFET_01V8__MODEL @@ -2263,9 +2263,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 2) terminal(B 2) ) device(32 SKY130_FD_PR__PFET_01V8__MODEL @@ -2276,9 +2276,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 2) terminal(G 24) - terminal(D 2) + terminal(D 23) terminal(B 2) ) device(33 SKY130_FD_PR__NFET_01V8__MODEL @@ -2289,9 +2289,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 1) terminal(B 1) ) device(34 SKY130_FD_PR__NFET_01V8__MODEL @@ -2302,9 +2302,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 1) terminal(G 24) - terminal(D 1) + terminal(D 23) terminal(B 1) ) device(35 SKY130_FD_PR__NFET_01V8__MODEL @@ -2315,9 +2315,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 24) terminal(G 4) - terminal(D 24) + terminal(D 9) terminal(B 1) ) device(36 SKY130_FD_PR__NFET_01V8__MODEL @@ -2328,9 +2328,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 23) terminal(G 4) - terminal(D 23) + terminal(D 10) terminal(B 1) ) device(37 SKY130_FD_PR__PFET_01V8__MODEL @@ -2341,9 +2341,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 2) terminal(B 2) ) device(38 SKY130_FD_PR__PFET_01V8__MODEL @@ -2354,9 +2354,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 2) terminal(G 26) - terminal(D 2) + terminal(D 25) terminal(B 2) ) device(39 SKY130_FD_PR__NFET_01V8__MODEL @@ -2367,9 +2367,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 1) terminal(B 1) ) device(40 SKY130_FD_PR__NFET_01V8__MODEL @@ -2380,9 +2380,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 1) terminal(G 26) - terminal(D 1) + terminal(D 25) terminal(B 1) ) device(41 SKY130_FD_PR__NFET_01V8__MODEL @@ -2393,9 +2393,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 26) terminal(G 3) - terminal(D 26) + terminal(D 11) terminal(B 1) ) device(42 SKY130_FD_PR__NFET_01V8__MODEL @@ -2406,9 +2406,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 25) terminal(G 3) - terminal(D 25) + terminal(D 12) terminal(B 1) ) device(43 SKY130_FD_PR__PFET_01V8__MODEL @@ -2419,9 +2419,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 2) terminal(B 2) ) device(44 SKY130_FD_PR__PFET_01V8__MODEL @@ -2432,9 +2432,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 2) terminal(G 28) - terminal(D 2) + terminal(D 27) terminal(B 2) ) device(45 SKY130_FD_PR__NFET_01V8__MODEL @@ -2445,9 +2445,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 1) terminal(B 1) ) device(46 SKY130_FD_PR__NFET_01V8__MODEL @@ -2458,9 +2458,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 1) terminal(G 28) - terminal(D 1) + terminal(D 27) terminal(B 1) ) device(47 SKY130_FD_PR__NFET_01V8__MODEL @@ -2471,9 +2471,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 28) terminal(G 4) - terminal(D 28) + terminal(D 11) terminal(B 1) ) device(48 SKY130_FD_PR__NFET_01V8__MODEL @@ -2484,9 +2484,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 27) terminal(G 4) - terminal(D 27) + terminal(D 12) terminal(B 1) ) diff --git a/testdata/lvs/test_22b.lvsdb.1 b/testdata/lvs/test_22b.lvsdb.1 index c3f876fc0..5b71fbe2d 100644 --- a/testdata/lvs/test_22b.lvsdb.1 +++ b/testdata/lvs/test_22b.lvsdb.1 @@ -1873,9 +1873,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 2) terminal(B 2) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -1886,9 +1886,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 2) terminal(G 14) - terminal(D 2) + terminal(D 13) terminal(B 2) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -1899,9 +1899,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 1) terminal(B 1) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -1912,9 +1912,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 1) terminal(G 14) - terminal(D 1) + terminal(D 13) terminal(B 1) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -1925,9 +1925,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 14) terminal(G 3) - terminal(D 14) + terminal(D 5) terminal(B 1) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -1938,9 +1938,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 13) terminal(G 3) - terminal(D 13) + terminal(D 6) terminal(B 1) ) device(7 SKY130_FD_PR__PFET_01V8__MODEL @@ -1951,9 +1951,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 2) terminal(B 2) ) device(8 SKY130_FD_PR__PFET_01V8__MODEL @@ -1964,9 +1964,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 2) terminal(G 16) - terminal(D 2) + terminal(D 15) terminal(B 2) ) device(9 SKY130_FD_PR__NFET_01V8__MODEL @@ -1977,9 +1977,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 1) terminal(B 1) ) device(10 SKY130_FD_PR__NFET_01V8__MODEL @@ -1990,9 +1990,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 1) terminal(G 16) - terminal(D 1) + terminal(D 15) terminal(B 1) ) device(11 SKY130_FD_PR__NFET_01V8__MODEL @@ -2003,9 +2003,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 16) terminal(G 4) - terminal(D 16) + terminal(D 5) terminal(B 1) ) device(12 SKY130_FD_PR__NFET_01V8__MODEL @@ -2016,9 +2016,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 15) terminal(G 4) - terminal(D 15) + terminal(D 6) terminal(B 1) ) device(13 SKY130_FD_PR__PFET_01V8__MODEL @@ -2029,9 +2029,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 2) terminal(B 2) ) device(14 SKY130_FD_PR__PFET_01V8__MODEL @@ -2042,9 +2042,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 2) terminal(G 18) - terminal(D 2) + terminal(D 17) terminal(B 2) ) device(15 SKY130_FD_PR__NFET_01V8__MODEL @@ -2055,9 +2055,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 1) terminal(B 1) ) device(16 SKY130_FD_PR__NFET_01V8__MODEL @@ -2068,9 +2068,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 1) terminal(G 18) - terminal(D 1) + terminal(D 17) terminal(B 1) ) device(17 SKY130_FD_PR__NFET_01V8__MODEL @@ -2081,9 +2081,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 18) terminal(G 3) - terminal(D 18) + terminal(D 7) terminal(B 1) ) device(18 SKY130_FD_PR__NFET_01V8__MODEL @@ -2094,9 +2094,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 17) terminal(G 3) - terminal(D 17) + terminal(D 8) terminal(B 1) ) device(19 SKY130_FD_PR__PFET_01V8__MODEL @@ -2107,9 +2107,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 2) terminal(B 2) ) device(20 SKY130_FD_PR__PFET_01V8__MODEL @@ -2120,9 +2120,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 2) terminal(G 20) - terminal(D 2) + terminal(D 19) terminal(B 2) ) device(21 SKY130_FD_PR__NFET_01V8__MODEL @@ -2133,9 +2133,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 1) terminal(B 1) ) device(22 SKY130_FD_PR__NFET_01V8__MODEL @@ -2146,9 +2146,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 1) terminal(G 20) - terminal(D 1) + terminal(D 19) terminal(B 1) ) device(23 SKY130_FD_PR__NFET_01V8__MODEL @@ -2159,9 +2159,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 20) terminal(G 4) - terminal(D 20) + terminal(D 7) terminal(B 1) ) device(24 SKY130_FD_PR__NFET_01V8__MODEL @@ -2172,9 +2172,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 19) terminal(G 4) - terminal(D 19) + terminal(D 8) terminal(B 1) ) device(25 SKY130_FD_PR__PFET_01V8__MODEL @@ -2185,9 +2185,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 2) terminal(B 2) ) device(26 SKY130_FD_PR__PFET_01V8__MODEL @@ -2198,9 +2198,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 2) terminal(G 22) - terminal(D 2) + terminal(D 21) terminal(B 2) ) device(27 SKY130_FD_PR__NFET_01V8__MODEL @@ -2211,9 +2211,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 1) terminal(B 1) ) device(28 SKY130_FD_PR__NFET_01V8__MODEL @@ -2224,9 +2224,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 1) terminal(G 22) - terminal(D 1) + terminal(D 21) terminal(B 1) ) device(29 SKY130_FD_PR__NFET_01V8__MODEL @@ -2237,9 +2237,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 22) terminal(G 3) - terminal(D 22) + terminal(D 9) terminal(B 1) ) device(30 SKY130_FD_PR__NFET_01V8__MODEL @@ -2250,9 +2250,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 21) terminal(G 3) - terminal(D 21) + terminal(D 10) terminal(B 1) ) device(31 SKY130_FD_PR__PFET_01V8__MODEL @@ -2263,9 +2263,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 2) terminal(B 2) ) device(32 SKY130_FD_PR__PFET_01V8__MODEL @@ -2276,9 +2276,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 2) terminal(G 24) - terminal(D 2) + terminal(D 23) terminal(B 2) ) device(33 SKY130_FD_PR__NFET_01V8__MODEL @@ -2289,9 +2289,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 1) terminal(B 1) ) device(34 SKY130_FD_PR__NFET_01V8__MODEL @@ -2302,9 +2302,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 1) terminal(G 24) - terminal(D 1) + terminal(D 23) terminal(B 1) ) device(35 SKY130_FD_PR__NFET_01V8__MODEL @@ -2315,9 +2315,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 24) terminal(G 4) - terminal(D 24) + terminal(D 9) terminal(B 1) ) device(36 SKY130_FD_PR__NFET_01V8__MODEL @@ -2328,9 +2328,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 23) terminal(G 4) - terminal(D 23) + terminal(D 10) terminal(B 1) ) device(37 SKY130_FD_PR__PFET_01V8__MODEL @@ -2341,9 +2341,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 2) terminal(B 2) ) device(38 SKY130_FD_PR__PFET_01V8__MODEL @@ -2354,9 +2354,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 2) terminal(G 26) - terminal(D 2) + terminal(D 25) terminal(B 2) ) device(39 SKY130_FD_PR__NFET_01V8__MODEL @@ -2367,9 +2367,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 1) terminal(B 1) ) device(40 SKY130_FD_PR__NFET_01V8__MODEL @@ -2380,9 +2380,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 1) terminal(G 26) - terminal(D 1) + terminal(D 25) terminal(B 1) ) device(41 SKY130_FD_PR__NFET_01V8__MODEL @@ -2393,9 +2393,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 26) terminal(G 3) - terminal(D 26) + terminal(D 11) terminal(B 1) ) device(42 SKY130_FD_PR__NFET_01V8__MODEL @@ -2406,9 +2406,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 25) terminal(G 3) - terminal(D 25) + terminal(D 12) terminal(B 1) ) device(43 SKY130_FD_PR__PFET_01V8__MODEL @@ -2419,9 +2419,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 2) terminal(B 2) ) device(44 SKY130_FD_PR__PFET_01V8__MODEL @@ -2432,9 +2432,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 2) terminal(G 28) - terminal(D 2) + terminal(D 27) terminal(B 2) ) device(45 SKY130_FD_PR__NFET_01V8__MODEL @@ -2445,9 +2445,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 1) terminal(B 1) ) device(46 SKY130_FD_PR__NFET_01V8__MODEL @@ -2458,9 +2458,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 1) terminal(G 28) - terminal(D 1) + terminal(D 27) terminal(B 1) ) device(47 SKY130_FD_PR__NFET_01V8__MODEL @@ -2471,9 +2471,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 28) terminal(G 4) - terminal(D 28) + terminal(D 11) terminal(B 1) ) device(48 SKY130_FD_PR__NFET_01V8__MODEL @@ -2484,9 +2484,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 27) terminal(G 4) - terminal(D 27) + terminal(D 12) terminal(B 1) ) diff --git a/testdata/lvs/test_22b.lvsdb.2 b/testdata/lvs/test_22b.lvsdb.2 index e30655ac0..03b56d2fd 100644 --- a/testdata/lvs/test_22b.lvsdb.2 +++ b/testdata/lvs/test_22b.lvsdb.2 @@ -1873,9 +1873,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 2) terminal(B 2) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -1886,9 +1886,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 2) terminal(G 14) - terminal(D 2) + terminal(D 13) terminal(B 2) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -1899,9 +1899,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 14) terminal(G 13) - terminal(D 14) + terminal(D 1) terminal(B 1) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -1912,9 +1912,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 13) + terminal(S 1) terminal(G 14) - terminal(D 1) + terminal(D 13) terminal(B 1) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -1925,9 +1925,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 14) terminal(G 3) - terminal(D 14) + terminal(D 5) terminal(B 1) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -1938,9 +1938,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 13) terminal(G 3) - terminal(D 13) + terminal(D 6) terminal(B 1) ) device(7 SKY130_FD_PR__PFET_01V8__MODEL @@ -1951,9 +1951,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 2) terminal(B 2) ) device(8 SKY130_FD_PR__PFET_01V8__MODEL @@ -1964,9 +1964,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 2) terminal(G 16) - terminal(D 2) + terminal(D 15) terminal(B 2) ) device(9 SKY130_FD_PR__NFET_01V8__MODEL @@ -1977,9 +1977,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 16) terminal(G 15) - terminal(D 16) + terminal(D 1) terminal(B 1) ) device(10 SKY130_FD_PR__NFET_01V8__MODEL @@ -1990,9 +1990,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 15) + terminal(S 1) terminal(G 16) - terminal(D 1) + terminal(D 15) terminal(B 1) ) device(11 SKY130_FD_PR__NFET_01V8__MODEL @@ -2003,9 +2003,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 16) terminal(G 4) - terminal(D 16) + terminal(D 5) terminal(B 1) ) device(12 SKY130_FD_PR__NFET_01V8__MODEL @@ -2016,9 +2016,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 15) terminal(G 4) - terminal(D 15) + terminal(D 6) terminal(B 1) ) device(13 SKY130_FD_PR__PFET_01V8__MODEL @@ -2029,9 +2029,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 2) terminal(B 2) ) device(14 SKY130_FD_PR__PFET_01V8__MODEL @@ -2042,9 +2042,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 2) terminal(G 18) - terminal(D 2) + terminal(D 17) terminal(B 2) ) device(15 SKY130_FD_PR__NFET_01V8__MODEL @@ -2055,9 +2055,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 18) terminal(G 17) - terminal(D 18) + terminal(D 1) terminal(B 1) ) device(16 SKY130_FD_PR__NFET_01V8__MODEL @@ -2068,9 +2068,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 17) + terminal(S 1) terminal(G 18) - terminal(D 1) + terminal(D 17) terminal(B 1) ) device(17 SKY130_FD_PR__NFET_01V8__MODEL @@ -2081,9 +2081,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 18) terminal(G 3) - terminal(D 18) + terminal(D 7) terminal(B 1) ) device(18 SKY130_FD_PR__NFET_01V8__MODEL @@ -2094,9 +2094,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 17) terminal(G 3) - terminal(D 17) + terminal(D 8) terminal(B 1) ) device(19 SKY130_FD_PR__PFET_01V8__MODEL @@ -2107,9 +2107,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 2) terminal(B 2) ) device(20 SKY130_FD_PR__PFET_01V8__MODEL @@ -2120,9 +2120,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 2) terminal(G 20) - terminal(D 2) + terminal(D 19) terminal(B 2) ) device(21 SKY130_FD_PR__NFET_01V8__MODEL @@ -2133,9 +2133,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 20) terminal(G 19) - terminal(D 20) + terminal(D 1) terminal(B 1) ) device(22 SKY130_FD_PR__NFET_01V8__MODEL @@ -2146,9 +2146,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 19) + terminal(S 1) terminal(G 20) - terminal(D 1) + terminal(D 19) terminal(B 1) ) device(23 SKY130_FD_PR__NFET_01V8__MODEL @@ -2159,9 +2159,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 7) + terminal(S 20) terminal(G 4) - terminal(D 20) + terminal(D 7) terminal(B 1) ) device(24 SKY130_FD_PR__NFET_01V8__MODEL @@ -2172,9 +2172,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 8) + terminal(S 19) terminal(G 4) - terminal(D 19) + terminal(D 8) terminal(B 1) ) device(25 SKY130_FD_PR__PFET_01V8__MODEL @@ -2185,9 +2185,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 2) terminal(B 2) ) device(26 SKY130_FD_PR__PFET_01V8__MODEL @@ -2198,9 +2198,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 2) terminal(G 22) - terminal(D 2) + terminal(D 21) terminal(B 2) ) device(27 SKY130_FD_PR__NFET_01V8__MODEL @@ -2211,9 +2211,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 22) terminal(G 21) - terminal(D 22) + terminal(D 1) terminal(B 1) ) device(28 SKY130_FD_PR__NFET_01V8__MODEL @@ -2224,9 +2224,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 21) + terminal(S 1) terminal(G 22) - terminal(D 1) + terminal(D 21) terminal(B 1) ) device(29 SKY130_FD_PR__NFET_01V8__MODEL @@ -2237,9 +2237,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 22) terminal(G 3) - terminal(D 22) + terminal(D 9) terminal(B 1) ) device(30 SKY130_FD_PR__NFET_01V8__MODEL @@ -2250,9 +2250,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 21) terminal(G 3) - terminal(D 21) + terminal(D 10) terminal(B 1) ) device(31 SKY130_FD_PR__PFET_01V8__MODEL @@ -2263,9 +2263,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 2) terminal(B 2) ) device(32 SKY130_FD_PR__PFET_01V8__MODEL @@ -2276,9 +2276,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 2) terminal(G 24) - terminal(D 2) + terminal(D 23) terminal(B 2) ) device(33 SKY130_FD_PR__NFET_01V8__MODEL @@ -2289,9 +2289,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 24) terminal(G 23) - terminal(D 24) + terminal(D 1) terminal(B 1) ) device(34 SKY130_FD_PR__NFET_01V8__MODEL @@ -2302,9 +2302,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 23) + terminal(S 1) terminal(G 24) - terminal(D 1) + terminal(D 23) terminal(B 1) ) device(35 SKY130_FD_PR__NFET_01V8__MODEL @@ -2315,9 +2315,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 9) + terminal(S 24) terminal(G 4) - terminal(D 24) + terminal(D 9) terminal(B 1) ) device(36 SKY130_FD_PR__NFET_01V8__MODEL @@ -2328,9 +2328,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 10) + terminal(S 23) terminal(G 4) - terminal(D 23) + terminal(D 10) terminal(B 1) ) device(37 SKY130_FD_PR__PFET_01V8__MODEL @@ -2341,9 +2341,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 2) terminal(B 2) ) device(38 SKY130_FD_PR__PFET_01V8__MODEL @@ -2354,9 +2354,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 2) terminal(G 26) - terminal(D 2) + terminal(D 25) terminal(B 2) ) device(39 SKY130_FD_PR__NFET_01V8__MODEL @@ -2367,9 +2367,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 26) terminal(G 25) - terminal(D 26) + terminal(D 1) terminal(B 1) ) device(40 SKY130_FD_PR__NFET_01V8__MODEL @@ -2380,9 +2380,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 25) + terminal(S 1) terminal(G 26) - terminal(D 1) + terminal(D 25) terminal(B 1) ) device(41 SKY130_FD_PR__NFET_01V8__MODEL @@ -2393,9 +2393,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 26) terminal(G 3) - terminal(D 26) + terminal(D 11) terminal(B 1) ) device(42 SKY130_FD_PR__NFET_01V8__MODEL @@ -2406,9 +2406,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 25) terminal(G 3) - terminal(D 25) + terminal(D 12) terminal(B 1) ) device(43 SKY130_FD_PR__PFET_01V8__MODEL @@ -2419,9 +2419,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 2) terminal(B 2) ) device(44 SKY130_FD_PR__PFET_01V8__MODEL @@ -2432,9 +2432,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 2) terminal(G 28) - terminal(D 2) + terminal(D 27) terminal(B 2) ) device(45 SKY130_FD_PR__NFET_01V8__MODEL @@ -2445,9 +2445,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 28) terminal(G 27) - terminal(D 28) + terminal(D 1) terminal(B 1) ) device(46 SKY130_FD_PR__NFET_01V8__MODEL @@ -2458,9 +2458,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 27) + terminal(S 1) terminal(G 28) - terminal(D 1) + terminal(D 27) terminal(B 1) ) device(47 SKY130_FD_PR__NFET_01V8__MODEL @@ -2471,9 +2471,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 11) + terminal(S 28) terminal(G 4) - terminal(D 28) + terminal(D 11) terminal(B 1) ) device(48 SKY130_FD_PR__NFET_01V8__MODEL @@ -2484,9 +2484,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 12) + terminal(S 27) terminal(G 4) - terminal(D 27) + terminal(D 12) terminal(B 1) ) diff --git a/testdata/lvs/test_22c.lvsdb.1 b/testdata/lvs/test_22c.lvsdb.1 index 0e0b1750e..3daddbd99 100644 --- a/testdata/lvs/test_22c.lvsdb.1 +++ b/testdata/lvs/test_22c.lvsdb.1 @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) diff --git a/testdata/lvs/test_22c.lvsdb.2 b/testdata/lvs/test_22c.lvsdb.2 index 4e5c37050..4e459b3fe 100644 --- a/testdata/lvs/test_22c.lvsdb.2 +++ b/testdata/lvs/test_22c.lvsdb.2 @@ -93,7 +93,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -101,13 +101,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (75 -210) (265 420)) + rect(l2 (-340 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -121,7 +121,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -129,13 +129,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (-340 -210) (265 420)) + rect(l2 (75 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -285,8 +285,8 @@ layout( rect(l2 (-2430 -1410) (250 720)) rect(l2 (-250 270) (265 420)) rect(l2 (1915 -1410) (250 720)) - rect(l6 (-250 -720) (250 720)) rect(l6 (-2430 -720) (250 720)) + rect(l6 (1930 -720) (250 720)) ) # Outgoing pins and their connections to nets @@ -298,32 +298,6 @@ layout( # Devices and their connections device(1 D$sky130_fd_pr__nfet_01v8__model - location(1575 215) - param(L 0.15) - param(W 0.42) - param(AS 0.1113) - param(AD 0.18165) - param(PS 1.37) - param(PD 1.285) - terminal(S 8) - terminal(G 6) - terminal(D 4) - terminal(B 10) - ) - device(2 D$sky130_fd_pr__nfet_01v8__model$1 - location(1965 840) - param(L 0.15) - param(W 0.42) - param(AS 0.18165) - param(AD 0.1113) - param(PS 1.285) - param(PD 1.37) - terminal(S 4) - terminal(G 3) - terminal(D 10) - terminal(B 10) - ) - device(3 D$sky130_fd_pr__nfet_01v8__model$2 location(605 215) param(L 0.15) param(W 0.42) @@ -336,7 +310,7 @@ layout( terminal(D 3) terminal(B 10) ) - device(4 D$sky130_fd_pr__nfet_01v8__model$3 + device(2 D$sky130_fd_pr__nfet_01v8__model$1 location(215 840) param(L 0.15) param(W 0.42) @@ -349,6 +323,32 @@ layout( terminal(D 10) terminal(B 10) ) + device(3 D$sky130_fd_pr__nfet_01v8__model$2 + location(1575 215) + param(L 0.15) + param(W 0.42) + param(AS 0.1113) + param(AD 0.18165) + param(PS 1.37) + param(PD 1.285) + terminal(S 8) + terminal(G 6) + terminal(D 4) + terminal(B 10) + ) + device(4 D$sky130_fd_pr__nfet_01v8__model$3 + location(1965 840) + param(L 0.15) + param(W 0.42) + param(AS 0.18165) + param(AD 0.1113) + param(PS 1.285) + param(PD 1.37) + terminal(S 4) + terminal(G 3) + terminal(D 10) + terminal(B 10) + ) device(5 D$sky130_fd_pr__pfet_01v8__model location(1965 2170) param(L 0.15) @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) @@ -941,10 +941,10 @@ xref( pin(0 0 match) pin(4 1 match) pin(1 2 match) - device(4 3 match) - device(2 4 match) - device(3 5 match) - device(1 6 match) + device(2 3 match) + device(4 4 match) + device(1 5 match) + device(3 6 match) device(6 1 match) device(5 2 match) ) diff --git a/testdata/lvs/test_22c.lvsdb.3 b/testdata/lvs/test_22c.lvsdb.3 index e235e4c85..66213ecfc 100644 --- a/testdata/lvs/test_22c.lvsdb.3 +++ b/testdata/lvs/test_22c.lvsdb.3 @@ -93,7 +93,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -101,13 +101,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (-340 -210) (265 420)) + rect(l2 (75 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -121,7 +121,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -129,13 +129,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (75 -210) (265 420)) + rect(l2 (-340 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -285,8 +285,8 @@ layout( rect(l2 (-2430 -1410) (250 720)) rect(l2 (-250 270) (265 420)) rect(l2 (1915 -1410) (250 720)) + rect(l6 (-250 -720) (250 720)) rect(l6 (-2430 -720) (250 720)) - rect(l6 (1930 -720) (250 720)) ) # Outgoing pins and their connections to nets @@ -298,32 +298,6 @@ layout( # Devices and their connections device(1 D$sky130_fd_pr__nfet_01v8__model - location(605 215) - param(L 0.15) - param(W 0.42) - param(AS 0.1113) - param(AD 0.18165) - param(PS 1.37) - param(PD 1.285) - terminal(S 7) - terminal(G 6) - terminal(D 3) - terminal(B 10) - ) - device(2 D$sky130_fd_pr__nfet_01v8__model$1 - location(215 840) - param(L 0.15) - param(W 0.42) - param(AS 0.18165) - param(AD 0.1113) - param(PS 1.285) - param(PD 1.37) - terminal(S 3) - terminal(G 4) - terminal(D 10) - terminal(B 10) - ) - device(3 D$sky130_fd_pr__nfet_01v8__model$2 location(1575 215) param(L 0.15) param(W 0.42) @@ -336,7 +310,7 @@ layout( terminal(D 4) terminal(B 10) ) - device(4 D$sky130_fd_pr__nfet_01v8__model$3 + device(2 D$sky130_fd_pr__nfet_01v8__model$1 location(1965 840) param(L 0.15) param(W 0.42) @@ -349,6 +323,32 @@ layout( terminal(D 10) terminal(B 10) ) + device(3 D$sky130_fd_pr__nfet_01v8__model$2 + location(605 215) + param(L 0.15) + param(W 0.42) + param(AS 0.1113) + param(AD 0.18165) + param(PS 1.37) + param(PD 1.285) + terminal(S 7) + terminal(G 6) + terminal(D 3) + terminal(B 10) + ) + device(4 D$sky130_fd_pr__nfet_01v8__model$3 + location(215 840) + param(L 0.15) + param(W 0.42) + param(AS 0.18165) + param(AD 0.1113) + param(PS 1.285) + param(PD 1.37) + terminal(S 3) + terminal(G 4) + terminal(D 10) + terminal(B 10) + ) device(5 D$sky130_fd_pr__pfet_01v8__model location(1965 2170) param(L 0.15) @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) @@ -941,10 +941,10 @@ xref( pin(0 0 match) pin(4 1 match) pin(1 2 match) - device(2 3 match) - device(4 4 match) - device(1 5 match) - device(3 6 match) + device(4 3 match) + device(2 4 match) + device(3 5 match) + device(1 6 match) device(6 1 match) device(5 2 match) ) diff --git a/testdata/lvs/test_22d.lvsdb.1 b/testdata/lvs/test_22d.lvsdb.1 index 4f171845c..453674e0e 100644 --- a/testdata/lvs/test_22d.lvsdb.1 +++ b/testdata/lvs/test_22d.lvsdb.1 @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) diff --git a/testdata/lvs/test_22d.lvsdb.2 b/testdata/lvs/test_22d.lvsdb.2 index 3a3bd09c8..253f1dbb1 100644 --- a/testdata/lvs/test_22d.lvsdb.2 +++ b/testdata/lvs/test_22d.lvsdb.2 @@ -93,7 +93,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -101,13 +101,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (75 -210) (265 420)) + rect(l2 (-340 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -121,7 +121,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -129,13 +129,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (-340 -210) (265 420)) + rect(l2 (75 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -285,8 +285,8 @@ layout( rect(l2 (-2430 -1410) (250 720)) rect(l2 (-250 270) (265 420)) rect(l2 (1915 -1410) (250 720)) - rect(l6 (-250 -720) (250 720)) rect(l6 (-2430 -720) (250 720)) + rect(l6 (1930 -720) (250 720)) ) # Outgoing pins and their connections to nets @@ -298,32 +298,6 @@ layout( # Devices and their connections device(1 D$sky130_fd_pr__nfet_01v8__model - location(1575 215) - param(L 0.15) - param(W 0.42) - param(AS 0.1113) - param(AD 0.18165) - param(PS 1.37) - param(PD 1.285) - terminal(S 8) - terminal(G 6) - terminal(D 4) - terminal(B 10) - ) - device(2 D$sky130_fd_pr__nfet_01v8__model$1 - location(1965 840) - param(L 0.15) - param(W 0.42) - param(AS 0.18165) - param(AD 0.1113) - param(PS 1.285) - param(PD 1.37) - terminal(S 4) - terminal(G 3) - terminal(D 10) - terminal(B 10) - ) - device(3 D$sky130_fd_pr__nfet_01v8__model$2 location(605 215) param(L 0.15) param(W 0.42) @@ -336,7 +310,7 @@ layout( terminal(D 3) terminal(B 10) ) - device(4 D$sky130_fd_pr__nfet_01v8__model$3 + device(2 D$sky130_fd_pr__nfet_01v8__model$1 location(215 840) param(L 0.15) param(W 0.42) @@ -349,6 +323,32 @@ layout( terminal(D 10) terminal(B 10) ) + device(3 D$sky130_fd_pr__nfet_01v8__model$2 + location(1575 215) + param(L 0.15) + param(W 0.42) + param(AS 0.1113) + param(AD 0.18165) + param(PS 1.37) + param(PD 1.285) + terminal(S 8) + terminal(G 6) + terminal(D 4) + terminal(B 10) + ) + device(4 D$sky130_fd_pr__nfet_01v8__model$3 + location(1965 840) + param(L 0.15) + param(W 0.42) + param(AS 0.18165) + param(AD 0.1113) + param(PS 1.285) + param(PD 1.37) + terminal(S 4) + terminal(G 3) + terminal(D 10) + terminal(B 10) + ) device(5 D$sky130_fd_pr__pfet_01v8__model location(1965 2170) param(L 0.15) @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) @@ -941,10 +941,10 @@ xref( pin(0 0 match) pin(4 1 match) pin(1 2 match) - device(4 3 match) - device(2 4 match) - device(3 5 match) - device(1 6 match) + device(2 3 match) + device(4 4 match) + device(1 5 match) + device(3 6 match) device(6 1 match) device(5 2 match) ) diff --git a/testdata/lvs/test_22d.lvsdb.3 b/testdata/lvs/test_22d.lvsdb.3 index 32d8060e5..a0c293345 100644 --- a/testdata/lvs/test_22d.lvsdb.3 +++ b/testdata/lvs/test_22d.lvsdb.3 @@ -93,7 +93,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -101,13 +101,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$1 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) + polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (-340 -210) (265 420)) + rect(l2 (75 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -121,7 +121,7 @@ layout( rect(l22 (-210 -75) (420 150)) ) terminal(D - polygon(l2 (-210 75) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (-210 75) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(B rect(l1 (-210 -75) (420 150)) @@ -129,13 +129,13 @@ layout( ) device(D$sky130_fd_pr__nfet_01v8__model$3 sky130_fd_pr__nfet_01v8__model terminal(S - polygon(l2 (-600 -550) (0 760) (525 0) (0 -420) (-105 0) (0 -340)) + polygon(l2 (180 -550) (0 340) (-105 0) (0 420) (525 0) (0 -760)) ) terminal(G rect(l22 (-75 -210) (150 420)) ) terminal(D - rect(l2 (75 -210) (265 420)) + rect(l2 (-340 -210) (265 420)) ) terminal(B rect(l1 (-75 -210) (150 420)) @@ -285,8 +285,8 @@ layout( rect(l2 (-2430 -1410) (250 720)) rect(l2 (-250 270) (265 420)) rect(l2 (1915 -1410) (250 720)) + rect(l6 (-250 -720) (250 720)) rect(l6 (-2430 -720) (250 720)) - rect(l6 (1930 -720) (250 720)) ) # Outgoing pins and their connections to nets @@ -298,32 +298,6 @@ layout( # Devices and their connections device(1 D$sky130_fd_pr__nfet_01v8__model - location(605 215) - param(L 0.15) - param(W 0.42) - param(AS 0.1113) - param(AD 0.18165) - param(PS 1.37) - param(PD 1.285) - terminal(S 7) - terminal(G 6) - terminal(D 3) - terminal(B 10) - ) - device(2 D$sky130_fd_pr__nfet_01v8__model$1 - location(215 840) - param(L 0.15) - param(W 0.42) - param(AS 0.18165) - param(AD 0.1113) - param(PS 1.285) - param(PD 1.37) - terminal(S 3) - terminal(G 4) - terminal(D 10) - terminal(B 10) - ) - device(3 D$sky130_fd_pr__nfet_01v8__model$2 location(1575 215) param(L 0.15) param(W 0.42) @@ -336,7 +310,7 @@ layout( terminal(D 4) terminal(B 10) ) - device(4 D$sky130_fd_pr__nfet_01v8__model$3 + device(2 D$sky130_fd_pr__nfet_01v8__model$1 location(1965 840) param(L 0.15) param(W 0.42) @@ -349,6 +323,32 @@ layout( terminal(D 10) terminal(B 10) ) + device(3 D$sky130_fd_pr__nfet_01v8__model$2 + location(605 215) + param(L 0.15) + param(W 0.42) + param(AS 0.1113) + param(AD 0.18165) + param(PS 1.37) + param(PD 1.285) + terminal(S 7) + terminal(G 6) + terminal(D 3) + terminal(B 10) + ) + device(4 D$sky130_fd_pr__nfet_01v8__model$3 + location(215 840) + param(L 0.15) + param(W 0.42) + param(AS 0.18165) + param(AD 0.1113) + param(PS 1.285) + param(PD 1.37) + terminal(S 3) + terminal(G 4) + terminal(D 10) + terminal(B 10) + ) device(5 D$sky130_fd_pr__pfet_01v8__model location(1965 2170) param(L 0.15) @@ -652,9 +652,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 1) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 1) terminal(B 1) ) device(2 SKY130_FD_PR__PFET_01V8__MODEL @@ -665,9 +665,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 1) terminal(G 7) - terminal(D 1) + terminal(D 6) terminal(B 1) ) device(3 SKY130_FD_PR__NFET_01V8__MODEL @@ -678,9 +678,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 2) + terminal(S 7) terminal(G 6) - terminal(D 7) + terminal(D 2) terminal(B 2) ) device(4 SKY130_FD_PR__NFET_01V8__MODEL @@ -691,9 +691,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 6) + terminal(S 2) terminal(G 7) - terminal(D 2) + terminal(D 6) terminal(B 2) ) device(5 SKY130_FD_PR__NFET_01V8__MODEL @@ -704,9 +704,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 4) + terminal(S 7) terminal(G 3) - terminal(D 7) + terminal(D 4) terminal(B 2) ) device(6 SKY130_FD_PR__NFET_01V8__MODEL @@ -717,9 +717,9 @@ reference( param(AD 0) param(PS 0) param(PD 0) - terminal(S 5) + terminal(S 6) terminal(G 3) - terminal(D 6) + terminal(D 5) terminal(B 2) ) @@ -941,10 +941,10 @@ xref( pin(0 0 match) pin(4 1 match) pin(1 2 match) - device(2 3 match) - device(4 4 match) - device(1 5 match) - device(3 6 match) + device(4 3 match) + device(2 4 match) + device(3 5 match) + device(1 6 match) device(6 1 match) device(5 2 match) ) diff --git a/testdata/ruby/dbNetlistReaderTests.rb b/testdata/ruby/dbNetlistReaderTests.rb index f157b9324..3632c72f7 100644 --- a/testdata/ruby/dbNetlistReaderTests.rb +++ b/testdata/ruby/dbNetlistReaderTests.rb @@ -116,6 +116,9 @@ class DBNetlistReaderTests_TestClass < TestBase assert_equal(nl.description, "Read by MyDelegate (sucessfully)") assert_equal(nl.to_s, <<"END") +circuit .TOP (); + subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS); +end; circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1); device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24); device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24); @@ -124,9 +127,6 @@ circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1); device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64); device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0); end; -circuit .TOP (); - subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS); -end; END end @@ -147,6 +147,9 @@ END assert_equal(nl.description, "Read by MyDelegate2 (sucessfully)") assert_equal(nl.to_s, <<"END") +circuit .TOP (); + subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VXX=VXX,Z=Z,GND=VSS,GND$1=VSS); +end; circuit SUBCKT ($1=$1,A=A,VXX=VXX,Z=Z,GND=GND,GND$1=GND$1); device HVPMOS $1 (S=VXX,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24); device HVPMOS $2 (S=VXX,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24); @@ -155,9 +158,6 @@ circuit SUBCKT ($1=$1,A=A,VXX=VXX,Z=Z,GND=GND,GND$1=GND$1); device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64); device WIDERSTAND $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0); end; -circuit .TOP (); - subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VXX=VXX,Z=Z,GND=VSS,GND$1=VSS); -end; END end @@ -212,7 +212,7 @@ END pd.net_names = [ "x", "y", "z" ] assert_equal(pd.net_names.join(","), "x,y,z") pd.parameters = { "A" => 17.5, "B" => 1 } - assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1.0}") + assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1}") end @@ -222,7 +222,7 @@ END pd.strings = [ "x", "y", "z" ] assert_equal(pd.strings.join(","), "x,y,z") pd.parameters = { "A" => 17.5, "B" => 1 } - assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1.0}") + assert_equal(pd.parameters.inspect, "{\"A\"=>17.5, \"B\"=>1}") end @@ -230,7 +230,7 @@ END dg = RBA::NetlistSpiceReaderDelegate::new pd = dg.parse_element_components("17 5 1e-9 a=17 b=1k") - assert_equal(pd.strings.join(","), "17,5,1e-9") + assert_equal(pd.strings.join(","), "17,5,1E-9") assert_equal(pd.parameters.inspect, "{\"A\"=>17.0, \"B\"=>1000.0}") end