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Merge pull request #1305 from KLayout/issue-1304 

Fixed issue #1304 (terminal order for MOS devices)
This commit is contained in:
Matthias Köfferlein 2023-03-04 19:32:46 +01:00 committed by GitHub
parent f413635deb 28883ee383
commit 2facc75807
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
129 changed files with 6082 additions and 5579 deletions
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4
src/db/db/db.pro
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@ -60,6 +60,8 @@ SOURCES = \
dbNetlistCompareCore.cc \
dbNetlistCompareGraph.cc \
dbNetlistCompareUtils.cc \
dbNetlistSpiceReaderDelegate.cc \
dbNetlistSpiceReaderExpressionParser.cc \
dbObject.cc \
dbPath.cc \
dbPCellDeclaration.cc \
@ -279,6 +281,8 @@ HEADERS = \
dbNetlistCompareCore.h \
dbNetlistCompareGraph.h \
dbNetlistCompareUtils.h \
dbNetlistSpiceReaderDelegate.h \
dbNetlistSpiceReaderExpressionParser.h \
dbObject.h \
dbObjectTag.h \
dbObjectWithProperties.h \

1687
src/db/db/dbNetlistSpiceReader.cc
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202
src/db/db/dbNetlistSpiceReader.h
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@ -25,136 +25,19 @@
#include "dbCommon.h"
#include "dbNetlistReader.h"
#include "tlStream.h"
#include <string>
#include <set>
#include "tlStream.h"
#include "tlObject.h"
#include "tlVariant.h"
#include <map>
#include <memory>
#include <list>
#include <string>
namespace db
{
class Netlist;
class Net;
class Circuit;
class DeviceClass;
class Device;
/**
* @brief A specialized exception class to handle netlist reader delegate errors
*/
class DB_PUBLIC NetlistSpiceReaderDelegateError
: public tl::Exception
{
public:
NetlistSpiceReaderDelegateError (const std::string &msg)
: tl::Exception (msg)
{ }
};
/**
* @brief A delegate to handle various forms of devices and translates them
*
* The reader delegate can be configured to receive subcircuit elements too.
* In this case, parameters are allowed.
* For receiving subcircuit elements, the delegate needs to indicate
* this by returning true upon "wants_subcircuit".
*/
class DB_PUBLIC NetlistSpiceReaderDelegate
: public tl::Object
{
public:
NetlistSpiceReaderDelegate ();
virtual ~NetlistSpiceReaderDelegate ();
/**
* @brief Called when the netlist reading starts
*/
virtual void start (db::Netlist *netlist);
/**
* @brief Called when the netlist reading ends
*/
virtual void finish (db::Netlist *netlist);
/**
* @brief Called when an unknown control statement is encountered
*
* Returns true if the statement is understood.
*/
virtual bool control_statement (const std::string &line);
/**
* @brief Returns true, if the delegate wants subcircuit elements with this name
*
* The name is always upper case.
*/
virtual bool wants_subcircuit (const std::string &circuit_name);
/**
* @brief This method translates a raw net name to a valid net name
*
* The default implementation will unescape backslash sequences into plain characters.
*/
virtual std::string translate_net_name (const std::string &nn);
/**
* @brief Makes a device from an element line
*
* @param circuit The circuit that is currently read.
* @param element The upper-case element code ("M", "R", ...).
* @param name The element's name.
* @param model The upper-case model name (may be empty).
* @param value The default value (e.g. resistance for resistors) and may be zero.
* @param nets The nets given in the element line.
* @param parameters The parameters of the element statement (parameter names are upper case).
*
* The default implementation will create corresponding devices for
* some known elements using the Spice writer's parameter conventions.
*
* This method returns true, if the element was read.
*/
virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, double> &params);
/**
* @brief Parses an element from a line
*
* @param s The line to parse (the part after the element and name)
* @param model Out parameter: the model name if given
* @param value Out parameter: the value if given (for R, L, C)
* @param nn Out parameter: the net names
* @param pv Out parameter: the parameter values (key/value pairs)
*/
virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector<std::string> &nn, std::map<std::string, double> &pv);
/**
* @brief Produces an error with the given message
*/
virtual void error (const std::string &msg);
/**
* @brief Reads a set of string components and parameters from the string
* A special key "param:" is recognized for starting a parameter list.
*/
void parse_element_components (const std::string &s, std::vector<std::string> &strings, std::map<std::string, double> &pv);
/**
* @brief Reads a value from the extractor (with formula evaluation)
*/
double read_value (tl::Extractor &ex);
/**
* @brief Tries to read a value from the extractor (with formula evaluation)
*/
bool try_read_value (const std::string &s, double &v);
private:
double read_atomic_value (tl::Extractor &ex);
double read_dot_expr (tl::Extractor &ex);
double read_bar_expr (tl::Extractor &ex);
};
class NetlistSpiceReaderDelegate;
/**
* @brief A SPICE format reader for netlists
@ -163,76 +46,25 @@ class DB_PUBLIC NetlistSpiceReader
: public NetlistReader
{
public:
typedef std::map<std::string, tl::Variant> parameters_type;
NetlistSpiceReader (NetlistSpiceReaderDelegate *delegate = 0);
virtual ~NetlistSpiceReader ();
virtual void read (tl::InputStream &stream, db::Netlist &netlist);
private:
class SpiceReaderStream
/**
* @brief Sets or resets strict mode
* In strict mode, all subcircuits need to be present in the net list for example.
*/
void set_strict (bool s)
{
public:
SpiceReaderStream ();
~SpiceReaderStream ();
m_strict = s;
}
void set_stream (tl::InputStream &stream);
void set_stream (tl::InputStream *stream);
void close ();
std::pair<std::string, bool> get_line();
int line_number () const;
std::string source () const;
bool at_end () const;
void swap (SpiceReaderStream &other)
{
std::swap (mp_stream, other.mp_stream);
std::swap (m_owns_stream, other.m_owns_stream);
std::swap (mp_text_stream, other.mp_text_stream);
std::swap (m_line_number, other.m_line_number);
std::swap (m_stored_line, other.m_stored_line);
std::swap (m_has_stored_line, other.m_has_stored_line);
}
private:
tl::InputStream *mp_stream;
bool m_owns_stream;
tl::TextInputStream *mp_text_stream;
int m_line_number;
std::string m_stored_line;
bool m_has_stored_line;
};
db::Netlist *mp_netlist;
db::Circuit *mp_circuit;
db::Circuit *mp_anonymous_top_circuit;
private:
tl::weak_ptr<NetlistSpiceReaderDelegate> mp_delegate;
std::list<SpiceReaderStream> m_streams;
SpiceReaderStream m_stream;
std::unique_ptr<std::map<std::string, db::Net *> > mp_nets_by_name;
std::map<std::string, bool> m_captured;
std::vector<std::string> m_global_nets;
std::set<std::string> m_global_net_names;
std::set<const db::Circuit *> m_circuits_read;
void push_stream (const std::string &path);
void pop_stream ();
bool at_end ();
bool read_element (tl::Extractor &ex, const std::string &element, const std::string &name);
void read_subcircuit (const std::string &sc_name, const std::string &nc_name, const std::vector<db::Net *> &nets);
void read_circuit (tl::Extractor &ex, const std::string &name);
void skip_circuit (tl::Extractor &ex);
bool read_card ();
std::string read_name (tl::Extractor &ex);
std::string get_line ();
void error (const std::string &msg);
void warn (const std::string &msg);
void finish ();
db::Net *make_net (const std::string &name);
void ensure_circuit ();
bool subcircuit_captured (const std::string &nc_name);
void build_global_nets ();
bool m_strict;
};
}

588
src/db/db/dbNetlistSpiceReaderDelegate.cc Normal file
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@ -0,0 +1,588 @@
/*
KLayout Layout Viewer
Copyright (C) 2006-2023 Matthias Koefferlein
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "dbNetlistSpiceReaderDelegate.h"
#include "dbNetlistSpiceReader.h"
#include "dbNetlistSpiceReaderExpressionParser.h"
#include "dbNetlist.h"
#include "dbCircuit.h"
#include "dbNetlistDeviceClasses.h"
namespace db
{
// ------------------------------------------------------------------------------------------------------
inline static int hex_num (char c)
{
if (c >= '0' && c <= '9') {
return (int (c - '0'));
} else if (c >= 'a' && c <= 'f') {
return (int (c - 'f') + 10);
} else {
return -1;
}
}
static std::string unescape_name (const std::string &n)
{
std::string nn;
nn.reserve (n.size ());
const char *cp = n.c_str ();
while (*cp) {
if (*cp == '\\' && cp[1]) {
if (tolower (cp[1]) == 'x') {
cp += 2;
char c = 0;
for (int i = 0; i < 2 && *cp; ++i) {
int n = hex_num (*cp);
if (n >= 0) {
++cp;
c = c * 16 + char (n);
} else {
break;
}
}
nn += c;
} else {
++cp;
nn += *cp++;
}
} else {
nn += *cp++;
}
}
return nn;
}
// ------------------------------------------------------------------------------------------------------
NetlistSpiceReaderDelegate::NetlistSpiceReaderDelegate ()
: mp_netlist (0)
{
// .. nothing yet ..
}
NetlistSpiceReaderDelegate::~NetlistSpiceReaderDelegate ()
{
// .. nothing yet ..
}
void NetlistSpiceReaderDelegate::start (db::Netlist * /*netlist*/)
{
// .. nothing yet ..
}
void NetlistSpiceReaderDelegate::finish (db::Netlist * /*netlist*/)
{
// .. nothing yet ..
}
bool NetlistSpiceReaderDelegate::control_statement(const std::string & /*line*/)
{
return false;
}
bool NetlistSpiceReaderDelegate::wants_subcircuit (const std::string & /*circuit_name*/)
{
return false;
}
std::string NetlistSpiceReaderDelegate::translate_net_name (const std::string &nn)
{
return unescape_name (nn);
}
void NetlistSpiceReaderDelegate::error (const std::string &msg)
{
throw tl::Exception (msg);
}
template <class Cls>
static db::DeviceClass *make_device_class (db::Circuit *circuit, const std::string &name)
{
if (! circuit || ! circuit->netlist ()) {
return 0;
}
db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (name);
if (! cls) {
cls = new Cls ();
cls->set_name (name);
circuit->netlist ()->add_device_class (cls);
}
return cls;
}
static std::string parse_component (tl::Extractor &ex)
{
const char *cp = ex.skip ();
const char *cp0 = cp;
char quote = 0;
unsigned int brackets = 0;
while (*cp) {
if (quote) {
if (*cp == quote) {
quote = 0;
} else if (*cp == '\\' && cp[1]) {
++cp;
}
} else if ((isspace (*cp) || *cp == '=') && ! brackets) {
break;
} else if (*cp == '"' || *cp == '\'') {
quote = *cp;
} else if (*cp == '(') {
++brackets;
} else if (*cp == ')') {
if (brackets > 0) {
--brackets;
}
}
++cp;
}
ex = tl::Extractor (cp);
return std::string (cp0, cp - cp0);
}
void NetlistSpiceReaderDelegate::parse_element_components (const std::string &s, std::vector<std::string> &strings, std::map<std::string, tl::Variant> &pv, const std::map<std::string, tl::Variant> &variables)
{
tl::Extractor ex (s.c_str ());
bool in_params = false;
while (! ex.at_end ()) {
if (ex.test_without_case ("params:")) {
in_params = true;
} else {
tl::Extractor ex0 = ex;
std::string n;
if (ex.try_read_word (n) && ex.test ("=")) {
// a parameter
pv [mp_netlist ? mp_netlist->normalize_name (n) : tl::to_upper_case (n)] = read_value (ex, variables);
} else {
// a net/model component
ex = ex0;
if (in_params) {
ex.error (tl::to_string (tr ("Invalid syntax for parameter assignment - needs keyword followed by '='")));
}
std::string comp_name = parse_component (ex);
comp_name = mp_netlist ? mp_netlist->normalize_name (comp_name) : tl::to_upper_case (comp_name);
// resolve variables if string type
auto v = variables.find (comp_name);
if (v != variables.end ()) {
if (v->second.is_a_string ()) {
strings.push_back (v->second.to_string ());
} else if (v->second.can_convert_to_double ()) {
// NOTE: this allows using a variable name "x" instead of "x=x"
pv [comp_name] = v->second;
} else {
strings.push_back (comp_name);
}
} else {
strings.push_back (comp_name);
}
}
}
}
}
void NetlistSpiceReaderDelegate::parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector<std::string> &nn, std::map<std::string, tl::Variant> &pv, const std::map<std::string, tl::Variant> &variables)
{
parse_element_components (s, nn, pv, variables);
// interpret the parameters according to the code
if (element == "X") {
// subcircuit call:
// Xname n1 n2 ... nn circuit [params]
if (nn.empty ()) {
error (tl::to_string (tr ("No circuit name given for subcircuit call")));
}
model = nn.back ();
nn.pop_back ();
} else if (element == "R" || element == "C" || element == "L") {
// resistor, cap, inductor: two-terminal devices with a value
// Rname n1 n2 value
// Rname n1 n2 n3 value
// Rname n1 n2 value model [params]
// Rname n1 n2 n3 value model [params]
// Rname n1 n2 [params]
// Rname n1 n2 model [params]
// Rname n1 n2 n3 model [params]
// NOTE: there is no "Rname n1 n2 n3 [params]"!
// (same for C, L instead of R)
if (nn.size () < 2) {
error (tl::to_string (tr ("Not enough specs for a R, C or L device")));
}
auto rv = pv.find (element);
if (rv != pv.end ()) {
// value given by parameter
value = rv->second.to_double ();
if (nn.size () >= 3) {
// Rname n1 n2 model [params]
// Rname n1 n2 n3 model [params]
model = nn.back ();
nn.pop_back ();
}
} else if (nn.size () >= 3) {
if (try_read_value (nn.back (), value, variables)) {
// Rname n1 n2 value
// Rname n1 n2 n3 value
nn.pop_back ();
} else {
// Rname n1 n2 value model [params]
// Rname n1 n2 n3 value model [params]
model = nn.back ();
nn.pop_back ();
if (! try_read_value (nn.back (), value, variables)) {
error (tl::to_string (tr ("Can't find a value for a R, C or L device")));
} else {
nn.pop_back ();
}
}
}
} else {
// others: n-terminal devices with a model (last node)
if (nn.empty ()) {
error (tl::sprintf (tl::to_string (tr ("No model name given for element '%s'")), element));
}
model = nn.back ();
nn.pop_back ();
if (element == "M") {
if (nn.size () != 4) {
error (tl::to_string (tr ("'M' element must have four nodes")));
}
} else if (element == "Q") {
if (nn.size () != 3 && nn.size () != 4) {
error (tl::to_string (tr ("'Q' element must have three or four nodes")));
}
} else if (element == "D") {
if (nn.size () != 2) {
error (tl::to_string (tr ("'D' element must have two nodes")));
}
}
// TODO: other devices?
}
}
bool NetlistSpiceReaderDelegate::element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, tl::Variant> &pv)
{
std::map<std::string, tl::Variant> params = pv;
std::vector<size_t> terminal_order;
double mult = 1.0;
auto mp = params.find ("M");
if (mp != params.end ()) {
mult = mp->second.to_double ();
}
if (mult < 1e-10) {
error (tl::sprintf (tl::to_string (tr ("Invalid multiplier value (M=%.12g) - must not be zero or negative")), mult));
}
std::string cn = model;
db::DeviceClass *cls = circuit->netlist ()->device_class_by_name (cn);
if (element == "R") {
if (nets.size () == 2) {
if (cls) {
if (! dynamic_cast<db::DeviceClassResistor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a resistor device class as required by 'R' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "RES";
}
cls = make_device_class<db::DeviceClassResistor> (circuit, cn);
}
} else if (nets.size () == 3) {
if (cls) {
if (! dynamic_cast<db::DeviceClassResistorWithBulk *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal resistor device class as required by 'R' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "RES3";
}
cls = make_device_class<db::DeviceClassResistorWithBulk> (circuit, cn);
}
} else {
error (tl::to_string (tr ("A 'R' element requires two or three nets")));
}
// Apply multiplier
value /= mult;
} else if (element == "L") {
if (nets.size () == 2) {
if (cls) {
if (! dynamic_cast<db::DeviceClassInductor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a inductor device class as required by 'L' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "IND";
}
cls = make_device_class<db::DeviceClassInductor> (circuit, cn);
}
} else {
error (tl::to_string (tr ("A 'L' element requires two nets")));
}
// Apply multiplier
value /= mult;
} else if (element == "C") {
if (nets.size () == 2) {
if (cls) {
if (! dynamic_cast<db::DeviceClassCapacitor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a capacitor device class as required by 'C' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "CAP";
}
cls = make_device_class<db::DeviceClassCapacitor> (circuit, cn);
}
} else if (nets.size () == 3) {
if (cls) {
if (! dynamic_cast<db::DeviceClassCapacitorWithBulk *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a three-terminal capacitor device class as required by 'C' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "CAP3";
}
cls = make_device_class<db::DeviceClassCapacitorWithBulk> (circuit, cn);
}
} else {
error (tl::to_string (tr ("A 'C' element requires two or three nets")));
}
// Apply multiplier
value *= mult;
} else if (element == "D") {
if (cls) {
if (! dynamic_cast<db::DeviceClassDiode *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a diode device class as required by 'D' element")), cn));
}
} else {
if (cn.empty ()) {
cn = "DIODE";
}
cls = make_device_class<db::DeviceClassDiode> (circuit, cn);
}
// Apply multiplier to "A"
auto p = params.find ("A");
if (p != params.end ()) {
p->second = tl::Variant (p->second.to_double () * mult);
}
} else if (element == "Q") {
if (nets.size () != 3 && nets.size () != 4) {
error (tl::to_string (tr ("'Q' element needs to have 3 or 4 terminals")));
} else if (cls) {
if (nets.size () == 3) {
if (! dynamic_cast<db::DeviceClassBJT3Transistor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a 3-terminal BJT device class as required by 'Q' element")), cn));
}
} else {
if (! dynamic_cast<db::DeviceClassBJT4Transistor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal BJT device class as required by 'Q' element")), cn));
}
}
} else {
if (nets.size () == 3) {
if (cn.empty ()) {
cn = "BJT3";
}
cls = make_device_class<db::DeviceClassBJT3Transistor> (circuit, cn);
} else {
if (cn.empty ()) {
cn = "BJT4";
}
cls = make_device_class<db::DeviceClassBJT4Transistor> (circuit, cn);
}
}
// Apply multiplier to "AE"
auto p = params.find ("AE");
if (p != params.end ()) {
p->second = tl::Variant (p->second.to_double () * mult);
}
} else if (element == "M") {
if (cls) {
if (! dynamic_cast<db::DeviceClassMOS4Transistor *>(cls)) {
error (tl::sprintf (tl::to_string (tr ("Class %s is not a 4-terminal MOS device class as required by 'M' element")), cn));
}
} else {
if (nets.size () == 4) {
if (cn.empty ()) {
cn = "MOS4";
}
cls = make_device_class<db::DeviceClassMOS4Transistor> (circuit, cn);
} else {
error (tl::to_string (tr ("'M' element needs to have 4 terminals")));
}
}
// Apply multiplier to "W"
auto p = params.find ("W");
if (p != params.end ()) {
p->second = tl::Variant (p->second.to_double () * mult);
}
// issue #1304
terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_D);
terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_G);
terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_S);
terminal_order.push_back (DeviceClassMOS4Transistor::terminal_id_B);
} else {
error (tl::sprintf (tl::to_string (tr ("Not a known element type: '%s'")), element));
}
const std::vector<db::DeviceTerminalDefinition> &td = cls->terminal_definitions ();
if (td.size () != nets.size ()) {
error (tl::sprintf (tl::to_string (tr ("Wrong number of terminals: class '%s' expects %d, but %d are given")), cn, int (td.size ()), int (nets.size ())));
}
db::Device *device = new db::Device (cls, name);
circuit->add_device (device);
if (terminal_order.empty ()) {
for (auto t = td.begin (); t != td.end (); ++t) {
device->connect_terminal (t->id (), nets [t - td.begin ()]);
}
} else {
for (auto t = terminal_order.begin (); t != terminal_order.end (); ++t) {
device->connect_terminal (*t, nets [t - terminal_order.begin ()]);
}
}
size_t defp = std::numeric_limits<size_t>::max ();
if (dynamic_cast<db::DeviceClassCapacitor *> (cls)) {
defp = db::DeviceClassCapacitor::param_id_C;
} else if (dynamic_cast<db::DeviceClassResistor *> (cls)) {
defp = db::DeviceClassResistor::param_id_R;
} else if (dynamic_cast<db::DeviceClassInductor *> (cls)) {
defp = db::DeviceClassInductor::param_id_L;
}
std::vector<db::DeviceParameterDefinition> &pd = cls->parameter_definitions_non_const ();
for (std::vector<db::DeviceParameterDefinition>::iterator i = pd.begin (); i != pd.end (); ++i) {
auto v = params.find (i->name ());
if (v != params.end ()) {
device->set_parameter_value (i->id (), v->second.to_double () / i->si_scaling ());
} else if (i->id () == defp) {
device->set_parameter_value (i->id (), value / i->si_scaling ());
}
}
return true;
}
tl::Variant
NetlistSpiceReaderDelegate::read_value (tl::Extractor &ex, const std::map<std::string, tl::Variant> &variables)
{
NetlistSpiceReaderExpressionParser parser (&variables);
return parser.read (ex);
}
bool
NetlistSpiceReaderDelegate::try_read_value (const std::string &s, double &v, const std::map<std::string, tl::Variant> &variables)
{
NetlistSpiceReaderExpressionParser parser (&variables);
tl::Variant vv;
tl::Extractor ex (s.c_str ());
bool res = parser.try_read (ex, vv);
if (res && ! vv.can_convert_to_double ()) {
res = false;
}
if (res) {
v = vv.to_double ();
}
return res;
}
}

169
src/db/db/dbNetlistSpiceReaderDelegate.h Normal file
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@ -0,0 +1,169 @@
/*
KLayout Layout Viewer
Copyright (C) 2006-2023 Matthias Koefferlein
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef HDR_dbNetlistSpiceReaderDelegate
#define HDR_dbNetlistSpiceReaderDelegate
#include "dbCommon.h"
#include "tlStream.h"
#include "tlException.h"
#include <string>
#include <vector>
#include <map>
namespace db
{
class Netlist;
class Net;
class Circuit;
class DeviceClass;
class Device;
/**
* @brief A delegate to handle various forms of devices and translates them
*
* The reader delegate can be configured to receive subcircuit elements too.
* In this case, parameters are allowed.
* For receiving subcircuit elements, the delegate needs to indicate
* this by returning true upon "wants_subcircuit".
*/
class DB_PUBLIC NetlistSpiceReaderDelegate
: public tl::Object
{
public:
NetlistSpiceReaderDelegate ();
virtual ~NetlistSpiceReaderDelegate ();
/**
* @brief Called when the netlist reading starts
*/
virtual void start (db::Netlist *netlist);
/**
* @brief Called when the netlist reading ends
*/
virtual void finish (db::Netlist *netlist);
/**
* @brief Called when an unknown control statement is encountered
*
* Returns true if the statement is understood.
*/
virtual bool control_statement (const std::string &line);
/**
* @brief Returns true, if the delegate wants subcircuit elements with this name
*
* The name is always upper case.
*/
virtual bool wants_subcircuit (const std::string &circuit_name);
/**
* @brief This method translates a raw net name to a valid net name
*
* The default implementation will unescape backslash sequences into plain characters.
*/
virtual std::string translate_net_name (const std::string &nn);
/**
* @brief Makes a device from an element line
*
* @param circuit The circuit that is currently read.
* @param element The upper-case element code ("M", "R", ...).
* @param name The element's name.
* @param model The upper-case model name (may be empty).
* @param value The default value (e.g. resistance for resistors) and may be zero.
* @param nets The nets given in the element line.
* @param parameters The parameters of the element statement (parameter names are upper case).
*
* The default implementation will create corresponding devices for
* some known elements using the Spice writer's parameter conventions.
*
* This method returns true, if the element was read.
*/
virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, tl::Variant> &params);
/**
* @brief Parses an element from a line
*
* @param s The line to parse (the part after the element and name)
* @param model Out parameter: the model name if given
* @param value Out parameter: the value if given (for R, L, C)
* @param nn Out parameter: the net names
* @param pv Out parameter: the parameter values (key/value pairs)
*/
virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector<std::string> &nn, std::map<std::string, tl::Variant> &pv, const std::map<std::string, tl::Variant> &params);
/**
* @brief Produces an error with the given message
*/
virtual void error (const std::string &msg);
/**
* @brief Reads a set of string components and parameters from the string
* A special key "param:" is recognized for starting a parameter list.
*/
void parse_element_components (const std::string &s, std::vector<std::string> &strings, std::map<std::string, tl::Variant> &pv, const std::map<std::string, tl::Variant> &variables);
/**
* @brief Reads a value from the extractor (with formula evaluation)
*/
static tl::Variant read_value(tl::Extractor &ex, const std::map<std::string, tl::Variant> &variables);
/**
* @brief Tries to read a value from the extractor (with formula evaluation)
*/
static bool try_read_value (const std::string &s, double &v, const std::map<std::string, tl::Variant> &variables);
/**
* @brief External interface for start
*/
void do_start ()
{
start (mp_netlist);
}
/**
* @brief External interface for finish
*/
void do_finish ()
{
finish (mp_netlist);
}
/**
* @brief Sets the netlist
*/
void set_netlist (db::Netlist *netlist)
{
mp_netlist = netlist;
}
private:
db::Netlist *mp_netlist;
};
}
#endif

556
src/db/db/dbNetlistSpiceReaderExpressionParser.cc Normal file
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@ -0,0 +1,556 @@
/*
KLayout Layout Viewer
Copyright (C) 2006-2023 Matthias Koefferlein
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include "dbNetlistSpiceReaderExpressionParser.h"
#include "dbNetlistSpiceReader.h"
#include <cmath>
namespace db
{
// ------------------------------------------------------------------------------------------------------
static bool to_bool (const tl::Variant &v)
{
if (v.is_bool ()) {
return v.to_bool ();
} else if (v.is_nil ()) {
return false;
} else if (v.can_convert_to_double ()) {
return v.to_double () != 0.0;
} else {
return true;
}
}
// ------------------------------------------------------------------------------------------------------
NetlistSpiceReaderExpressionParser::NetlistSpiceReaderExpressionParser (const variables_type *vars)
{
static variables_type empty_variables;
mp_variables = vars ? vars : &empty_variables;
}
// expression syntax taken from ngspice:
// https://nmg.gitlab.io/ngspice-manual/circuitdescription/paramparametricnetlists/syntaxofexpressions.html
static double sqrt_f (double v) { return sqrt (v); }
static double sin_f (double v) { return sin (v); }
static double cos_f (double v) { return cos (v); }
static double tan_f (double v) { return tan (v); }
static double sinh_f (double v) { return sinh (v); }
static double cosh_f (double v) { return cosh (v); }
static double tanh_f (double v) { return tanh (v); }
static double asin_f (double v) { return asin (v); }
static double acos_f (double v) { return acos (v); }
static double atan_f (double v) { return atan (v); }
static double asinh_f (double v) { return asinh (v); }
static double acosh_f (double v) { return acosh (v); }
static double atanh_f (double v) { return atanh (v); }
static double exp_f (double v) { return exp (v); }
static double ln_f (double v) { return log (v); }
static double log_f (double v) { return log10 (v); }
static double abs_f (double v) { return abs (v); }
static double nint_f (double v) { return nearbyint (v); } // we basically should we the rounding mode before ...
static double floor_f (double v) { return floor (v); }
static double ceil_f (double v) { return ceil (v); }
static double sgn_f (double v) { return v == 0.0 ? 0.0 : (v < 0.0 ? -1.0 : 1.0); }
static double int_f (double v) { return sgn_f (v) * floor (sgn_f (v) * v); }
tl::Variant
NetlistSpiceReaderExpressionParser::eval_func (const std::string &name, const std::vector<tl::Variant> &params, bool * /*status*/) const
{
double (*f) (double) = 0;
if (name == "SQRT") { f = sqrt_f; } else
if (name == "SIN") { f = sin_f; } else
if (name == "COS") { f = cos_f; } else
if (name == "TAN") { f = tan_f; } else
if (name == "SINH") { f = sinh_f; } else
if (name == "COSH") { f = cosh_f; } else
if (name == "TANH") { f = tanh_f; } else
if (name == "ASIN") { f = asin_f; } else
if (name == "ACOS") { f = acos_f; } else
if (name == "ATAN" || name == "arctan") { f = atan_f; } else
if (name == "ASINH") { f = asinh_f; } else
if (name == "ACOSH") { f = acosh_f; } else
if (name == "ATANH") { f = atanh_f; } else
if (name == "EXP") { f = exp_f; } else
if (name == "LN") { f = ln_f; } else
if (name == "LOG") { f = log_f; } else
if (name == "ABS") { f = abs_f; } else
if (name == "NINT") { f = nint_f; } else
if (name == "FLOOR") { f = floor_f; } else
if (name == "CEIL") { f = ceil_f; } else
if (name == "SGN") { f = sgn_f; } else
if (name == "INT") { f = int_f; }
if (f != 0) {
if (params.size () < 1 || ! params.front ().can_convert_to_double ()) {
return tl::Variant ();
} else {
return tl::Variant ((*f) (params.front ().to_double ()));
}
} else if (name == "PWR" || name == "POW") {
if (params.size () < 2 || ! params [0].can_convert_to_double () || ! params [1].can_convert_to_double ()) {
return tl::Variant ();
} else {
return tl::Variant (pow (params [0].to_double (), params [1].to_double ()));
}
} else if (name == "TERNERY_FCN") {
if (params.size () < 3) {
return tl::Variant ();
} else {
return to_bool (params [0]) ? params [1] : params [2];
}
} else if (name == "MIN") {
if (params.size () < 1) {
return tl::Variant ();
}
tl::Variant v = params [0];
for (size_t i = 1; i < params.size (); ++i) {
if (params [i] < v) {
v = params [i];
}
}
return v;
} else if (name == "MAX") {
if (params.size () < 1) {
return tl::Variant ();
}
tl::Variant v = params [0];
for (size_t i = 1; i < params.size (); ++i) {
if (v < params [i]) {
v = params [i];
}
}
return v;
} else {
return tl::Variant ();
}
}
tl::Variant
NetlistSpiceReaderExpressionParser::read_atomic_value (tl::Extractor &ex, bool *status) const
{
double vd = 0.0;
std::string var;
if (ex.test ("-")) {
tl::Variant v = read_atomic_value (ex, status);
if (v.can_convert_to_double ()) {
return tl::Variant (-v.to_double ());
} else {
return tl::Variant ();
}
} else if (ex.test ("!")) {
tl::Variant v = read_atomic_value (ex, status);
return tl::Variant (! to_bool (v));
} else if (ex.test ("(")) {
tl::Variant v = read_tl_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (status) {
*status = ex.test (")");
} else {
ex.expect (")");
}
return v;
} else if (ex.try_read (vd)) {
if (status) {
*status = true;
}
double f = 1.0;
if (*ex == 't' || *ex == 'T') {
f = 1e12;
} else if (*ex == 'g' || *ex == 'G') {
f = 1e9;
} else if (*ex == 'k' || *ex == 'K') {
f = 1e3;
} else if (*ex == 'm' || *ex == 'M') {
f = 1e-3;
if (ex.test_without_case ("meg")) {
f = 1e6;
}
} else if (*ex == 'u' || *ex == 'U') {
f = 1e-6;
} else if (*ex == 'n' || *ex == 'N') {
f = 1e-9;
} else if (*ex == 'p' || *ex == 'P') {
f = 1e-12;
} else if (*ex == 'f' || *ex == 'F') {
f = 1e-15;
} else if (*ex == 'a' || *ex == 'A') {
f = 1e-18;
}
while (*ex && isalpha (*ex)) {
++ex;
}
vd *= f;
return tl::Variant (vd);
} else if (ex.try_read_word (var)) {
var = tl::to_upper_case (var);
if (ex.test ("(")) {
// a function
std::vector<tl::Variant> params;
if (! ex.test (")")) {
while (! ex.at_end ()) {
params.push_back (read_tl_expr (ex, status));
if (status && !*status) {
return tl::Variant ();
}
if (! ex.test (",")) {
break;
}
}
if (status && ! ex.test (")")) {
*status = false;
return tl::Variant ();
} else {
ex.expect (")");
}
}
return eval_func (var, params, status);
} else {
auto vi = mp_variables->find (var);
if (vi != mp_variables->end ()) {
return vi->second;
} else {
// keep word as string value
return tl::Variant (var);
}
}
} else {
if (status) {
*status = false;
} else {
throw tl::Exception (tl::sprintf (tl::to_string (tr ("Expected number of variable name here: '...%s'")), ex.get ()));
}
return tl::Variant ();
}
}
tl::Variant NetlistSpiceReaderExpressionParser::read_pwr_expr (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_atomic_value (ex, status);
if (status && !*status) {
return tl::Variant ();
}
while (true) {
if (ex.test ("**") || ex.test ("^")) {
tl::Variant vv = read_atomic_value (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = tl::Variant (pow (v.to_double (), vv.to_double ()));
}
} else {
break;
}
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_dot_expr (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_pwr_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
while (true) {
if (ex.test ("*")) {
tl::Variant vv = read_pwr_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = v.to_double () * vv.to_double ();
}
} else if (ex.test ("/")) {
tl::Variant vv = read_pwr_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = v.to_double () / vv.to_double ();
}
} else if (ex.test ("%")) {
tl::Variant vv = read_pwr_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = tl::Variant ((long int) v.to_double () % (long int) vv.to_double ());
}
} else {
break;
}
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_bar_expr (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_dot_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
while (true) {
if (ex.test ("+")) {
tl::Variant vv = read_dot_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = v.to_double () + vv.to_double ();
}
} else if (ex.test ("-")) {
tl::Variant vv = read_dot_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! v.can_convert_to_double () || ! vv.can_convert_to_double ()) {
v = tl::Variant ();
} else {
v = v.to_double () - vv.to_double ();
}
} else {
break;
}
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_compare_expr (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
while (true) {
if (ex.test ("==")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (v == vv);
} else if (ex.test ("!=")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (!(v == vv));
} else if (ex.test ("<=")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (v < vv || v == vv);
} else if (ex.test ("<")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (v < vv);
} else if (ex.test (">=")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (vv < v || v == vv);
} else if (ex.test (">")) {
tl::Variant vv = read_bar_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (vv < v);
} else {
break;
}
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_logical_op (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_compare_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
while (true) {
if (ex.test ("&&")) {
tl::Variant vv = read_compare_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (to_bool (v) && to_bool (vv));
} else if (ex.test ("||")) {
tl::Variant vv = read_compare_expr (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = tl::Variant (to_bool (v) || to_bool (vv));
} else {
break;
}
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_ternary_op (tl::Extractor &ex, bool *status) const
{
tl::Variant v = read_logical_op (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (ex.test ("?")) {
tl::Variant vv1 = read_logical_op (ex, status);
if (status && !*status) {
return tl::Variant ();
}
if (! ex.test (":")) {
if (status) {
*status = false;
} else {
ex.expect (":");
}
}
tl::Variant vv2 = read_logical_op (ex, status);
if (status && !*status) {
return tl::Variant ();
}
v = to_bool (v) ? vv1 : vv2;
}
return v;
}
tl::Variant NetlistSpiceReaderExpressionParser::read_tl_expr (tl::Extractor &ex, bool *status) const
{
return read_ternary_op (ex, status);
}
static const char *start_quote (tl::Extractor &ex)
{
if (ex.test ("'")) {
return "'";
} else if (ex.test ("\"")) {
return "\"";
} else if (ex.test ("{")) {
return "}";
} else {
return 0;
}
}
tl::Variant NetlistSpiceReaderExpressionParser::read (const std::string &s) const
{
tl::Extractor ex (s.c_str ());
return read (ex);
}
tl::Variant NetlistSpiceReaderExpressionParser::read (tl::Extractor &ex) const
{
tl::Variant res;
const char *endquote = start_quote (ex);
res = read_tl_expr (ex, 0);
if (endquote) {
ex.test (endquote);
}
return res;
}
bool NetlistSpiceReaderExpressionParser::try_read (const std::string &s, tl::Variant &value) const
{
tl::Extractor ex (s.c_str ());
return try_read (ex, value);
}
bool NetlistSpiceReaderExpressionParser::try_read (tl::Extractor &ex, tl::Variant &value) const
{
tl::Extractor ex_saved = ex;
bool status = false;
const char *endquote = start_quote (ex);
value = read_tl_expr (ex, &status);
if (endquote && ! ex.test (endquote)) {
status = false;
}
if (! status) {
value = tl::Variant ();
ex = ex_saved;
}
return status;
}
}

70
src/db/db/dbNetlistSpiceReaderExpressionParser.h Normal file
View File

@ -0,0 +1,70 @@
/*
KLayout Layout Viewer
Copyright (C) 2006-2023 Matthias Koefferlein
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef HDR_dbNetlistSpiceReaderExpressionParser
#define HDR_dbNetlistSpiceReaderExpressionParser
#include "dbCommon.h"
#include "tlStream.h"
#include "tlVariant.h"
#include "tlString.h"
#include <string>
#include <map>
#include <vector>
namespace db
{
/**
* @brief A class implementing the expression parser
*
* This class is exposed mainly for testing purposes.
*/
class DB_PUBLIC NetlistSpiceReaderExpressionParser
{
public:
typedef std::map<std::string, tl::Variant> variables_type;
NetlistSpiceReaderExpressionParser (const variables_type *vars);
tl::Variant read (tl::Extractor &ex) const;
tl::Variant read (const std::string &s) const;
bool try_read (tl::Extractor &ex, tl::Variant &v) const;
bool try_read (const std::string &s, tl::Variant &v) const;
private:
const variables_type *mp_variables;
tl::Variant read_atomic_value (tl::Extractor &ex, bool *status) const;
tl::Variant read_dot_expr (tl::Extractor &ex, bool *status) const;
tl::Variant read_bar_expr (tl::Extractor &ex, bool *status) const;
tl::Variant read_pwr_expr (tl::Extractor &ex, bool *status) const;
tl::Variant read_compare_expr (tl::Extractor &ex, bool *status) const;
tl::Variant read_logical_op (tl::Extractor &ex, bool *status) const;
tl::Variant read_ternary_op (tl::Extractor &ex, bool *status) const;
tl::Variant read_tl_expr (tl::Extractor &ex, bool *status) const;
tl::Variant eval_func (const std::string &name, const std::vector<tl::Variant> &params, bool *status) const;
};
}
#endif

13
src/db/db/dbNetlistSpiceWriter.cc
View File

@ -160,12 +160,21 @@ void NetlistSpiceWriterDelegate::write_device (const db::Device &dev) const
os << "M";
os << format_name (dev.expanded_name ());
os << format_terminals (dev);
// issue #1304
os << " ";
os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_D));
os << " ";
os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_G));
os << " ";
os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_S));
os << " ";
if (! mos4) {
// we assume for the MOS3 type the bulk is connected to Source
os << " ";
os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS3Transistor::terminal_id_S));
} else {
os << net_to_string (dev.net_for_terminal (db::DeviceClassMOS4Transistor::terminal_id_B));
}
// Use device class name for the model

94
src/db/db/gsiDeclDbNetlist.cc
View File

@ -26,6 +26,7 @@
#include "dbNetlistSpiceWriter.h"
#include "dbNetlistReader.h"
#include "dbNetlistSpiceReader.h"
#include "dbNetlistSpiceReaderDelegate.h"
#include "tlException.h"
#include "tlInternational.h"
#include "tlStream.h"
@ -2417,15 +2418,15 @@ public:
const std::vector<std::string> &net_names () const { return m_net_names; }
std::vector<std::string> &net_names_nc () { return m_net_names; }
void set_net_names (const std::vector<std::string> &nn) { m_net_names = nn; }
const std::map<std::string, double> &parameters () const { return m_parameters; }
std::map<std::string, double> &parameters_nc () { return m_parameters; }
void set_parameters (const std::map<std::string, double> &parameters) { m_parameters = parameters; }
const db::NetlistSpiceReader::parameters_type &parameters () const { return m_parameters; }
db::NetlistSpiceReader::parameters_type &parameters_nc () { return m_parameters; }
void set_parameters (const db::NetlistSpiceReader::parameters_type &parameters) { m_parameters = parameters; }
private:
std::string m_model;
double m_value;
std::vector<std::string> m_net_names;
std::map<std::string, double> m_parameters;
db::NetlistSpiceReader::parameters_type m_parameters;
};
/**
@ -2439,13 +2440,13 @@ public:
const std::vector<std::string> &strings () const { return m_strings; }
std::vector<std::string> &strings_nc () { return m_strings; }
void set_strings (const std::vector<std::string> &nn) { m_strings = nn; }
const std::map<std::string, double> &parameters () const { return m_parameters; }
std::map<std::string, double> &parameters_nc () { return m_parameters; }
void set_parameters (const std::map<std::string, double> &parameters) { m_parameters = parameters; }
const db::NetlistSpiceReader::parameters_type &parameters () const { return m_parameters; }
db::NetlistSpiceReader::parameters_type &parameters_nc () { return m_parameters; }
void set_parameters (const db::NetlistSpiceReader::parameters_type &parameters) { m_parameters = parameters; }
private:
std::vector<std::string> m_strings;
std::map<std::string, double> m_parameters;
db::NetlistSpiceReader::parameters_type m_parameters;
};
/**
@ -2456,7 +2457,7 @@ class NetlistSpiceReaderDelegateImpl
{
public:
NetlistSpiceReaderDelegateImpl ()
: db::NetlistSpiceReaderDelegate ()
: db::NetlistSpiceReaderDelegate (), mp_variables (0)
{
// .. nothing yet ..
}
@ -2566,15 +2567,16 @@ public:
ParseElementData parse_element_helper (const std::string &s, const std::string &element)
{
ParseElementData data;
db::NetlistSpiceReaderDelegate::parse_element (s, element, data.model_name_nc (), data.value_nc (), data.net_names_nc (), data.parameters_nc ());
db::NetlistSpiceReaderDelegate::parse_element (s, element, data.model_name_nc (), data.value_nc (), data.net_names_nc (), data.parameters_nc (), variables ());
return data;
}
virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector<std::string> &nn, std::map<std::string, double> &pv)
virtual void parse_element (const std::string &s, const std::string &element, std::string &model, double &value, std::vector<std::string> &nn, db::NetlistSpiceReader::parameters_type &pv, const db::NetlistSpiceReader::parameters_type &variables)
{
try {
m_error.clear ();
mp_variables = &variables;
ParseElementData data;
if (cb_parse_element.can_issue ()) {
@ -2588,21 +2590,27 @@ public:
nn = data.net_names ();
pv = data.parameters ();
mp_variables = 0;
} catch (tl::Exception &) {
mp_variables = 0;
if (! m_error.empty ()) {
db::NetlistSpiceReaderDelegate::error (m_error);
} else {
throw;
}
} catch (...) {
mp_variables = 0;
throw;
}
}
virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, double> &params)
virtual bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const db::NetlistSpiceReader::parameters_type &params)
{
try {
m_error.clear ();
if (cb_element.can_issue ()) {
return cb_element.issue<db::NetlistSpiceReaderDelegate, bool, db::Circuit *, const std::string &, const std::string &, const std::string &, double, const std::vector<db::Net *> &, const std::map<std::string, double> &> (&db::NetlistSpiceReaderDelegate::element, circuit, element, name, model, value, nets, params);
return cb_element.issue<db::NetlistSpiceReaderDelegate, bool, db::Circuit *, const std::string &, const std::string &, const std::string &, double, const std::vector<db::Net *> &, const db::NetlistSpiceReader::parameters_type &> (&db::NetlistSpiceReaderDelegate::element, circuit, element, name, model, value, nets, params);
} else {
return db::NetlistSpiceReaderDelegate::element (circuit, element, name, model, value, nets, params);
}
@ -2616,6 +2624,12 @@ public:
}
}
const db::NetlistSpiceReader::parameters_type &variables () const
{
static db::NetlistSpiceReader::parameters_type empty;
return mp_variables ? *mp_variables : empty;
}
gsi::Callback cb_start;
gsi::Callback cb_finish;
gsi::Callback cb_control_statement;
@ -2626,6 +2640,7 @@ public:
private:
std::string m_error;
const db::NetlistSpiceReader::parameters_type *mp_variables;
};
static void start_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Netlist *netlist)
@ -2653,7 +2668,7 @@ static std::string translate_net_name_fb (NetlistSpiceReaderDelegateImpl *delega
return delegate->db::NetlistSpiceReaderDelegate::translate_net_name (name);
}
static bool element_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, double> &params)
static bool element_fb (NetlistSpiceReaderDelegateImpl *delegate, db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const db::NetlistSpiceReader::parameters_type &params)
{
return delegate->db::NetlistSpiceReaderDelegate::element (circuit, element, name, model, value, nets, params);
}
@ -2663,41 +2678,43 @@ static ParseElementData parse_element_fb (NetlistSpiceReaderDelegateImpl *delega
return delegate->parse_element_helper (s, element);
}
static tl::Variant value_from_string (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s)
static tl::Variant value_from_string (NetlistSpiceReaderDelegateImpl * /*delegate*/, const std::string &s, const db::NetlistSpiceReader::parameters_type &variables)
{
tl::Variant res;
double v = 0.0;
if (delegate->try_read_value (s, v)) {
if (db::NetlistSpiceReaderDelegate::try_read_value (s, v, variables)) {
res = v;
}
return res;
}
static ParseElementComponentsData parse_element_components (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s)
static ParseElementComponentsData parse_element_components (NetlistSpiceReaderDelegateImpl *delegate, const std::string &s, const db::NetlistSpiceReader::parameters_type &variables)
{
ParseElementComponentsData data;
delegate->parse_element_components (s, data.strings_nc (), data.parameters_nc ());
delegate->parse_element_components (s, data.strings_nc (), data.parameters_nc (), variables);
return data;
}
Class<ParseElementComponentsData> db_ParseElementComponentsData ("db", "ParseElementComponentsData",
gsi::method ("strings", &ParseElementComponentsData::strings,
"@brief Gets the string parameters\n"
"@brief Gets the (unnamed) string parameters\n"
"These parameters are typically net names or model name."
) +
gsi::method ("strings=", &ParseElementComponentsData::set_strings, gsi::arg ("list"),
"@brief Sets the string parameters\n"
"@brief Sets the (unnamed) string parameters\n"
) +
gsi::method ("parameters", &ParseElementComponentsData::parameters,
"@brief Gets the (named) numerical parameters\n"
"@brief Gets the (named) parameters\n"
"Named parameters are typically (but not neccessarily) numerical, like 'w=0.15u'."
) +
gsi::method ("parameters=", &ParseElementComponentsData::set_parameters, gsi::arg ("dict"),
"@brief Sets the (named) numerical parameters\n"
"@brief Sets the (named) parameters\n"
),
"@brief Supplies the return value for \\NetlistSpiceReaderDelegate#parse_element_components.\n"
"This is a structure with two members: 'strings' for the string arguments and 'parameters' for the "
"named numerical arguments.\n"
"named arguments.\n"
"\n"
"This helper class has been introduced in version 0.27.1.\n"
"This helper class has been introduced in version 0.27.1. Starting with version 0.28.6, named parameters can be string types too.\n"
);
Class<ParseElementData> db_ParseElementData ("db", "ParseElementData",
@ -2720,16 +2737,16 @@ Class<ParseElementData> db_ParseElementData ("db", "ParseElementData",
"@brief Sets the net names\n"
) +
gsi::method ("parameters", &ParseElementData::parameters,
"@brief Gets the (named) numerical parameters\n"
"@brief Gets the (named) parameters\n"
) +
gsi::method ("parameters=", &ParseElementData::set_parameters, gsi::arg ("dict"),
"@brief Sets the (named) numerical parameters\n"
"@brief Sets the (named) parameters\n"
),
"@brief Supplies the return value for \\NetlistSpiceReaderDelegate#parse_element.\n"
"This is a structure with four members: 'model_name' for the model name, 'value' for the default numerical value, 'net_names' for the net names and 'parameters' for the "
"named numerical parameters.\n"
"named parameters.\n"
"\n"
"This helper class has been introduced in version 0.27.1.\n"
"This helper class has been introduced in version 0.27.1. Starting with version 0.28.6, named parameters can be string types too.\n"
);
Class<NetlistSpiceReaderDelegateImpl> db_NetlistSpiceReaderDelegate ("db", "NetlistSpiceReaderDelegate",
@ -2765,6 +2782,13 @@ Class<NetlistSpiceReaderDelegateImpl> db_NetlistSpiceReaderDelegate ("db", "Netl
"\n"
"This method has been introduced in version 0.27.1\n"
) +
gsi::method ("variables", &NetlistSpiceReaderDelegateImpl::variables,
"@brief Gets the variables defined inside the SPICE file during execution of 'parse_element'\n"
"In order to evaluate formulas, this method allows accessing the variables that are "
"present during the execution of the SPICE reader.\n"
"\n"
"This method has been introduced in version 0.28.6."
) +
gsi::callback ("parse_element", &NetlistSpiceReaderDelegateImpl::parse_element_helper, &NetlistSpiceReaderDelegateImpl::cb_parse_element,
gsi::arg ("s"), gsi::arg ("element"),
"@brief Parses an element card\n"
@ -2795,27 +2819,33 @@ Class<NetlistSpiceReaderDelegateImpl> db_NetlistSpiceReaderDelegate ("db", "Netl
"some known elements using the Spice writer's parameter conventions.\n"
"\n"
"The method must return true, if the element was was understood and false otherwise.\n"
"\n"
"Starting with version 0.28.6, the parameter values can be strings too."
) +
gsi::method ("error", &NetlistSpiceReaderDelegateImpl::error, gsi::arg ("msg"),
"@brief Issues an error with the given message.\n"
"Use this method to generate an error."
) +
gsi::method_ext ("value_from_string", &value_from_string, gsi::arg ("s"),
gsi::method_ext ("value_from_string", &value_from_string, gsi::arg ("s"), gsi::arg ("variables", db::NetlistSpiceReader::parameters_type (), "{}"),
"@brief Translates a string into a value\n"
"This function simplifies the implementation of SPICE readers by providing a translation of a unit-annotated string "
"into double values. For example, '1k' is translated to 1000.0. In addition, simple formula evaluation is supported, e.g "
"'(1+3)*2' is translated into 8.0.\n"
"\n"
"This method has been introduced in version 0.27.1\n"
"The variables dictionary defines named variables with the given values.\n"
"\n"
"This method has been introduced in version 0.27.1. The variables argument has been added in version 0.28.6.\n"
) +
gsi::method_ext ("parse_element_components", &parse_element_components, gsi::arg ("s"),
gsi::method_ext ("parse_element_components", &parse_element_components, gsi::arg ("s"), gsi::arg ("variables", db::NetlistSpiceReader::parameters_type (), "{}"),
"@brief Parses a string into string and parameter components.\n"
"This method is provided to simplify the implementation of 'parse_element'. It takes a string and splits it into "
"string arguments and parameter values. For example, 'a b c=6' renders two string arguments in 'nn' and one parameter ('C'->6.0). "
"It returns data \\ParseElementComponentsData object with the strings and parameters.\n"
"The parameter names are already translated to upper case.\n"
"\n"
"This method has been introduced in version 0.27.1\n"
"The variables dictionary defines named variables with the given values.\n"
"\n"
"This method has been introduced in version 0.27.1. The variables argument has been added in version 0.28.6.\n"
),
"@brief Provides a delegate for the SPICE reader for translating device statements\n"
"Supply a customized class to provide a specialized reading scheme for devices. "

281
src/db/unit_tests/dbNetlistReaderTests.cc
View File

@ -21,6 +21,8 @@
*/
#include "dbNetlistSpiceReader.h"
#include "dbNetlistSpiceReaderDelegate.h"
#include "dbNetlistSpiceReaderExpressionParser.h"
#include "dbNetlist.h"
#include "dbNetlistDeviceClasses.h"
@ -167,33 +169,49 @@ TEST(4_ReaderWithUnconnectedPins)
" subcircuit INV2 $2 ('1'='7','2'='4','3'='6','4'='3','5'='2','6'='1');\n"
"end;\n"
"circuit INV2 ('1'='1','2'='2','3'='3','4'='4','5'='5','6'='6');\n"
" device PMOS $1 (S='3',G='2',D='5',B='1') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n"
" device NMOS $3 (S='3',G='2',D='4',B='6') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n"
" device PMOS $1 (S='5',G='2',D='3',B='1') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n"
" device NMOS $3 (S='4',G='2',D='3',B='6') (L=0.25,W=3.5,AS=1.4,AD=1.4,PS=6.85,PD=6.85);\n"
"end;\n"
);
}
TEST(5_CircuitParameters)
{
db::Netlist nl;
std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader5.cir");
db::NetlistSpiceReader reader;
reader.set_strict (true);
try {
db::Netlist nl;
tl::InputStream is (path);
reader.read (is, nl);
// strict mode makes this sample fail
EXPECT_EQ (true, false);
} catch (...) {
// ..
}
db::Netlist nl;
reader.set_strict (false);
tl::InputStream is (path);
reader.read (is, nl);
EXPECT_EQ (nl.to_string (),
"circuit SUBCKT ($1=$1,'A[5]<1>'='A[5]<1>','V42(%)'='V42(%)',Z=Z,GND=GND,GND$1=GND$1);\n"
" subcircuit HVPMOS D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n"
" subcircuit HVPMOS D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n"
" subcircuit HVNMOS D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n"
" subcircuit HVNMOS D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n"
" subcircuit HVNMOS D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n"
" subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n"
" subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n"
" subcircuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n"
" subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n"
" subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n"
"end;\n"
"circuit HVPMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n"
"circuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit HVNMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n"
"circuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
);
}
@ -209,7 +227,7 @@ public:
return circuit_name == "HVNMOS" || circuit_name == "HVPMOS";
}
bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, double> &params)
bool element (db::Circuit *circuit, const std::string &element, const std::string &name, const std::string &model, double value, const std::vector<db::Net *> &nets, const std::map<std::string, tl::Variant> &params)
{
if (element == "X") {
@ -235,9 +253,9 @@ public:
const std::vector<db::DeviceParameterDefinition> &td = cls->parameter_definitions ();
for (std::vector<db::DeviceParameterDefinition>::const_iterator i = td.begin (); i != td.end (); ++i) {
std::map<std::string, double>::const_iterator pi = params.find (i->name ());
auto pi = params.find (i->name ());
if (pi != params.end ()) {
device->set_parameter_value (i->id (), pi->second * 1.5);
device->set_parameter_value (i->id (), pi->second.to_double () * 1.5);
}
}
@ -262,6 +280,9 @@ TEST(6_ReaderWithDelegate)
reader.read (is, nl);
EXPECT_EQ (nl.to_string (),
"circuit .TOP ();\n"
" subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);\n"
"end;\n"
"circuit SUBCKT ($1=$1,A=A,VDD=VDD,Z=Z,GND=GND,GND$1=GND$1);\n"
" device HVPMOS $1 (S=VDD,G=$3,D=Z,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
" device HVPMOS $2 (S=VDD,G=A,D=$3,B=$1) (L=0.3,W=1.5,AS=0.27,AD=0.27,PS=3.24,PD=3.24);\n"
@ -270,9 +291,6 @@ TEST(6_ReaderWithDelegate)
" device HVNMOS $5 (S=GND,G=A,D=$3,B=GND$1) (L=0.6,W=0.6,AS=0.285,AD=0.285,PS=2.64,PD=2.64);\n"
" device RES $1 (A=A,B=Z) (R=100000,L=0,W=0,A=0,P=0);\n"
"end;\n"
"circuit .TOP ();\n"
" subcircuit SUBCKT SUBCKT ($1=IN,A=OUT,VDD=VDD,Z=Z,GND=VSS,GND$1=VSS);\n"
"end;\n"
);
}
@ -378,8 +396,8 @@ TEST(9_DeviceMultipliers)
" device RMODEL2 $6 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device RMODEL2 $7 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device RES3 $8 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device NMOS $1 (S='1',G='2',D='3',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $2 (S='1',G='2',D='3',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $1 (S='3',G='2',D='1',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $2 (S='3',G='2',D='1',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n"
" device CAP $1 (A='1',B='2') (C=2e-09,A=0,P=0);\n"
" device CAP $2 (A='3',B='4') (C=1e-09,A=0,P=0);\n"
" device CMODEL $3 (A='1',B='2') (C=2e-09,A=0,P=0);\n"
@ -423,8 +441,8 @@ TEST(9_DeviceMultipliers)
" device RMODEL2 $6 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device RMODEL2 $7 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device RES3 $8 (A='3',B='4',W='5') (R=1700,L=0,W=0,A=0,P=0);\n"
" device NMOS $1 (S='1',G='2',D='3',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $2 (S='1',G='2',D='3',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $1 (S='3',G='2',D='1',B='4') (L=7,W=4,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $2 (S='3',G='2',D='1',B='4') (L=7,W=2,AS=0,AD=0,PS=0,PD=0);\n"
" device CAP $1 (A='1',B='2') (C=2e-09,A=0,P=0);\n"
" device CAP $2 (A='3',B='4') (C=1e-09,A=0,P=0);\n"
" device CMODEL $3 (A='1',B='2') (C=2e-09,A=0,P=0);\n"
@ -527,16 +545,16 @@ TEST(13_NoGlobalNetsIfNotUsed)
" subcircuit C3 '3' (VDD=VDD,GND=GND);\n"
" subcircuit C4 '4' (VDD=VDD,GND=GND);\n"
"end;\n"
"circuit C1 (VDD=VDD,GND=GND);\n"
" subcircuit FILLER_CAP '1' (VDD=VDD,GND=GND);\n"
" subcircuit DUMMY '2' ();\n"
"end;\n"
"circuit FILLER_CAP (VDD=VDD,GND=GND);\n"
" device NMOS '1' (S=GND,G=VDD,D=GND,B=GND) (L=10,W=10,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
"circuit DUMMY ();\n"
" device NMOS '1' (S=A,G=A,D=A,B=B) (L=1,W=1,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
"circuit C1 (VDD=VDD,GND=GND);\n"
" subcircuit FILLER_CAP '1' (VDD=VDD,GND=GND);\n"
" subcircuit DUMMY '2' ();\n"
"end;\n"
"circuit C2 ();\n"
" subcircuit DUMMY '1' ();\n"
"end;\n"
@ -578,15 +596,19 @@ TEST(15_ContinuationWithBlanks)
EXPECT_EQ (nl.to_string (),
"circuit SUBCKT ($1=$1,'A[5]<1>'='A[5]<1>','V42(%)'='V42(%)',Z=Z,GND=GND,GND$1=GND$1);\n"
" subcircuit HVPMOS D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n"
" subcircuit HVPMOS D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n"
" subcircuit HVNMOS D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n"
" subcircuit HVNMOS D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n"
" subcircuit HVNMOS D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n"
" subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$1 ($1='V42(%)',$2=$3,$3=Z,$4=$1);\n"
" subcircuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' D_$2 ($1='V42(%)',$2='A[5]<1>',$3=$3,$4=$1);\n"
" subcircuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' D_$3 ($1=GND,$2=$3,$3=GND,$4=GND$1);\n"
" subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' D_$4 ($1=GND,$2=$3,$3=Z,$4=GND$1);\n"
" subcircuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' D_$5 ($1=GND,$2='A[5]<1>',$3=$3,$4=GND$1);\n"
"end;\n"
"circuit HVPMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n"
"circuit 'HVPMOS(AD=0.18,AS=0.18,L=0.2,PD=2.16,PS=2.16,W=1)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit HVNMOS ($1=(null),$2=(null),$3=(null),$4=(null));\n"
"circuit 'HVNMOS(AD=0,AS=0,L=1.13,PD=6,PS=6,W=2.12)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.16,PS=1.16,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
"circuit 'HVNMOS(AD=0.19,AS=0.19,L=0.4,PD=1.76,PS=1.76,W=0.4)' ($1=$0,$2=$0,$3=$0,$4=$0);\n"
"end;\n"
);
}
@ -611,3 +633,198 @@ TEST(16_issue898)
"end;\n"
);
}
TEST(17_RecursiveExpansion)
{
db::Netlist nl, nl2;
{
std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader17.cir");
db::NetlistSpiceReader reader;
tl::InputStream is (path);
reader.read (is, nl);
}
EXPECT_EQ (nl.to_string (),
"circuit .TOP ();\n"
" subcircuit 'SUB1(L=0.15,W=1.5)' SUB1A (N1=A,N2=B,N3=C);\n"
" subcircuit 'SUB1(L=0.25,W=3)' SUB1B (N1=A,N2=B,N3=C);\n"
"end;\n"
"circuit 'SUB1(L=0.15,W=1.5)' (N1=N1,N2=N2,N3=N3);\n"
" subcircuit 'SUB2(L=0.15,M=1,W=1.5)' SUB2A (N1=N1,N2=N2,N3=N3);\n"
" subcircuit 'SUB2(L=0.15,M=2,W=1.5)' SUB2B (N1=N1,N2=N2,N3=N3);\n"
"end;\n"
"circuit 'SUB2(L=0.15,M=1,W=1.5)' (N1=N1,N2=N2,N3=N3);\n"
" device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=150000,W=1500000,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
"circuit 'SUB2(L=0.15,M=2,W=1.5)' (N1=N1,N2=N2,N3=N3);\n"
" device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=150000,W=3000000,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
"circuit 'SUB1(L=0.25,W=3)' (N1=N1,N2=N2,N3=N3);\n"
" subcircuit 'SUB2(L=0.25,M=1,W=3)' SUB2A (N1=N1,N2=N2,N3=N3);\n"
" subcircuit 'SUB2(L=0.25,M=2,W=3)' SUB2B (N1=N1,N2=N2,N3=N3);\n"
"end;\n"
"circuit 'SUB2(L=0.25,M=1,W=3)' (N1=N1,N2=N2,N3=N3);\n"
" device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=250000,W=3000000,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
"circuit 'SUB2(L=0.25,M=2,W=3)' (N1=N1,N2=N2,N3=N3);\n"
" device NMOS NMOS (S=N3,G=N2,D=N1,B=N1) (L=250000,W=6000000,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
);
{
std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader17b.cir");
db::NetlistSpiceReader reader;
tl::InputStream is (path);
reader.read (is, nl2);
}
EXPECT_EQ (nl2.to_string (), nl.to_string ());
}
TEST(18_XSchemOutput)
{
db::Netlist nl;
std::string path = tl::combine_path (tl::combine_path (tl::testdata (), "algo"), "nreader18.cir");
db::NetlistSpiceReader reader;
tl::InputStream is (path);
reader.read (is, nl);
EXPECT_EQ (nl.to_string (),
"circuit .TOP ();\n"
" subcircuit 'PMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' XPMOS (D=Q,G=I,S=VDD,B=VDD);\n"
" subcircuit 'NMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' XNMOS (D=Q,G=I,S=VSS,B=VSS);\n"
" subcircuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY0 (D=VSS,G=VSS,S=VSS,B=VSS);\n"
" subcircuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY1 (D=VSS,G=VSS,S=VSS,B=VSS);\n"
" subcircuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY2 (D=VDD,G=VDD,S=VDD,B=VDD);\n"
" subcircuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' XDUMMY3 (D=VDD,G=VDD,S=VDD,B=VDD);\n"
"end;\n"
"circuit 'PMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' (D=D,G=G,S=S,B=B);\n"
" device SKY130_FD_PR__PFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=6,AS=0.32625,AD=0.2175,PS=2.685,PD=1.79);\n"
"end;\n"
"circuit 'NMOS4_STANDARD(L=0.15U,NF=4,W=1.5U)' (D=D,G=G,S=S,B=B);\n"
" device SKY130_FD_PR__NFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=6,AS=0.32625,AD=0.2175,PS=2.685,PD=1.79);\n"
"end;\n"
"circuit 'NMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' (D=D,G=G,S=S,B=B);\n"
" device SKY130_FD_PR__NFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=3,AS=0.435,AD=0.2175,PS=3.58,PD=1.79);\n"
"end;\n"
"circuit 'PMOS4_STANDARD(L=0.15U,NF=2,W=1.5U)' (D=D,G=G,S=S,B=B);\n"
" device SKY130_FD_PR__PFET_01V8 M1 (S=S,G=G,D=D,B=B) (L=0.15,W=3,AS=0.435,AD=0.2175,PS=3.58,PD=1.79);\n"
"end;\n"
);
}
TEST(100_ExpressionParser)
{
std::map<std::string, tl::Variant> vars;
vars["A"] = 17.5;
vars["B"] = 42;
vars["S"] = "string";
tl::Variant v;
db::NetlistSpiceReaderExpressionParser parser (&vars);
EXPECT_EQ (parser.read ("1.75").to_string (), "1.75");
EXPECT_EQ (parser.read ("-1.75").to_string (), "-1.75");
EXPECT_EQ (parser.read ("-a*0.1").to_string (), "-1.75");
EXPECT_EQ (parser.read ("-A*0.1").to_string (), "-1.75");
EXPECT_EQ (parser.read ("b/6").to_string (), "7");
EXPECT_EQ (parser.read ("B/6").to_string (), "7");
EXPECT_EQ (parser.read ("s").to_string (), "string");
EXPECT_EQ (parser.read ("S").to_string (), "string");
EXPECT_EQ (parser.read ("!0").to_string (), "true");
EXPECT_EQ (parser.read ("!1").to_string (), "false");
EXPECT_EQ (parser.read ("4*2+1").to_string (), "9");
EXPECT_EQ (parser.read ("4*2-1").to_string (), "7");
EXPECT_EQ (parser.read ("4/2-1").to_string (), "1");
EXPECT_EQ (parser.read ("4%2-1").to_string (), "-1");
EXPECT_EQ (parser.read ("5%2-1").to_string (), "0");
EXPECT_EQ (parser.read ("2**2*2+1").to_string (), "9");
EXPECT_EQ (parser.read ("2**2*(2+1)").to_string (), "12");
EXPECT_EQ (parser.read ("pow(2,2)*(2+1)").to_string (), "12");
EXPECT_EQ (parser.read ("POW(2,2)*(2+1)").to_string (), "12");
EXPECT_EQ (parser.read ("pwr(2,2)*(2+1)").to_string (), "12");
EXPECT_EQ (parser.read ("PWR(2,2)*(2+1)").to_string (), "12");
EXPECT_EQ (parser.read ("3==2+1").to_string (), "true");
EXPECT_EQ (parser.read ("4==2+1").to_string (), "false");
EXPECT_EQ (parser.read ("3!=2+1").to_string (), "false");
EXPECT_EQ (parser.read ("4!=2+1").to_string (), "true");
EXPECT_EQ (parser.read ("2<2+1").to_string (), "true");
EXPECT_EQ (parser.read ("3<2+1").to_string (), "false");
EXPECT_EQ (parser.read ("4<2+1").to_string (), "false");
EXPECT_EQ (parser.read ("2<=2+1").to_string (), "true");
EXPECT_EQ (parser.read ("3<=2+1").to_string (), "true");
EXPECT_EQ (parser.read ("4<=2+1").to_string (), "false");
EXPECT_EQ (parser.read ("2>2+1").to_string (), "false");
EXPECT_EQ (parser.read ("3>2+1").to_string (), "false");
EXPECT_EQ (parser.read ("4>2+1").to_string (), "true");
EXPECT_EQ (parser.read ("2>=2+1").to_string (), "false");
EXPECT_EQ (parser.read ("3>=2+1").to_string (), "true");
EXPECT_EQ (parser.read ("4>=2+1").to_string (), "true");
EXPECT_EQ (parser.read ("1==2||2==2").to_string (), "true");
EXPECT_EQ (parser.read ("1==2||3==2").to_string (), "false");
EXPECT_EQ (parser.read ("1==2&&2==2").to_string (), "false");
EXPECT_EQ (parser.read ("1==1&&2==2").to_string (), "true");
EXPECT_EQ (parser.read ("1==2?2:3").to_string (), "3");
EXPECT_EQ (parser.read ("ternery_fcn(1==2,2,3)").to_string (), "3");
EXPECT_EQ (parser.read ("1==1?2:3").to_string (), "2");
EXPECT_EQ (parser.read ("ternery_fcn(1==1,2,3)").to_string (), "2");
EXPECT_EQ (parser.read ("sin(0)").to_string (), "0");
EXPECT_EQ (parser.read ("sin(atan(1.0)*2)").to_string (), "1");
EXPECT_EQ (parser.read ("cos(0)").to_string (), "1");
EXPECT_EQ (parser.read ("cos(atan(1.0)*2)").to_string (), "0");
EXPECT_EQ (parser.read ("tan(0)").to_string (), "0");
EXPECT_EQ (parser.read ("tan(atan(1.0))").to_string (), "1");
EXPECT_EQ (parser.read ("sin(asin(0.5))").to_string (), "0.5");
EXPECT_EQ (parser.read ("cos(acos(0.5))").to_string (), "0.5");
EXPECT_EQ (parser.read ("ln(exp(0.5))").to_string (), "0.5");
EXPECT_EQ (parser.read ("exp(0.0)").to_string (), "1");
EXPECT_EQ (parser.read ("log(10**0.5)").to_string (), "0.5");
EXPECT_EQ (parser.read ("int(-0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("int(-1.5)").to_string (), "-1");
EXPECT_EQ (parser.read ("int(0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("int(1.5)").to_string (), "1");
EXPECT_EQ (parser.read ("floor(-0.5)").to_string (), "-1");
EXPECT_EQ (parser.read ("floor(-1.5)").to_string (), "-2");
EXPECT_EQ (parser.read ("floor(0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("floor(1.5)").to_string (), "1");
EXPECT_EQ (parser.read ("ceil(-0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("ceil(-1.5)").to_string (), "-1");
EXPECT_EQ (parser.read ("ceil(0.5)").to_string (), "1");
EXPECT_EQ (parser.read ("ceil(1.5)").to_string (), "2");
EXPECT_EQ (parser.read ("nint(-0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("nint(-1.5)").to_string (), "-2");
EXPECT_EQ (parser.read ("nint(0.5)").to_string (), "0");
EXPECT_EQ (parser.read ("nint(1.5)").to_string (), "2");
EXPECT_EQ (parser.read ("min(4,1,3)").to_string (), "1");
EXPECT_EQ (parser.read ("min(4,3)").to_string (), "3");
EXPECT_EQ (parser.read ("min(4)").to_string (), "4");
EXPECT_EQ (parser.read ("max(1,4,3)").to_string (), "4");
EXPECT_EQ (parser.read ("max(4,3)").to_string (), "4");
EXPECT_EQ (parser.read ("max(4)").to_string (), "4");
EXPECT_EQ (parser.read ("max(a,b)").to_string (), "42");
EXPECT_EQ (parser.try_read ("a syntax error", v), false);
v = tl::Variant ();
EXPECT_EQ (parser.try_read ("1+2*(2+1)-1", v), true);
EXPECT_EQ (v.to_string (), "6");
EXPECT_EQ (parser.try_read ("{1+2*(2+1)-1)", v), false);
EXPECT_EQ (parser.try_read ("'1+2*(2+1)-1)", v), false);
EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1)", v), false);
EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1'", v), false);
v = tl::Variant ();
EXPECT_EQ (parser.try_read ("{1+2*(2+1)-1}", v), true);
EXPECT_EQ (v.to_string (), "6");
v = tl::Variant ();
EXPECT_EQ (parser.try_read ("'1+2*(2+1)-1'", v), true);
EXPECT_EQ (v.to_string (), "6");
v = tl::Variant ();
EXPECT_EQ (parser.try_read ("\"1+2*(2+1)-1\"", v), true);
EXPECT_EQ (v.to_string (), "6");
}

1
src/lvs/unit_tests/lvsSimpleTests.cc
View File

@ -159,6 +159,7 @@ TEST(11_device_scaling)
TEST(12_simple_dmos)
{
run_test (_this, "ringo_simple_dmos", "ringo.gds");
run_test (_this, "ringo_simple_dmos_fixed", "ringo_fixed_sources.gds");
}
TEST(13_simple_ringo_device_subcircuits)

6
src/lvs/unit_tests/lvsTests.cc
View File

@ -142,7 +142,7 @@ TEST(16_private)
TEST(17_private)
{
test_is_long_runner ();
run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_3.lvsdb");
run_test (_this, "test_17.lylvs", "test_17b.cir.gz", "test_17.gds.gz", true, "test_17b_4.lvsdb");
}
TEST(18_private)
@ -160,12 +160,12 @@ TEST(19_private)
TEST(20_private)
{
// test_is_long_runner ();
run_test (_this, "test_20.lylvs", "test_20.cir.gz", "test_20.gds.gz", true, "test_20b_3.lvsdb");
run_test (_this, "test_20.lylvs", "test_20.cir.gz", "test_20.gds.gz", true, "test_20_4.lvsdb");
}
TEST(21_private)
{
run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21.lvsdb");
run_test (_this, "test_21.lylvs", "test_21.cir.gz", "test_21.gds.gz", true, "test_21_2.lvsdb");
}
// issue #1021

17
src/tl/tl/tlVariant.cc
View File

@ -27,6 +27,7 @@
#include <string.h>
#include <limits>
#include <cmath>
#if defined(HAVE_QT)
@ -1054,6 +1055,18 @@ normalized_type (Variant::type type1, Variant::type type2)
}
}
static const double epsilon = 1e-13;
static inline bool fequal (double a, double b)
{
double avg = 0.5 * (fabs (a) + fabs (b));
return fabs (a - b) <= epsilon * avg;
}
static inline bool fless (double a, double b)
{
return fequal (a, b) ? false : a < b;
}
bool
Variant::operator== (const tl::Variant &d) const
@ -1083,7 +1096,7 @@ Variant::operator== (const tl::Variant &d) const
} else if (t == t_id) {
return m_var.m_id == d.m_var.m_id;
} else if (t == t_double) {
return to_double () == d.to_double ();
return fequal (to_double (), d.to_double ());
} else if (t == t_string) {
return strcmp (to_string (), d.to_string ()) == 0;
} else if (t == t_bytearray) {
@ -1139,7 +1152,7 @@ Variant::operator< (const tl::Variant &d) const
} else if (t == t_id) {
return m_var.m_id < d.m_var.m_id;
} else if (t == t_double) {
return to_double () < d.to_double ();
return fless (to_double (), d.to_double ());
} else if (t == t_string) {
return strcmp (to_string (), d.to_string ()) < 0;
} else if (t == t_bytearray) {

32
src/tl/unit_tests/tlVariantTests.cc
View File

@ -1059,7 +1059,35 @@ TEST(5)
EXPECT_EQ (m [" 3"], 0);
}
// fuzzy compare of doubles
TEST(6)
{
volatile double a = 10.0;
EXPECT_EQ (tl::Variant (0.0) == tl::Variant (0.0), true);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (1.0 / a), true);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1e-14)), true);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 0.9e-13)), true);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1.1e-13)), false);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (0.1 * (1.0 + 1e-12)), false);
EXPECT_EQ (tl::Variant (-0.1) == tl::Variant (-0.1 * (1.0 + 0.9e-13)), true);
EXPECT_EQ (tl::Variant (-0.1) == tl::Variant (-0.1 * (1.0 + 1.1e-13)), false);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (-0.1 * (1.0 + 0.9e-13)), false);
EXPECT_EQ (tl::Variant (0.1) == tl::Variant (-0.1 * (1.0 + 1.1e-13)), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (1.0 / a), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1e-14)), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 0.9e-13)), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1.1e-13)), true);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (0.1 * (1.0 + 1e-12)), true);
EXPECT_EQ (tl::Variant (-0.1) < tl::Variant (-0.1 * (1.0 + 0.9e-13)), false);
EXPECT_EQ (tl::Variant (-0.1) < tl::Variant (-0.1 * (1.0 + 1.1e-13)), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (-0.1 * (1.0 + 0.9e-13)), false);
EXPECT_EQ (tl::Variant (0.1) < tl::Variant (-0.1 * (1.0 + 1.1e-13)), false);
EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 0.9e-13)) < tl::Variant (-0.1), false);
EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 1.1e-13)) < tl::Variant (-0.1), true);
EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 0.9e-13)) < tl::Variant (0.1), true);
EXPECT_EQ (tl::Variant (-0.1 * (1.0 + 1.1e-13)) < tl::Variant (0.1), true);
}
}

8
testdata/algo/lvs_test1_au.lvsdb.1 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)

8
testdata/algo/lvs_test1_au.lvsdb.2 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)

8
testdata/algo/lvs_test1b_au.lvsdb.1 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)

8
testdata/algo/lvs_test1b_au.lvsdb.2 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)

70
testdata/algo/lvs_test2_au.lvsdb.1 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference

70
testdata/algo/lvs_test2_au.lvsdb.2 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference

70
testdata/algo/lvs_test2b_au.lvsdb.1 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference

70
testdata/algo/lvs_test2b_au.lvsdb.2 vendored
View File

@ -447,9 +447,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 5)
terminal(G 2)
terminal(D 5)
terminal(D 3)
terminal(B 1)
)
device(2 NMOS
@ -460,9 +460,9 @@ reference(
param(AD 1.4)
param(PS 6.85)
param(PD 6.85)
terminal(S 3)
terminal(S 4)
terminal(G 2)
terminal(D 4)
terminal(D 3)
terminal(B 6)
)
@ -497,6 +497,37 @@ reference(
pin(5 1)
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
circuit(RINGO
@ -567,37 +598,6 @@ reference(
)
)
circuit(INV2PAIRX
# Nets
net(1 name('1'))
net(2 name('2'))
net(3 name('3'))
net(4 name('4'))
net(5 name('5'))
net(6 name('6'))
net(7 name('7'))
# Outgoing pins and their connections to nets
pin(1 name('1'))
pin(2 name('2'))
pin(3 name('3'))
pin(4 name('4'))
pin(5 name('5'))
pin(6 name('6'))
pin(7 name('7'))
# Subcircuits and their connections
circuit(1 INV2 name($2)
pin(0 7)
pin(1 4)
pin(2 6)
pin(3 3)
pin(4 2)
pin(5 1)
)
)
)
# Cross reference

2
testdata/algo/nreader1.cir vendored
View File

@ -13,5 +13,5 @@ R$2 3 1 7650
* device instance $3 4.665,0.335 RES
R$3 3 2 2670
* device instance $4 1.765,7.485 HVPMOS
M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
.ENDS TOP

15
testdata/algo/nreader17.cir vendored Normal file
View File

@ -0,0 +1,15 @@
* recursive expansion of parametrized subcircuits
Xsub1a a b c sub1 w=1.5 l=0.15
Xsub1b a b c sub1 w=3.0 l=0.25
.subckt sub1 n1 n2 n3 w=1.0 l=0.5
Xsub2a n1 n2 n3 sub2 w l m=1
Xsub2b n1 n2 n3 sub2 w l m=2
.ends
.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0
Mnmos n1 n2 n3 n1 nmos w=w l=l m=m
.ends

24
testdata/algo/nreader17b.cir vendored Normal file
View File

@ -0,0 +1,24 @@
* recursive expansion of parametrized subcircuits
.param w1 1.5 w2 {w1*2}
.param l1 0.15 l2 'l1+0.1'
Xsub1a a b c sub1 w=w1 l=l1
Xsub1b a b c sub1 w=w2 l=l2
.subckt sub1 n1 n2 n3 w l
* declares w and l parameters instead of nodes:
w = 1.0
l = 1.0
.param w1 = w
.param l1 = l
Xsub2a n1 n2 n3 sub2 w=w1 l=l1 m=1
.param w2 "w+0.0" l2 l*(0.5+0.5)
Xsub2b n1 n2 n3 sub2 w=w2 l=l2 m=2
.ends
.subckt sub2 n1 n2 n3 w=0.0 l=0.0 m=0
Mnmos n1 n2 n3 n1 nmos w=w l=l m=m
.ends

59
testdata/algo/nreader18.cir vendored Normal file
View File

@ -0,0 +1,59 @@
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/inverter1_generated_sky130_fd_pr/inverter1/inverter1.sch
**.subckt inverter1 I Q VDD VSS
*.ipin I
*.opin Q
*.iopin VDD
*.iopin VSS
XXpmos Q I VDD VDD pmos4_standard w=1.5u l=150n nf=4
XXnmos Q I VSS VSS nmos4_standard w=1.5u l=150n nf=4
XXDUMMY0 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2
XXDUMMY1 VSS VSS VSS VSS nmos4_standard w=1.5u l=150n nf=2
XXDUMMY2 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2
XXDUMMY3 VDD VDD VDD VDD pmos4_standard w=1.5u l=150n nf=2
**.ends
* expanding symbol: BAG_prim/pmos4_standard/pmos4_standard.sym # of pins=4
** sym_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sym
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/pmos4_standard/pmos4_standard.sch
.subckt pmos4_standard D G S B model w l nf
w=100n
l=18n
nf=4
model=pmos4_standard
spiceprefix=X
*.iopin D
*.iopin G
*.iopin S
*.iopin B
MM1 D G S B sky130_fd_pr__pfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u'
+ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W'
+ sa=0 sb=0 sd=0 mult=1 m=nf
.ends
* expanding symbol: BAG_prim/nmos4_standard/nmos4_standard.sym # of pins=4
** sym_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sym
** sch_path:
*+ /home/matthias/dev/bag/mosaic_bag/opensource_db_template/BAG2_technology_definition/BAG_prim/nmos4_standard/nmos4_standard.sch
.subckt nmos4_standard D G S B model w l nf
w=100n
l=18n
nf=4
model=nmos4_standard
spiceprefix=X
*.iopin D
*.iopin G
*.iopin S
*.iopin B
MM1 D G S B sky130_fd_pr__nfet_01v8 L=l W=w ad='int((nf+1)/2) * W/nf * 0.29u' as='int((nf+2)/2) * W/nf * 0.29u'
+ pd='2*int((nf+1)/2) * (W + 0.29u)/nf' ps='2*int((nf+2)/2) * (W + 0.29u)/nf' nrd='0.29u / W' nrs='0.29u / W'
+ sa=0 sb=0 sd=0 mult=1 m=nf
.ends
.end

2
testdata/algo/nreader1b.cir vendored
View File

@ -13,5 +13,5 @@ R$2 3 1 7650 M2
* device instance $3 4.665,0.335 RES, model M3
R$3 3 2 2670 M3
* device instance $4 1.765,7.485 HVPMOS
M$4 6 4 7 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
M$4 7 4 6 7 MHVPMOS L=0.25U W=1.5U AS=0.63P AD=0.63P PS=3.84U PD=3.84U
.ENDS TOP

12
testdata/algo/nreader2.cir vendored
View File

@ -54,13 +54,13 @@ X$12 12 13 15 12 11 15 INVX1
* net 6 A
* net 7 BULK
* device instance $1 0.85,5.8 LVPMOS
M$1 2 6 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 1.55,5.8 LVPMOS
M$2 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 0.85,2.135 LVNMOS
M$3 3 6 8 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 1.55,2.135 LVNMOS
M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
* cell INVX1
@ -77,7 +77,7 @@ M$4 8 5 2 7 MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* net 5 IN
* net 6 BULK
* device instance $1 0.85,5.8 LVPMOS
M$1 1 5 2 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 0.85,2.135 LVNMOS
M$2 3 5 2 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1

12
testdata/algo/nreader3.cir vendored
View File

@ -1,13 +1,13 @@
.subckt INVX1 1 2 3 4 5 6
m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um
m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um
m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um
m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um
.ends
.subckt ND2X1 1 2 3 4 5 6 7
m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um
m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um
m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um
m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um
m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um
m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um
m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um
m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um
.ends ND2X1
.subckt RINGO 11 12 13 14 15

12
testdata/algo/nreader7.cir vendored
View File

@ -19,13 +19,13 @@ X$12 OUT FB INVX1
.ENDS RINGO
.SUBCKT ND2X1 OUT B A
M$1 OUT A VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A INT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$4 INT B OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$1 VDD A OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 INT A VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$4 OUT B INT VSS MLVNMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1
.SUBCKT INVX1 OUT IN
M$1 VDD IN OUT VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$1 OUT IN VDD VDD MLVPMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS VSS MLVNMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1

8
testdata/algo/nreader8b.cir vendored
View File

@ -1,8 +1,8 @@
.subckt ND2X1 1 2 3 4 5 6 7
m$1 2 6 1 4 MLVPMOS L=0.25um W=1.5um
m$2 1 5 2 4 MLVPMOS L=0.25um W=1.5um
m$3 3 6 8 7 MLVNMOS L=0.25um W=0.95um
m$4 8 5 2 7 MLVNMOS L=0.25um W=0.95um
m$1 1 6 2 4 MLVPMOS L=0.25um W=1.5um
m$2 2 5 1 4 MLVPMOS L=0.25um W=1.5um
m$3 8 6 3 7 MLVNMOS L=0.25um W=0.95um
m$4 2 5 8 7 MLVNMOS L=0.25um W=0.95um
.ends ND2X1

4
testdata/algo/nreader8x.cir vendored
View File

@ -1,3 +1,3 @@
m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um
m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um
m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um
m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um

4
testdata/algo/nwriter11_au.txt vendored
View File

@ -28,7 +28,7 @@ XSC2 3 7 4 3 C1
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1

4
testdata/algo/nwriter11b_au.txt vendored
View File

@ -18,7 +18,7 @@ XSC2 n3 nc_12 n4 n3 C1
* pin p4
.SUBCKT C1 n1 n2 n4 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 n1 n4 n3 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 n3 n4 n1 n5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 n3 n4 n2 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 n2 n4 n3 n5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1

4
testdata/algo/nwriter5_au.txt vendored
View File

@ -10,7 +10,7 @@
* net 3 n3
* net 4 n4
* device instance $1 r0 *1 0,0 M3CLS
M$1 1 4 3 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 1 M3CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M3CLS
M$2 3 4 2 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 3 M3CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1

4
testdata/algo/nwriter6_au.txt vendored
View File

@ -12,7 +12,7 @@
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1

4
testdata/algo/nwriter8_au.txt vendored
View File

@ -28,7 +28,7 @@ XSC2 3 2 4 3 C1
* net 4 n4
* net 5 n5
* device instance $1 r0 *1 0,0 M4CLS
M$1 1 4 3 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
M$1 3 4 1 5 M4CLS L=0.25U W=0.18U AS=1.2P AD=0.75P PS=2.2U PD=1.75U
* device instance $2 r0 *1 0,0 M4CLS
M$2 3 4 2 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
M$2 2 4 3 5 M4CLS L=1.4U W=0.25U AS=1.3P AD=0.85P PS=2.3U PD=1.85U
.ENDS C1

4
testdata/lvs/double_height.cir vendored
View File

@ -10,8 +10,8 @@ X$2 VSS VDD A1 Q1 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV

4
testdata/lvs/double_height2.cir vendored
View File

@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV

4
testdata/lvs/double_height2_texts.cir vendored
View File

@ -10,8 +10,8 @@ X$2 VSS R A2 Q2 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV

4
testdata/lvs/floating.cir vendored
View File

@ -44,7 +44,7 @@ X$2 3 5 2 6 INVX1
* net 3 IN
* net 4 VSS
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1

8
testdata/lvs/floating.lvsdb vendored
View File

@ -284,9 +284,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 2)
terminal(B 3)
)
device(2 PMOS
@ -297,9 +297,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 4)
terminal(G 1)
terminal(D 4)
terminal(D 2)
terminal(B 4)
)

8
testdata/lvs/inv.lvsdb vendored
View File

@ -197,9 +197,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)
device(2 NMOS
@ -210,9 +210,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 1)
terminal(G 2)
terminal(D 1)
terminal(D 3)
terminal(B 5)
)

8
testdata/lvs/inv2.lvsdb vendored
View File

@ -167,9 +167,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 4)
T(S 3)
T(G 2)
T(D 3)
T(D 4)
T(B 4)
)
D(2 NMOS
@ -180,9 +180,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 3)
T(S 1)
T(G 2)
T(D 1)
T(D 3)
T(B 1)
)
)

4
testdata/lvs/inv2_layout.cir vendored
View File

@ -7,7 +7,7 @@
* net 3 OUT
* net 4 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 2 1 3 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
M$1 3 1 2 2 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
* device instance $2 r0 *1 1.025,0.65 NMOS
M$2 4 1 3 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
M$2 3 1 4 4 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
.ENDS INVERTER_WITH_DIODES

4
testdata/lvs/inv_layout.cir vendored
View File

@ -9,7 +9,7 @@
* net 5 NWELL
* net 6 SUBSTRATE
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 3 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
M$1 4 1 3 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.675P PS=3.9U PD=3.9U
* device instance $2 r0 *1 1.025,0.65 NMOS
M$2 2 1 4 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
M$2 4 1 2 6 NMOS L=0.25U W=0.9U AS=0.405P AD=0.405P PS=2.7U PD=2.7U
.ENDS INVERTER

4
testdata/lvs/invchain_cheat.cir.1 vendored
View File

@ -18,8 +18,8 @@ X$2 \$I2 \$I4 \$I5 \$I7 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV

8
testdata/lvs/nand2_split_gate.cir.1 vendored
View File

@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,2 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,2 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES

8
testdata/lvs/nand2_split_gate.cir.2 vendored
View File

@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES

23
testdata/lvs/nand2_split_gate.cir.3 vendored Normal file
View File

@ -0,0 +1,23 @@
* Extracted by KLayout
* cell NAND2_WITH_DIODES
* pin B
* pin A
* pin OUT
* pin VDD
* pin VSS
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
* net 1 B
* net 2 A
* net 4 OUT
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES

16
testdata/lvs/nand2_split_gate.lvsdb.1 vendored
View File

@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)

16
testdata/lvs/nand2_split_gate.lvsdb.2 vendored
View File

@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)

8
testdata/lvs/nand2_split_gate_early.cir.1 vendored
View File

@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,2 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,2 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES

8
testdata/lvs/nand2_split_gate_early.cir.2 vendored
View File

@ -13,11 +13,11 @@
* net 5 VDD
* net 6 VSS
* device instance $1 r0 *1 1.025,4.95 PMOS
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
* device instance $2 r0 *1 1.775,4.95 PMOS
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
* device instance $3 r0 *1 1.025,0.65 NMOS
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
* device instance $4 r0 *1 1.775,0.65 NMOS
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
.ENDS NAND2_WITH_DIODES

16
testdata/lvs/nand2_split_gate_early.lvsdb.1 vendored
View File

@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)

16
testdata/lvs/nand2_split_gate_early.lvsdb.2 vendored
View File

@ -335,9 +335,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 2)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(2 PMOS
@ -348,9 +348,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 5)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 5)
terminal(B 5)
)
device(3 NMOS
@ -361,9 +361,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 4)
terminal(S 6)
terminal(G 2)
terminal(D 6)
terminal(D 4)
terminal(B 4)
)
device(4 NMOS
@ -374,9 +374,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 3)
terminal(G 1)
terminal(D 3)
terminal(D 6)
terminal(B 4)
)

10
testdata/lvs/ringo.cir vendored
View File

@ -16,12 +16,12 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U
M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U
M$4 1 B OUT BULK NMOS L=0.25U W=0.95U
M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U
M$3 1 A VSS BULK NMOS L=0.25U W=0.95U
M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U
.ENDS ND2X1
.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK
M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U
M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U
M$1 OUT IN VDD NWELL PMOS L=0.25U W=1.5U
M$2 OUT IN VSS BULK NMOS L=0.25U W=0.95U
.ENDS INVX1

12
testdata/lvs/ringo_device_subcircuits.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

BIN
testdata/lvs/ringo_fixed_sources.gds vendored Normal file
View File

Binary file not shown.

16
testdata/lvs/ringo_layout_var.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1B
* cell INVX1
@ -71,9 +71,9 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

4
testdata/lvs/ringo_layout_var.lvsdb.1 vendored
View File

@ -692,9 +692,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_layout_var.lvsdb.2 vendored
View File

@ -692,9 +692,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_mixed_hierarchy.cir vendored
View File

@ -35,13 +35,13 @@ X$15 3 12 16 3 11 16 INVX1
* cell instance $16 r0 *1 18.6,0
X$16 3 13 16 3 12 16 INVX1
* device instance $1 r0 *1 2.65,5.8 PMOS
M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 3 2 4 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 3.35,5.8 PMOS
M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 4 1 3 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 2.65,2.135 NMOS
M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 15 2 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 3.35,2.135 NMOS
M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS RINGO
* cell INVX1
@ -58,7 +58,7 @@ M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1

4
testdata/lvs/ringo_mixed_hierarchy.lvsdb vendored
View File

@ -616,9 +616,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 6)
terminal(S 2)
terminal(G 4)
terminal(D 2)
terminal(D 6)
terminal(B 2)
)
device(2 PMOS

12
testdata/lvs/ringo_simple.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

4
testdata/lvs/ringo_simple.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_simple.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_simple_compare2.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

4
testdata/lvs/ringo_simple_compare2.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_simple_compare2.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_simple_device_scaling.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
M$1 2 5 1 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
M$2 2 5 3 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
M$1 1 6 2 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
M$2 2 5 1 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
M$3 8 6 3 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
M$4 2 5 8 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
.ENDS ND2X1

24
testdata/lvs/ringo_simple_device_scaling.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

24
testdata/lvs/ringo_simple_device_scaling.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

12
testdata/lvs/ringo_simple_dmos.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 7 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 6 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$3 3 7 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 4 6 2 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

62
testdata/lvs/ringo_simple_dmos.lvsdb.1 vendored
View File

@ -609,9 +609,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -851,62 +851,36 @@ xref(
)
)
circuit(ND2X1 ND2X1 nomatch
log(
entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
)
xref(
net(4 8 mismatch)
net(5 4 mismatch)
net(5 4 match)
net(4 3 mismatch)
net(7 6 match)
net(6 5 match)
net(2 2 mismatch)
net(2 2 match)
net(8 7 mismatch)
net(1 1 mismatch)
net(3 3 mismatch)
net(1 1 match)
net(3 8 mismatch)
pin(() 2 mismatch)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 mismatch)
device(4 4 match)
pin(2 () mismatch)
device(3 3 match)
device(4 4 mismatch)
device(1 1 match)
device(2 2 match)
device(1 1 mismatch)
)
)
circuit(RINGO RINGO match
circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1')
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

62
testdata/lvs/ringo_simple_dmos.lvsdb.2 vendored
View File

@ -609,9 +609,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -851,62 +851,36 @@ xref(
)
)
circuit(ND2X1 ND2X1 nomatch
log(
entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
)
xref(
net(4 8 mismatch)
net(5 4 mismatch)
net(5 4 match)
net(4 3 mismatch)
net(7 6 match)
net(6 5 match)
net(2 2 mismatch)
net(2 2 match)
net(8 7 mismatch)
net(1 1 mismatch)
net(3 3 mismatch)
net(1 1 match)
net(3 8 mismatch)
pin(() 2 mismatch)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 mismatch)
device(4 4 match)
pin(2 () mismatch)
device(3 3 match)
device(4 4 mismatch)
device(1 1 match)
device(2 2 match)
device(1 1 mismatch)
)
)
circuit(RINGO RINGO match
circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1')
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

83
testdata/lvs/ringo_simple_dmos_fixed.cir.1 vendored Normal file
View File

@ -0,0 +1,83 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 11 12 13 14 15
* net 11 FB
* net 12 VDD
* net 13 OUT
* net 14 ENABLE
* net 15 VSS
* cell instance $1 r0 *1 1.8,0
X$1 12 1 15 12 11 14 15 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 12 2 15 12 1 15 INVX1
* cell instance $3 r0 *1 6,0
X$3 12 3 15 12 2 15 INVX1
* cell instance $4 r0 *1 7.8,0
X$4 12 4 15 12 3 15 INVX1
* cell instance $5 r0 *1 9.6,0
X$5 12 5 15 12 4 15 INVX1
* cell instance $6 r0 *1 11.4,0
X$6 12 6 15 12 5 15 INVX1
* cell instance $7 r0 *1 13.2,0
X$7 12 7 15 12 6 15 INVX1
* cell instance $8 r0 *1 15,0
X$8 12 8 15 12 7 15 INVX1
* cell instance $9 r0 *1 16.8,0
X$9 12 9 15 12 8 15 INVX1
* cell instance $10 r0 *1 18.6,0
X$10 12 10 15 12 9 15 INVX1
* cell instance $11 r0 *1 20.4,0
X$11 12 11 15 12 10 15 INVX1
* cell instance $12 r0 *1 22.2,0
X$12 12 13 15 12 11 15 INVX1
.ENDS RINGO
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin SUBSTRATE
.SUBCKT ND2X1 1 2 3 5 6 7 8
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 6 B
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U
.ENDS ND2X1

83
testdata/lvs/ringo_simple_dmos_fixed.cir.2 vendored Normal file
View File

@ -0,0 +1,83 @@
* Extracted by KLayout
* cell RINGO
* pin FB
* pin VDD
* pin OUT
* pin ENABLE
* pin VSS
.SUBCKT RINGO 11 12 13 14 15
* net 11 FB
* net 12 VDD
* net 13 OUT
* net 14 ENABLE
* net 15 VSS
* cell instance $1 r0 *1 1.8,0
X$1 12 1 15 12 11 14 15 ND2X1
* cell instance $2 r0 *1 4.2,0
X$2 12 2 15 12 1 15 INVX1
* cell instance $3 r0 *1 6,0
X$3 12 3 15 12 2 15 INVX1
* cell instance $4 r0 *1 7.8,0
X$4 12 4 15 12 3 15 INVX1
* cell instance $5 r0 *1 9.6,0
X$5 12 5 15 12 4 15 INVX1
* cell instance $6 r0 *1 11.4,0
X$6 12 6 15 12 5 15 INVX1
* cell instance $7 r0 *1 13.2,0
X$7 12 7 15 12 6 15 INVX1
* cell instance $8 r0 *1 15,0
X$8 12 8 15 12 7 15 INVX1
* cell instance $9 r0 *1 16.8,0
X$9 12 9 15 12 8 15 INVX1
* cell instance $10 r0 *1 18.6,0
X$10 12 10 15 12 9 15 INVX1
* cell instance $11 r0 *1 20.4,0
X$11 12 11 15 12 10 15 INVX1
* cell instance $12 r0 *1 22.2,0
X$12 12 13 15 12 11 15 INVX1
.ENDS RINGO
* cell INVX1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin IN
* pin SUBSTRATE
.SUBCKT INVX1 1 2 3 4 5 6
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
* pin VDD
* pin OUT
* pin VSS
* pin
* pin B
* pin A
* pin SUBSTRATE
.SUBCKT ND2X1 1 2 3 5 6 7 8
* net 1 VDD
* net 2 OUT
* net 3 VSS
* net 6 B
* net 7 A
* net 8 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 1.55,2.135 NMOS
M$3 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U
* device instance $4 r0 *1 0.85,2.135 NMOS
M$4 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U
.ENDS ND2X1

83
testdata/lvs/ringo_simple_dmos_fixed.lvs vendored Normal file
View File

@ -0,0 +1,83 @@
source($lvs_test_source, "RINGO")
report_lvs($lvs_test_target_lvsdb, true)
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
schematic("ringo.cir")
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
pplus = input(3, 0)
nplus = input(4, 0)
poly = input(5, 0)
contact = input(8, 0)
metal1 = input(9, 0)
via1 = input(10, 0)
metal2 = input(11, 0)
source = input(14, 0)
# Bulk layer for terminal provisioning
bulk = polygon_layer
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
pgate = pactive & poly
psd = pactive - pgate
ps = psd & source
pd = psd - source
ntie = active_in_nwell & nplus
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ngate = nactive & poly
nsd = nactive - ngate
ns = nsd & source
nd = nsd - source
ptie = active_outside_nwell & pplus
# Device extraction
# PMOS transistor device extraction
extract_devices(dmos4("PMOS"), { "S" => ps, "D" => pd, "G" => pgate, "W" => nwell,
"tS" => ps, "tD" => pd, "tG" => poly, "tW" => nwell })
# NMOS transistor device extraction
extract_devices(dmos4("NMOS"), { "S" => ns, "D" => nd, "G" => ngate, "W" => bulk,
"tS" => ns, "tD" => nd, "tG" => poly, "tW" => bulk })
# Define connectivity for netlist extraction
# Inter-layer
connect(ps, pd)
connect(ns, nd)
connect(ps, contact)
connect(pd, contact)
connect(ns, contact)
connect(nd, contact)
connect(poly, contact)
connect(ntie, contact)
connect(nwell, ntie)
connect(ptie, contact)
connect(contact, metal1)
connect(metal1, via1)
connect(via1, metal2)
# Global
connect_global(bulk, "SUBSTRATE")
connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.simplify
compare

918
testdata/lvs/ringo_simple_dmos_fixed.lvsdb.1 vendored Normal file
View File

@ -0,0 +1,918 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l4 '1/0')
layer(l5 '5/0')
layer(l10 '8/0')
layer(l13 '9/0')
layer(l14 '10/0')
layer(l15 '11/0')
layer(l9)
layer(l3)
layer(l1)
layer(l11)
layer(l8)
layer(l6)
layer(l12)
# Mask layer connectivity
connect(l4 l4 l11)
connect(l5 l5 l10)
connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
connect(l13 l10 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l9 l9)
connect(l3 l10 l3 l1)
connect(l1 l10 l3 l1)
connect(l11 l4 l10 l11)
connect(l8 l10 l8 l6)
connect(l6 l10 l8 l6)
connect(l12 l10 l12)
# Global nets and connectivity
global(l9 SUBSTRATE)
global(l12 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l3 (125 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (-550 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l3 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l3 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (233 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l8 (-342 -475) (217 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -790) (300 1700))
rect(l13 (-1350 0) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l3 (-275 -2150) (425 1500))
rect(l3 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l10 (1810 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-1580 3760) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (1220 920) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l13 (-110 1390) (300 1400))
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l13 (-140 -500) (0 0))
rect(l13 (-1750 1100) (300 1400))
rect(l13 (1100 -1700) (300 300))
rect(l13 (-300 0) (300 1400))
rect(l1 (-1750 -1450) (425 1500))
rect(l1 (950 -1500) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l8 (-950 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l8 (1208 1660) (192 950))
rect(l8 (-192 -950) (217 950))
rect(l6 (-425 -950) (208 950))
rect(l6 (-233 -950) (233 950))
)
net(5
rect(l4 (-100 4500) (2600 3500))
)
net(6 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-285 1050) (180 180))
rect(l13 (-70 -90) (0 0))
rect(l13 (-170 -150) (300 300))
)
net(7 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-265 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(8 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(5)
pin(6 name(B))
pin(7 name(A))
pin(8 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 7)
terminal(D 2)
terminal(B 5)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 5)
)
device(3 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.22135)
param(PS 2.75)
param(PD 2.366)
terminal(S 3)
terminal(G 7)
terminal(D 4)
terminal(B 8)
)
device(4 D$NMOS$1
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.20615)
param(AD 0.40375)
param(PS 2.334)
param(PD 2.75)
terminal(S 4)
terminal(G 6)
terminal(D 2)
terminal(B 8)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (410 6260) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -240) (300 1400))
rect(l13 (-650 300) (1800 800))
rect(l13 (-1450 -1100) (300 300))
rect(l13 (300 400) (0 0))
rect(l3 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -4120) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -790) (300 4790))
rect(l13 (-150 -2500) (0 0))
rect(l1 (-225 1050) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (1800 800))
rect(l13 (-850 -400) (0 0))
rect(l8 (-650 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l4 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-465 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l13 (4040 2950) (610 300))
)
net(2
rect(l13 (5550 2950) (900 300))
)
net(3
rect(l13 (7350 2950) (900 300))
)
net(4
rect(l13 (9150 2950) (900 300))
)
net(5
rect(l13 (10950 2950) (900 300))
)
net(6
rect(l13 (12750 2950) (900 300))
)
net(7
rect(l13 (14550 2950) (900 300))
)
net(8
rect(l13 (16350 2950) (900 300))
)
net(9
rect(l13 (18150 2950) (900 300))
)
net(10
rect(l13 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l13 (21750 2950) (900 300))
rect(l13 (-19530 590) (320 320))
rect(l13 (17820 -320) (320 320))
rect(l14 (-18400 -260) (200 200))
rect(l14 (17940 -200) (200 200))
rect(l15 (-18040 -300) (17740 400))
rect(l15 (-17920 -200) (0 0))
rect(l15 (-220 -200) (400 400))
rect(l15 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l4 (500 4500) (1400 3500))
rect(l4 (-1900 -3500) (600 3500))
rect(l4 (23300 -3500) (1400 3500))
rect(l4 (-100 -3500) (600 3500))
rect(l10 (-24690 -1240) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l13 (-21740 860) (0 0))
rect(l13 (-2350 -450) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23400 -800) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (550 -400) (600 800))
rect(l11 (-24850 -1500) (500 1500))
rect(l11 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l13 (23440 3840) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(14 name(ENABLE)
rect(l13 (2440 2940) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(15 name(VSS)
rect(l10 (1110 1610) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-21740 -390) (0 0))
rect(l13 (-1900 -400) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23850 -750) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (550 -400) (600 800))
rect(l12 (-24850 -800) (500 1500))
rect(l12 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(4 8 match)
net(5 4 match)
net(7 6 match)
net(6 5 match)
net(2 2 match)
net(8 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

918
testdata/lvs/ringo_simple_dmos_fixed.lvsdb.2 vendored Normal file
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@ -0,0 +1,918 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l4 '1/0')
layer(l5 '5/0')
layer(l10 '8/0')
layer(l13 '9/0')
layer(l14 '10/0')
layer(l15 '11/0')
layer(l9)
layer(l3)
layer(l1)
layer(l11)
layer(l8)
layer(l6)
layer(l12)
# Mask layer connectivity
connect(l4 l4 l11)
connect(l5 l5 l10)
connect(l10 l5 l10 l13 l3 l1 l11 l8 l6 l12)
connect(l13 l10 l13 l14)
connect(l14 l13 l14 l15)
connect(l15 l14 l15)
connect(l9 l9)
connect(l3 l10 l3 l1)
connect(l1 l10 l3 l1)
connect(l11 l4 l10 l11)
connect(l8 l10 l8 l6)
connect(l6 l10 l8 l6)
connect(l12 l10 l12)
# Global nets and connectivity
global(l9 SUBSTRATE)
global(l12 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l3 (125 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (-550 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l3 (-575 -750) (450 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l3 (-550 -750) (425 1500))
)
terminal(G
rect(l5 (-125 -750) (250 1500))
)
terminal(D
rect(l1 (125 -750) (425 1500))
)
terminal(B
rect(l4 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l8 (-342 -475) (217 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (233 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l8 (-550 -475) (425 950))
)
terminal(G
rect(l5 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l9 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -790) (300 1700))
rect(l13 (-1350 0) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l3 (-250 -2150) (425 1500))
rect(l3 (-450 -1500) (425 1500))
)
net(2 name(OUT)
rect(l10 (1810 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-1580 3760) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (1220 920) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
polygon(l13 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l13 (-110 1390) (300 1400))
polygon(l13 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l13 (-140 -500) (0 0))
rect(l13 (-1750 1100) (300 1400))
rect(l13 (1100 -1700) (300 300))
rect(l13 (-300 0) (300 1400))
rect(l1 (-1750 -1450) (425 1500))
rect(l1 (950 -1500) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (2400 800))
rect(l13 (-1150 -400) (0 0))
rect(l8 (-950 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l8 (1208 1660) (192 950))
rect(l8 (-192 -950) (217 950))
rect(l6 (-425 -950) (208 950))
rect(l6 (-233 -950) (233 950))
)
net(5
rect(l4 (-100 4500) (2600 3500))
)
net(6 name(B)
rect(l5 (1425 2860) (250 1940))
rect(l5 (-345 -950) (300 300))
rect(l5 (-205 650) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-285 1050) (180 180))
rect(l13 (-70 -90) (0 0))
rect(l13 (-170 -150) (300 300))
)
net(7 name(A)
rect(l5 (725 2860) (250 1940))
rect(l5 (-325 -1850) (300 300))
rect(l5 (-225 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-265 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(8 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(5)
pin(6 name(B))
pin(7 name(A))
pin(8 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 7)
terminal(D 2)
terminal(B 5)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 5)
)
device(3 D$NMOS
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.20615)
param(AD 0.40375)
param(PS 2.334)
param(PD 2.75)
terminal(S 4)
terminal(G 6)
terminal(D 2)
terminal(B 8)
)
device(4 D$NMOS$1
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.22135)
param(PS 2.75)
param(PD 2.366)
terminal(S 3)
terminal(G 7)
terminal(D 4)
terminal(B 8)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l10 (410 6260) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l13 (-240 -240) (300 1400))
rect(l13 (-650 300) (1800 800))
rect(l13 (-1450 -1100) (300 300))
rect(l13 (300 400) (0 0))
rect(l3 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l10 (1110 5160) (180 180))
rect(l10 (-180 920) (180 180))
rect(l10 (-180 -730) (180 180))
rect(l10 (-180 -4120) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -790) (300 4790))
rect(l13 (-150 -2500) (0 0))
rect(l1 (-225 1050) (425 1500))
rect(l6 (-192 -4890) (192 950))
rect(l6 (-425 -950) (233 950))
)
net(3 name(VSS)
rect(l10 (410 1770) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-240 -1300) (300 1360))
rect(l13 (-650 -2160) (1800 800))
rect(l13 (-850 -400) (0 0))
rect(l8 (-650 860) (208 950))
rect(l8 (0 -950) (217 950))
)
net(4
rect(l4 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l5 (725 2860) (250 1940))
rect(l5 (-525 -1850) (300 300))
rect(l5 (-25 1550) (250 2000))
rect(l5 (-250 -2000) (250 2000))
rect(l5 (-250 -5390) (250 1450))
rect(l10 (-465 150) (180 180))
rect(l13 (-90 -90) (0 0))
rect(l13 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1
rect(l13 (4040 2950) (610 300))
)
net(2
rect(l13 (5550 2950) (900 300))
)
net(3
rect(l13 (7350 2950) (900 300))
)
net(4
rect(l13 (9150 2950) (900 300))
)
net(5
rect(l13 (10950 2950) (900 300))
)
net(6
rect(l13 (12750 2950) (900 300))
)
net(7
rect(l13 (14550 2950) (900 300))
)
net(8
rect(l13 (16350 2950) (900 300))
)
net(9
rect(l13 (18150 2950) (900 300))
)
net(10
rect(l13 (19950 2950) (900 300))
)
net(11 name(FB)
rect(l13 (21750 2950) (900 300))
rect(l13 (-19530 590) (320 320))
rect(l13 (17820 -320) (320 320))
rect(l14 (-18400 -260) (200 200))
rect(l14 (17940 -200) (200 200))
rect(l15 (-18040 -300) (17740 400))
rect(l15 (-17920 -200) (0 0))
rect(l15 (-220 -200) (400 400))
rect(l15 (17740 -400) (400 400))
)
net(12 name(VDD)
rect(l4 (500 4500) (1400 3500))
rect(l4 (-1900 -3500) (600 3500))
rect(l4 (23300 -3500) (1400 3500))
rect(l4 (-100 -3500) (600 3500))
rect(l10 (-24690 -1240) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l13 (-21740 860) (0 0))
rect(l13 (-2350 -450) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23400 -800) (1200 800))
rect(l13 (-750 -1450) (300 1400))
rect(l13 (-100 -350) (0 0))
rect(l13 (550 -400) (600 800))
rect(l11 (-24850 -1500) (500 1500))
rect(l11 (22900 -1500) (500 1500))
)
net(13 name(OUT)
rect(l13 (23440 3840) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(14 name(ENABLE)
rect(l13 (2440 2940) (320 320))
rect(l14 (-260 -260) (200 200))
rect(l15 (-100 -100) (0 0))
rect(l15 (-200 -200) (400 400))
)
net(15 name(VSS)
rect(l10 (1110 1610) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l10 (23220 370) (180 180))
rect(l10 (-180 -1280) (180 180))
rect(l10 (-180 370) (180 180))
rect(l13 (-21740 -390) (0 0))
rect(l13 (-1900 -400) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (-1250 -400) (600 800))
rect(l13 (23850 -750) (300 1400))
rect(l13 (-750 -1450) (1200 800))
rect(l13 (-550 -400) (0 0))
rect(l13 (550 -400) (600 800))
rect(l12 (-24850 -800) (500 1500))
rect(l12 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(11 name(FB))
pin(12 name(VDD))
pin(13 name(OUT))
pin(14 name(ENABLE))
pin(15 name(VSS))
# Subcircuits and their connections
circuit(1 ND2X1 location(1800 0)
pin(0 12)
pin(1 1)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 14)
pin(6 15)
)
circuit(2 INVX1 location(4200 0)
pin(0 12)
pin(1 2)
pin(2 15)
pin(3 12)
pin(4 1)
pin(5 15)
)
circuit(3 INVX1 location(6000 0)
pin(0 12)
pin(1 3)
pin(2 15)
pin(3 12)
pin(4 2)
pin(5 15)
)
circuit(4 INVX1 location(7800 0)
pin(0 12)
pin(1 4)
pin(2 15)
pin(3 12)
pin(4 3)
pin(5 15)
)
circuit(5 INVX1 location(9600 0)
pin(0 12)
pin(1 5)
pin(2 15)
pin(3 12)
pin(4 4)
pin(5 15)
)
circuit(6 INVX1 location(11400 0)
pin(0 12)
pin(1 6)
pin(2 15)
pin(3 12)
pin(4 5)
pin(5 15)
)
circuit(7 INVX1 location(13200 0)
pin(0 12)
pin(1 7)
pin(2 15)
pin(3 12)
pin(4 6)
pin(5 15)
)
circuit(8 INVX1 location(15000 0)
pin(0 12)
pin(1 8)
pin(2 15)
pin(3 12)
pin(4 7)
pin(5 15)
)
circuit(9 INVX1 location(16800 0)
pin(0 12)
pin(1 9)
pin(2 15)
pin(3 12)
pin(4 8)
pin(5 15)
)
circuit(10 INVX1 location(18600 0)
pin(0 12)
pin(1 10)
pin(2 15)
pin(3 12)
pin(4 9)
pin(5 15)
)
circuit(11 INVX1 location(20400 0)
pin(0 12)
pin(1 11)
pin(2 15)
pin(3 12)
pin(4 10)
pin(5 15)
)
circuit(12 INVX1 location(22200 0)
pin(0 12)
pin(1 13)
pin(2 15)
pin(3 12)
pin(4 11)
pin(5 15)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 6)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(4 8 match)
net(5 4 match)
net(7 6 match)
net(6 5 match)
net(2 2 match)
net(8 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(4 3 match)
device(3 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(1 6 match)
net(10 15 match)
net(2 7 match)
net(3 8 match)
net(4 9 match)
net(5 10 match)
net(6 11 match)
net(7 12 match)
net(8 13 match)
net(9 14 match)
net(14 4 match)
net(11 3 match)
net(13 5 match)
net(12 2 match)
net(15 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
circuit(2 2 match)
circuit(3 3 match)
circuit(4 4 match)
circuit(5 5 match)
circuit(6 6 match)
circuit(7 7 match)
circuit(8 8 match)
circuit(9 9 match)
circuit(10 10 match)
circuit(11 11 match)
circuit(12 12 match)
circuit(1 1 match)
)
)
)

12
testdata/lvs/ringo_simple_dummy_device.cir vendored
View File

@ -54,9 +54,9 @@ M$1 16 1 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -75,11 +75,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

26
testdata/lvs/ringo_simple_dummy_device.lvsdb.1 vendored
View File

@ -609,8 +609,8 @@ layout(
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -657,9 +657,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -670,9 +670,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -683,9 +683,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -717,9 +717,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -730,9 +730,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

26
testdata/lvs/ringo_simple_dummy_device.lvsdb.2 vendored
View File

@ -609,8 +609,8 @@ layout(
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -657,9 +657,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -670,9 +670,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 6)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -683,9 +683,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -717,9 +717,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -730,9 +730,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

965
testdata/lvs/ringo_simple_dummy_device.lvsdb.3 vendored
View File

@ -1,965 +0,0 @@
#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Circuit boundary
rect((-100 400) (2600 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -790) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l2 (-275 -2150) (425 1500))
rect(l2 (-400 -1500) (425 1500))
)
net(2 name(OUT)
rect(l8 (1810 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-140 -500) (0 0))
rect(l11 (-1750 1100) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l6 (-950 860) (425 950))
)
net(4
rect(l3 (-100 4500) (2600 3500))
)
net(5 name(B)
rect(l4 (1425 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
rect(l11 (-70 -90) (0 0))
rect(l11 (-170 -150) (300 300))
)
net(6 name(A)
rect(l4 (725 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-265 150) (180 180))
rect(l11 (-90 -90) (0 0))
rect(l11 (-150 -150) (300 300))
)
net(7 name(SUBSTRATE))
net(8
rect(l6 (975 1660) (425 950))
rect(l6 (-400 -950) (425 950))
)
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(B))
pin(6 name(A))
pin(7 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 D$PMOS$1
location(1550 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 D$NMOS$1
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 D$NMOS$2
location(1550 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (300 400) (0 0))
rect(l2 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-150 -2500) (0 0))
rect(l2 (-225 1050) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-850 -400) (0 0))
rect(l6 (-650 860) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 1550) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-465 150) (180 180))
rect(l11 (-90 -90) (0 0))
rect(l11 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 D$NMOS
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (27600 7650))
# Nets with their geometries
net(1
rect(l4 (26050 2800) (525 550))
rect(l4 (-525 -300) (300 300))
rect(l4 (-25 -2000) (250 1450))
rect(l8 (-465 310) (180 180))
rect(l11 (-240 -240) (300 300))
)
net(2
rect(l11 (4040 2950) (610 300))
)
net(3
rect(l11 (5550 2950) (900 300))
)
net(4
rect(l11 (7350 2950) (900 300))
)
net(5
rect(l11 (9150 2950) (900 300))
)
net(6
rect(l11 (10950 2950) (900 300))
)
net(7
rect(l11 (12750 2950) (900 300))
)
net(8
rect(l11 (14550 2950) (900 300))
)
net(9
rect(l11 (16350 2950) (900 300))
)
net(10
rect(l11 (18150 2950) (900 300))
)
net(11
rect(l11 (19950 2950) (900 300))
)
net(12 name(FB)
rect(l11 (21750 2950) (900 300))
rect(l11 (-19530 590) (320 320))
rect(l11 (17820 -320) (320 320))
rect(l12 (-18400 -260) (200 200))
rect(l12 (17940 -200) (200 200))
rect(l13 (-18040 -300) (17740 400))
rect(l13 (-17920 -200) (0 0))
rect(l13 (-220 -200) (400 400))
rect(l13 (17740 -400) (400 400))
)
net(13 name(VDD)
rect(l3 (500 4500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l3 (0 -3500) (600 3500))
rect(l8 (-26490 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21740 860) (0 0))
rect(l11 (-2350 -450) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l9 (-26650 -1500) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(14 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(15 name(ENABLE)
rect(l11 (2440 2940) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(16 name(VSS)
rect(l8 (26010 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (520 -730) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-25780 -890) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (1260 -40) (300 1360))
rect(l11 (400 -1360) (300 1360))
rect(l11 (-24000 -1710) (0 0))
rect(l11 (-1900 -400) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l11 (0 -800) (600 800))
rect(l6 (-1025 400) (425 950))
rect(l6 (-1100 -950) (425 950))
rect(l10 (-25375 -2150) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(12 name(FB))
pin(13 name(VDD))
pin(14 name(OUT))
pin(15 name(ENABLE))
pin(16 name(VSS))
# Devices and their connections
device(1 D$NMOS
location(26450 2075)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 16)
terminal(G 1)
terminal(D 16)
terminal(B 16)
)
# Subcircuits and their connections
circuit(3 ND2X1 location(1800 0)
pin(0 13)
pin(1 2)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 15)
pin(6 16)
)
circuit(4 INVX1 location(4200 0)
pin(0 13)
pin(1 3)
pin(2 16)
pin(3 13)
pin(4 2)
pin(5 16)
)
circuit(5 INVX1 location(6000 0)
pin(0 13)
pin(1 4)
pin(2 16)
pin(3 13)
pin(4 3)
pin(5 16)
)
circuit(6 INVX1 location(7800 0)
pin(0 13)
pin(1 5)
pin(2 16)
pin(3 13)
pin(4 4)
pin(5 16)
)
circuit(7 INVX1 location(9600 0)
pin(0 13)
pin(1 6)
pin(2 16)
pin(3 13)
pin(4 5)
pin(5 16)
)
circuit(8 INVX1 location(11400 0)
pin(0 13)
pin(1 7)
pin(2 16)
pin(3 13)
pin(4 6)
pin(5 16)
)
circuit(9 INVX1 location(13200 0)
pin(0 13)
pin(1 8)
pin(2 16)
pin(3 13)
pin(4 7)
pin(5 16)
)
circuit(10 INVX1 location(15000 0)
pin(0 13)
pin(1 9)
pin(2 16)
pin(3 13)
pin(4 8)
pin(5 16)
)
circuit(11 INVX1 location(16800 0)
pin(0 13)
pin(1 10)
pin(2 16)
pin(3 13)
pin(4 9)
pin(5 16)
)
circuit(12 INVX1 location(18600 0)
pin(0 13)
pin(1 11)
pin(2 16)
pin(3 13)
pin(4 10)
pin(5 16)
)
circuit(13 INVX1 location(20400 0)
pin(0 13)
pin(1 12)
pin(2 16)
pin(3 13)
pin(4 11)
pin(5 16)
)
circuit(14 INVX1 location(22200 0)
pin(0 13)
pin(1 14)
pin(2 16)
pin(3 13)
pin(4 12)
pin(5 16)
)
)
)
# Reference netlist
reference(
# Device class section
class(NMOS MOS4)
class(PMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(ND2X1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(B))
net(6 name(A))
net(7 name(BULK))
net(8 name('1'))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(B))
pin(6 name(A))
pin(7 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(G 6)
terminal(D 1)
terminal(B 4)
)
device(2 PMOS
name($2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(3 NMOS
name($3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 6)
terminal(D 8)
terminal(B 7)
)
device(4 NMOS
name($4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(G 5)
terminal(D 2)
terminal(B 7)
)
)
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
net(16 name(DUMMY))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Devices and their connections
device(1 NMOS
name($1)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(G 16)
terminal(D 1)
terminal(B 1)
)
# Subcircuits and their connections
circuit(1 ND2X1 name($1)
pin(0 2)
pin(1 6)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 4)
pin(6 1)
)
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
device(2 2 match)
device(1 1 match)
)
)
circuit(ND2X1 ND2X1 match
xref(
net(8 8 match)
net(4 4 match)
net(6 6 match)
net(5 5 match)
net(2 2 match)
net(7 7 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(5 5 match)
pin(4 4 match)
pin(1 1 match)
pin(6 6 match)
pin(0 0 match)
pin(2 2 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
)
)
circuit(RINGO RINGO match
xref(
net(2 6 match)
net(11 15 match)
net(3 7 match)
net(4 8 match)
net(5 9 match)
net(6 10 match)
net(7 11 match)
net(8 12 match)
net(9 13 match)
net(10 14 match)
net(1 16 match)
net(15 4 match)
net(12 3 match)
net(14 5 match)
net(13 2 match)
net(16 1 match)
pin(3 3 match)
pin(0 2 match)
pin(2 4 match)
pin(1 1 match)
pin(4 0 match)
device(1 1 match)
circuit(4 2 match)
circuit(5 3 match)
circuit(6 4 match)
circuit(7 5 match)
circuit(8 6 match)
circuit(9 7 match)
circuit(10 8 match)
circuit(11 9 match)
circuit(12 10 match)
circuit(13 11 match)
circuit(14 12 match)
circuit(3 1 match)
)
)
)

12
testdata/lvs/ringo_simple_implicit_connections.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

4
testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 vendored
View File

@ -624,9 +624,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_simple_implicit_connections.lvsdb.2 vendored
View File

@ -624,9 +624,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_simple_io.cir.1 vendored
View File

@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I3 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I3 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1

12
testdata/lvs/ringo_simple_io.cir.2 vendored
View File

@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
.ENDS RINGO
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
+ PD=2.75U
.ENDS INVX1
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$3 \$I5 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
+ PD=1.4U
M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
M$4 OUT B \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
+ PD=2.75U
.ENDS ND2X1

4
testdata/lvs/ringo_simple_io.lvsdb.1 vendored
View File

@ -546,9 +546,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(S 1)
T(G 6)
T(D 1)
T(D 2)
T(B 4)
)
D(2 PMOS

4
testdata/lvs/ringo_simple_io.lvsdb.2 vendored
View File

@ -546,9 +546,9 @@ H(
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(S 1)
T(G 6)
T(D 1)
T(D 2)
T(B 4)
)
D(2 PMOS

4
testdata/lvs/ringo_simple_io2.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_simple_io2.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_simple_net_and_circuit_equivalence.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INV
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INV
* cell nd2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS nd2X1

4
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

4
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 6)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS

12
testdata/lvs/ringo_simple_pin_swapping.cir vendored
View File

@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
* net 5 IN
* net 6 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
* device instance $2 r0 *1 0.85,2.135 NMOS
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
.ENDS INVX1
* cell ND2X1
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
* net 6 A
* net 7 SUBSTRATE
* device instance $1 r0 *1 0.85,5.8 PMOS
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
* device instance $2 r0 *1 1.55,5.8 PMOS
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
* device instance $3 r0 *1 0.85,2.135 NMOS
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
* device instance $4 r0 *1 1.55,2.135 NMOS
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
.ENDS ND2X1

24
testdata/lvs/ringo_simple_pin_swapping.lvsdb.1 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 5)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 5)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

24
testdata/lvs/ringo_simple_pin_swapping.lvsdb.2 vendored
View File

@ -605,9 +605,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 2)
terminal(S 1)
terminal(G 5)
terminal(D 1)
terminal(D 2)
terminal(B 4)
)
device(2 PMOS
@ -618,9 +618,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(3 NMOS
@ -631,9 +631,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 8)
terminal(G 5)
terminal(D 8)
terminal(D 3)
terminal(B 7)
)
device(4 NMOS
@ -644,9 +644,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 8)
terminal(S 2)
terminal(G 6)
terminal(D 2)
terminal(D 8)
terminal(B 7)
)
@ -678,9 +678,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 1)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 1)
terminal(B 4)
)
device(2 NMOS
@ -691,9 +691,9 @@ reference(
param(AD 0)
param(PS 0)
param(PD 0)
terminal(S 3)
terminal(S 2)
terminal(G 5)
terminal(D 2)
terminal(D 3)
terminal(B 6)
)

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