From 20c8c6bdaadfc8a417c470227a67505390e022ea Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Thu, 4 Jul 2019 00:57:04 +0200 Subject: [PATCH] WIP: more LVS doc. --- src/lay/lay/doc/manual/lvs.xml | 5 +- src/lay/lay/doc/manual/lvs_compare.xml | 17 + src/lay/lay/doc/manual/lvs_device_classes.xml | 250 ++++++++ .../lay/doc/manual/lvs_device_extractors.xml | 326 ++++++++++ src/lay/lay/doc/manual/lvs_devices.xml | 557 +----------------- src/lay/lay/doc/manual/lvs_io.xml | 240 ++++++++ src/lay/lay/doc/manual/lvs_tweaks.xml | 17 + src/lay/lay/layHelpResources.qrc | 5 + 8 files changed, 870 insertions(+), 547 deletions(-) create mode 100644 src/lay/lay/doc/manual/lvs_compare.xml create mode 100644 src/lay/lay/doc/manual/lvs_device_classes.xml create mode 100644 src/lay/lay/doc/manual/lvs_device_extractors.xml create mode 100644 src/lay/lay/doc/manual/lvs_io.xml create mode 100644 src/lay/lay/doc/manual/lvs_tweaks.xml diff --git a/src/lay/lay/doc/manual/lvs.xml b/src/lay/lay/doc/manual/lvs.xml index 2cbfdc05f..e39fb29d2 100644 --- a/src/lay/lay/doc/manual/lvs.xml +++ b/src/lay/lay/doc/manual/lvs.xml @@ -14,6 +14,9 @@ + + + diff --git a/src/lay/lay/doc/manual/lvs_compare.xml b/src/lay/lay/doc/manual/lvs_compare.xml new file mode 100644 index 000000000..b23365003 --- /dev/null +++ b/src/lay/lay/doc/manual/lvs_compare.xml @@ -0,0 +1,17 @@ + + + + + + LVS Device Classes + + + + + +

+ LVS (and also DRC as far as netlist extraction is concerned) provides + +

+ + diff --git a/src/lay/lay/doc/manual/lvs_device_classes.xml b/src/lay/lay/doc/manual/lvs_device_classes.xml new file mode 100644 index 000000000..b34e2d52c --- /dev/null +++ b/src/lay/lay/doc/manual/lvs_device_classes.xml @@ -0,0 +1,250 @@ + + + + + + LVS Device Classes + + + + + +

+ KLayout implements a variety of standard device classes. These device classes + are the basis for forming particular incarnations of device classes. + For example, the MOS4 class is the basis for the specific device classes + for NMOS and PMOS transistors. +

+ +

Resistor

+ +

+ +

+ +

+ The plain resistor has two terminals, A and B. It features the following + parameters: +

+ +
    +
  • R: The resistance value in Ohm
    • +
  • L: The length in µm
    • +
  • W: The width in µm
    • +
  • A: The area of the resistor area in µm²
    • +
  • P: The perimeter of the resistor area in µm
    • +
+ +

+ Resistors can combine in parallel or serial fashion. +

+ +

+ In SPICE, plain resistors are represented by the "R" element. + The API class is . +

+ +

Resistor with bulk terminal

+ +

+ +

+ +

+ The resistor with bulk terminal is an extension of the plain resistor. + If has the same parameters, but one additional terminal (W) which connects to + the area the resistor sits in (e.g. well or substrate). +

+ +

+ Resistors with bulk can combine in parallel or serial fashion if their + bulk terminals are connected to the same net. +

+ +

+ The API class of the resistor with bulk is . +

+ +

Capacitor

+ +

+ +

+ +

+ The plain capacitor has two terminals, A and B. It features the following + parameters: +

+ +
    +
  • C: The capacitance value in Farad
    • +
  • A: The area of the capacitor area in µm²
    • +
  • P: The perimeter of the capacitor area in µm
    • +
+ +

+ In SPICE, plain capacitors are represented by the "C" element. + The API class is . +

+ +

Capacitor with bulk terminal

+ +

+ +

+ +

+ The capacitor with bulk terminal is an extension of the plain capacitor. + If has the same parameters, but one additional terminal (W) which connects to + the area the capacitor sits in (e.g. well or substrate). +

+ +

+ Capacitors with bulk can combine in parallel or serial fashion if their + bulk terminals are connected to the same net. +

+ +

+ The API class of the capacitor with bulk is . +

+ +

Diode

+ +

+ +

+ +

+ Diodes have two terminals, A and C for anode and cathode. Diodes + feature the following parameters: +

+ +
    +
  • A: The area of the diode in µm²
    • +
  • P: The perimeter of the diode in µm
    • +
+ +

+ Diodes combine in parallel (A to A and C to C). In this case + their areas and perimeters will add. +

+ +

+ In SPICE, diodes are represented by the "D" element using the + device class name as the model name. + The API class is . +

+ +

MOS transistor

+ +

+ +

+ +

+ Three-terminal MOS transistors have terminals S, G and D for source, gate and drain. + S and D are commutable. They feature the following parameters: +

+ +
    +
  • W: The gate width in µm
    • +
  • L: The gate (channel) length in µm
    • +
  • AS: The source area in µm²
    • +
  • PS: The source perimeter in µm
    • +
  • AD: The drain area in µm²
    • +
  • PD: The drain perimeter in µm
    • +
+ +

+ MOS3 transistors combine in parallel when the source/drains and gates are connected + and their gate lengths are identical. + In this case their widths, areas and perimeters will add. +

+ +

MOS transistor with bulk

+ +

+ The API class of the three-terminal MOS transistor is . +

+ +

+ +

+ +

+ The four-terminal transistor is an extension of the three-terminal one and + offers an additional bulk terminal (B). It is probably the most prominent + transistor device as the four-terminal version is compatible with the SPICE + "M" element. +

+ +

+ MOS transistors with bulk can combine in parallel the same way the three-terminal + versions do if their bulk terminals are connected to the same net. +

+ +

+ In SPICE, MOS4 devices are represented by the "M" element with the + device class name as the model name. + The API class is . +

+ +

Bipolar transistor

+ +

+ +

+ +

+ The three-terminal bipolar transistor can be either NPN or PNP type. + In KLayout, this device type can represent both lateral and vertical + types. + The parameters are: +

+ +
    +
  • AE: The emitter area in µm²
    • +
  • PE: The emitter perimeter in µm
    • +
  • NE: The emitter count (initially 1)
    • +
  • AB: The base area in µm²
    • +
  • PB: The base perimeter in µm
    • +
  • AC: The collector area in µm²
    • +
  • PC: The collector perimeter in µm
    • +
+ +

+ Upon extraction, multi-emitter versions are extracted as multiple devices - one + for each emitter area - and NE = 1. Bipolar transistors combine when in parallel. + In this case, their emitter parameters AE, PE and NE are added. +

+ +

+ In SPICE, BJT3 devices are represented by the "Q" element with the + device class name as the model name. + The API class is . +

+ +

Bipolar transistor with substrate

+ +

+ +

+ +

+ The four-terminal transistor is an extension of the three-terminal one and + offers an additional bulk terminal (S). +

+ +

+ Bipolar transistors with bulk can combine in parallel the same way the three-terminal + versions do if their bulk terminals are connected to the same net. +

+ +

+ In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the + device class name as the model name. + The API class is . +

+ + + diff --git a/src/lay/lay/doc/manual/lvs_device_extractors.xml b/src/lay/lay/doc/manual/lvs_device_extractors.xml new file mode 100644 index 000000000..cb5110e8e --- /dev/null +++ b/src/lay/lay/doc/manual/lvs_device_extractors.xml @@ -0,0 +1,326 @@ + + + + + + LVS Devices + + + + + +

+ Device extractors and the actual "workers" of the device extraction process. + KLayout comes with a variety of pre-built device extractors. It's possible to + implement custom device extractors in the framework of LVS scripts (speaking + Ruby). +

+ +

Resistor extractors (resistor + and resistor_with_bulk)

+ +

+ The resistor extractor assumes a layout which consists of a resistor "wire" + and two caps (contacts). The wire is specified with the layer symbol "R", + the caps are specified with the layer symbol "C": +

+ +

+ +

+ +

+ The extractor will compute the resistance from the number of squares + and the sheet resistance. The sheet resistance needs to be given + when creating the extractor: +

+ + 
sheet_rho = 0.5
+model_name = "RES"
+extract_devices(resistor(model_name, sheet_rho), { "R" => res_layer, "C" => cap_layer })
+ +

+ The plain resistor offers two terminals which it outputs on "tA" and "tB" terminal layers. + If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "C" layer. + respectively. +

+ +

+ +

+ +

+ +

+ +

+ For the resistor with bulk, the wire area is output on the "tW" terminal layer as + the "W" terminal: +

+ +

+ +

+ +

Capacitor extractors (capacitor + and capacitor_with_bulk)

+ +

+ Capacitors are assumed to consist of two "plates" (vertical capacitors). + The plates are on layers P1 and P2. The capacitor is extracted from the area where + these two layers overlap. +

+ +

+ +

+ +

+ The extractor will compute the capacitance from the area of the + overlap and the capacitance per area (F/µm²) value. +

+ + 
area_cap = 1.5e-15
+model_name = "CAP"
+extract_devices(capacitor(model_name, area_cap), { "P1" => metal1, "P2" => metal2 })
+ +

+ The plain capacitor offers two terminals which it outputs on "tA" and "tB" terminal layers. + If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "P1" and "P2" layers + respectively. +

+ +

+ +

+ +

+ +

+ +

+ For the capacitor with bulk, the capacitor area is output on the "tW" terminal layer as + the "W" terminal: +

+ +

+ +

+ +

Diode extractor (diode)

+ +

+ Diodes are assumed to consist of two vertical implant regions (wells, diffusion). + One of the regions is p type ("P" layer) and the other "n" type ("N" layer). + These layers also form the anode (p) and cathode (n) of the diode. +

+ +

+ +

+ +

+ The extractor will compute the capacitance from the area of the + overlap and the capacitance per area (F/µm²) value. +

+ + 
model_name = "DIODE"
+extract_devices(diode(model_name), { "P" => pplus, "N" => nwell })
+ +

+ The diode offers two terminals which it outputs on "tA" and "tC" terminal layers. + If "tA" is not specified, "A" terminals will be written on the "P" layer. + If "tC" is not specified, "C" terminals will be written on the "N" layer. +

+ +

+ +

+ +

+ +

+ +

MOS transistor extractor (mos3 and mos4)

+ +

+ MOS transistors are recognized by their gate ("G" input) and source/drain ("SD" input) regions. + Source and drain needs to be separated from the gate shape. The touching edges of gate and + source/drain regions define the width of the device, the perpendicular dimension the gate length. + Because the separation of source/drain, the computation of gates and the separation of + these for NMOS and PMOS devices, the "G" and "SD" layers are usually derived layers. + As these usually won't participate in the connectivity, it's important to specify the + "tS", "tD", "tG" and "tB" (for MOS4) layers explicitly and redirect the terminal shapes + to layers that really participate in connections. +

+ +

+ +

+ + 
model_name = "PMOS"
+extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" => (active & poly), "W" => nwell,
+                                    "tS" => active, "tD" => active, "tG" => poly, "tB" => nwell })
+ +

+ The MOS3 device produces three terminals which it outputs on "tS", "tG" and "tD" terminal layers (source, + gate and drain respectively): +

+ +

+ +

+ +

+ +

+ +

+ +

+ +

+ The MOS4 device offers one more terminal (bulk) which it writes on "tB". +

+ +

+ +

+ +

Bipolar transistor extractor (bjt3 and bjt4)

+ +

+ There are basically two kind of bipolar transistors: vertical and lateral ones. +

+ +

+ Lateral transistors are formed by implant or diffusion wells creating a intermittent + n/p structure on the wafer. The basic recognition region is the base region. The collector + and emitter regions are inside or overlapping the base region and use the opposite doping + than base: if the base region is n doped, then + collector and emitter regions have to be p doped. The structure then forms a PNP transistor. + KLayout recognizes lateral transistors when the base is partially covered by the collector region. + For lateral transistors, the emitter is defined by the emitter region inside base. The + collector region is defined by collector inside base and outside emitter. +

+ +

+ (lateral PNP transistor) +

+ +

+ Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors + are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed + by taking the collector as the substrate, nwell for the base and pplus implant for the emitter. + KLayout recognizes a vertical bipolar transistor when the base is covered entirely by the + collector or has no collector at all - this means the collector + region can be empty (e.g. bulk). +

+ +

+ (vertical PNP transistor) +

+ +

+ In both cases, there can be multiple emitter regions inside a base island. In this + case, one transistor is extracted for each emitter region. +

+ +

Vertical bipolar transistors

+ +

+ Vertical bipolar transistors take their inputs from "B" (base), "C" (collector) + and "E" (emitter). "C" is optional: +

+ +

+ +

+ +

+ Especially for bipolar devices it's important to device useful terminal output + layers. Typically, the wells and diffusion areas will be connected through "contact", + (not considering the Schottky diodes for now). + So it's a good idea to send the terminals to the contact layer: +

+ + 
model_name = "PNP"
+extract_devices(bjt3(model_name), { "C" => collector, "B" => base, "E" => emitter, 
+                                    "tC" => contact, "tB" => contact, "tE" => contact })
+ +

+ The BJT3 device produces three terminals which it outputs on "tC", "tB" and "tE" terminal layers (collector, + base and emitter respectively): +

+ +

+ +

+ +

+ +

+ +

+ +

+ +

+ If the collector region is empty (e.g. p substrate), the base shape is copied to the "tC" output layer + for the collector terminal. +

+ +

+ The BJT4 device offers one more terminal (substrate) which it writes on "tS". "tS" is + a copy of the emitter shape but connected to the substrate terminal: +

+ +

+ +

+ +

Lateral bipolar transistors

+ +

+ Lateral bipolar transistors also take their inputs from "B" (base), "C" (collector) + and "E" (emitter). For lateral transistors, "C" is not optional and must not fully cover + the base region. Apart from this, the use model for BJT3 and BJT4 extractors is + identical for vertical and lateral transistors. +

+ +

+ A typical lateral transistor is formed by a collector ring and emitter + island inside the base region: +

+ +

+ +

+ +

+ The terminals produced by the bipolar transistor extractor in the lateral case are + the same than for the vertical case, but with a different geometry: +

+ +

+ +

+ +

+ +

+ +

+ +

+ +

+ Again, for BJT4, "tS" is a copy of the emitter shape but connected to the substrate terminal: +

+ +

+ +

+ + + diff --git a/src/lay/lay/doc/manual/lvs_devices.xml b/src/lay/lay/doc/manual/lvs_devices.xml index 48b5c3be9..1ea87704c 100644 --- a/src/lay/lay/doc/manual/lvs_devices.xml +++ b/src/lay/lay/doc/manual/lvs_devices.xml @@ -3,11 +3,9 @@ - LVS Devices + LVS Device Extractors - - - +

Device extractors and device classes

@@ -15,555 +13,22 @@ KLayout provides two concepts for handling device variety:

-
    -
  • Device classes are device categories. There are general categories such as - resistors or MOS transistors. Specific categories can be created to represent specific - incarnations - e.g. NMOS and PMOS devices. Device classes also determine how devices - combine.
    • -
  • Device extractors are objects that analyze layout and produce devices. As for - device classes, there are general device extractors. Each device extractor produces - devices from a specific class.
    • -
- -

Device classes

- -

Resistor

- -

- -

- -

- The plain resistor has two terminals, A and B. It features the following - parameters: -

- -
    -
  • R: The resistance value in Ohm
    • -
  • L: The length in µm
    • -
  • W: The width in µm
    • -
  • A: The area of the resistor area in µm²
    • -
  • P: The perimeter of the resistor area in µm
    • -
- -

- Resistors can combine in parallel or serial fashion. -

- -

- In SPICE, plain resistors are represented by the "R" element. - The API class is . -

- -

Resistor with bulk terminal

- -

- -

- -

- The resistor with bulk terminal is an extension of the plain resistor. - If has the same parameters, but one additional terminal (W) which connects to - the area the resistor sits in (e.g. well or substrate). -

- -

- Resistors with bulk can combine in parallel or serial fashion if their - bulk terminals are connected to the same net. -

- -

- The API class of the resistor with bulk is . -

- -

Capacitor

- -

- -

- -

- The plain capacitor has two terminals, A and B. It features the following - parameters: -

- -
    -
  • C: The capacitance value in Farad
    • -
  • A: The area of the capacitor area in µm²
    • -
  • P: The perimeter of the capacitor area in µm
    • -
- -

- In SPICE, plain capacitors are represented by the "C" element. - The API class is . -

- -

Capacitor with bulk terminal

- -

- -

- -

- The capacitor with bulk terminal is an extension of the plain capacitor. - If has the same parameters, but one additional terminal (W) which connects to - the area the capacitor sits in (e.g. well or substrate). -

- -

- Capacitors with bulk can combine in parallel or serial fashion if their - bulk terminals are connected to the same net. -

- -

- The API class of the capacitor with bulk is . -

- -

Diode

- -

- -

- -

- Diodes have two terminals, A and C for anode and cathode. Diodes - feature the following parameters: -

- -
    -
  • A: The area of the diode in µm²
    • -
  • P: The perimeter of the diode in µm
    • -
- -

- Diodes combine in parallel (A to A and C to C). In this case - their areas and perimeters will add. -

- -

- In SPICE, diodes are represented by the "D" element using the - device class name as the model name. - The API class is . -

- -

MOS transistor

- -

- -

- -

- Three-terminal MOS transistors have terminals S, G and D for source, gate and drain. - S and D are commutable. They feature the following parameters: -

- -
    -
  • W: The gate width in µm
    • -
  • L: The gate (channel) length in µm
    • -
  • AS: The source area in µm²
    • -
  • PS: The source perimeter in µm
    • -
  • AD: The drain area in µm²
    • -
  • PD: The drain perimeter in µm
    • -
- -

- MOS3 transistors combine in parallel when the source/drains and gates are connected - and their gate lengths are identical. - In this case their widths, areas and perimeters will add. -

- -

MOS transistor with bulk

-

- The API class of the three-terminal MOS transistor is . + Device classes are device categories. There are general categories such as + resistors or MOS transistors. Specific categories can be created to represent specific + incarnations - e.g. NMOS and PMOS devices. Device classes also determine how devices + combine.

-

- -

+

Device classes are documented here: .

- The four-terminal transistor is an extension of the three-terminal one and - offers an additional bulk terminal (B). It is probably the most prominent - transistor device as the four-terminal version is compatible with the SPICE - "M" element. + Device extractors are the actual worker objects that analyze layout and produce devices. + As for device classes, there are general device extractors. Each device extractor produces + devices from a specific class.

-

- MOS transistors with bulk can combine in parallel the same way the three-terminal - versions do if their bulk terminals are connected to the same net. -

- -

- In SPICE, MOS4 devices are represented by the "M" element with the - device class name as the model name. - The API class is . -

- -

Bipolar transistor

- -

- -

- -

- The three-terminal bipolar transistor can be either NPN or PNP type. - In KLayout, this device type can represent both lateral and vertical - types. - The parameters are: -

- -
    -
  • AE: The emitter area in µm²
    • -
  • PE: The emitter perimeter in µm
    • -
  • NE: The emitter count (initially 1)
    • -
  • AB: The base area in µm²
    • -
  • PB: The base perimeter in µm
    • -
  • AC: The collector area in µm²
    • -
  • PC: The collector perimeter in µm
    • -
- -

- Upon extraction, multi-emitter versions are extracted as multiple devices - one - for each emitter area - and NE = 1. Bipolar transistors combine when in parallel. - In this case, their emitter parameters AE, PE and NE are added. -

- -

- In SPICE, BJT3 devices are represented by the "Q" element with the - device class name as the model name. - The API class is . -

- -

Bipolar transistor with substrate

- -

- -

- -

- The four-terminal transistor is an extension of the three-terminal one and - offers an additional bulk terminal (S). -

- -

- Bipolar transistors with bulk can combine in parallel the same way the three-terminal - versions do if their bulk terminals are connected to the same net. -

- -

- In SPICE, BJT4 devices are represented by the "Q" element with four nodes and the - device class name as the model name. - The API class is . -

- -

Device extractors

- -

Resistor extractors (resistor - and resistor_with_bulk)

- -

- The resistor extractor assumes a layout which consists of a resistor "wire" - and two caps (contacts). The wire is specified with the layer symbol "R", - the caps are specified with the layer symbol "C": -

- -

- -

- -

- The extractor will compute the resistance from the number of squares - and the sheet resistance. The sheet resistance needs to be given - when creating the extractor: -

- - 
sheet_rho = 0.5
-model_name = "RES"
-extract_devices(resistor(model_name, sheet_rho), { "R" => res_layer, "C" => cap_layer })
- -

- The plain resistor offers two terminals which it outputs on "tA" and "tB" terminal layers. - If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "C" layer. - respectively. -

- -

- -

- -

- -

- -

- For the resistor with bulk, the wire area is output on the "tW" terminal layer as - the "W" terminal: -

- -

- -

- -

Capacitor extractors (capacitor - and capacitor_with_bulk)

- -

- Capacitors are assumed to consist of two "plates" (vertical capacitors). - The plates are on layers P1 and P2. The capacitor is extracted from the area where - these two layers overlap. -

- -

- -

- -

- The extractor will compute the capacitance from the area of the - overlap and the capacitance per area (F/µm²) value. -

- - 
area_cap = 1.5e-15
-model_name = "CAP"
-extract_devices(capacitor(model_name, area_cap), { "P1" => metal1, "P2" => metal2 })
- -

- The plain capacitor offers two terminals which it outputs on "tA" and "tB" terminal layers. - If "tA" or "tB" is not specified, "A" or "B" terminals will be written on the "P1" and "P2" layers - respectively. -

- -

- -

- -

- -

- -

- For the capacitor with bulk, the capacitor area is output on the "tW" terminal layer as - the "W" terminal: -

- -

- -

- -

Diode extractor (diode)

- -

- Diodes are assumed to consist of two vertical implant regions (wells, diffusion). - One of the regions is p type ("P" layer) and the other "n" type ("N" layer). - These layers also form the anode (p) and cathode (n) of the diode. -

- -

- -

- -

- The extractor will compute the capacitance from the area of the - overlap and the capacitance per area (F/µm²) value. -

- - 
model_name = "DIODE"
-extract_devices(diode(model_name), { "P" => pplus, "N" => nwell })
- -

- The diode offers two terminals which it outputs on "tA" and "tC" terminal layers. - If "tA" is not specified, "A" terminals will be written on the "P" layer. - If "tC" is not specified, "C" terminals will be written on the "N" layer. -

- -

- -

- -

- -

- -

MOS transistor extractor (mos3 and mos4)

- -

- MOS transistors are recognized by their gate ("G" input) and source/drain ("SD" input) regions. - Source and drain needs to be separated from the gate shape. The touching edges of gate and - source/drain regions define the width of the device, the perpendicular dimension the gate length. - Because the separation of source/drain, the computation of gates and the separation of - these for NMOS and PMOS devices, the "G" and "SD" layers are usually derived layers. - As these usually won't participate in the connectivity, it's important to specify the - "tS", "tD", "tG" and "tB" (for MOS4) layers explicitly and redirect the terminal shapes - to layers that really participate in connections. -

- -

- -

- - 
model_name = "PMOS"
-extract_devices(mos4(model_name), { "SD" => (active - poly) & pplus, "G" => (active & poly), "W" => nwell,
-                                    "tS" => active, "tD" => active, "tG" => poly, "tB" => nwell })
- -

- The MOS3 device produces three terminals which it outputs on "tS", "tG" and "tD" terminal layers (source, - gate and drain respectively): -

- -

- -

- -

- -

- -

- -

- -

- The MOS4 device offers one more terminal (bulk) which it writes on "tB". -

- -

- -

- -

Bipolar transistor extractor (bjt3 and bjt4)

- -

- There are basically two kind of bipolar transistors: vertical and lateral ones. -

- -

- Lateral transistors are formed by implant or diffusion wells creating a intermittent - n/p structure on the wafer. The basic recognition region is the base region. The collector - and emitter regions are inside or overlapping the base region and use the opposite doping - than base: if the base region is n doped, then - collector and emitter regions have to be p doped. The structure then forms a PNP transistor. - KLayout recognizes lateral transistors when the base is partially covered by the collector region. - For lateral transistors, the emitter is defined by the emitter region inside base. The - collector region is defined by collector inside base and outside emitter. -

- -

- (lateral PNP transistor) -

- -

- Vertical transistors are formed by a stack of n/p wells. Sometimes vertical transistors - are formed as parasitic devices in standard CMOS processes. A PNP transistor can be formed - by taking the collector as the substrate, nwell for the base and pplus implant for the emitter. - KLayout recognizes a vertical bipolar transistor when the base is covered entirely by the - collector or has no collector at all - this means the collector - region can be empty (e.g. bulk). -

- -

- (vertical PNP transistor) -

- -

- In both cases, there can be multiple emitter regions inside a base island. In this - case, one transistor is extracted for each emitter region. -

- -

Vertical bipolar transistors

- -

- Vertical bipolar transistors take their inputs from "B" (base), "C" (collector) - and "E" (emitter). "C" is optional: -

- -

- -

- -

- Especially for bipolar devices it's important to device useful terminal output - layers. Typically, the wells and diffusion areas will be connected through "contact", - (not considering the Schottky diodes for now). - So it's a good idea to send the terminals to the contact layer: -

- - 
model_name = "PNP"
-extract_devices(bjt3(model_name), { "C" => collector, "B" => base, "E" => emitter, 
-                                    "tC" => contact, "tB" => contact, "tE" => contact })
- -

- The BJT3 device produces three terminals which it outputs on "tC", "tB" and "tE" terminal layers (collector, - base and emitter respectively): -

- -

- -

- -

- -

- -

- -

- -

- If the collector region is empty (e.g. p substrate), the base shape is copied to the "tC" output layer - for the collector terminal. -

- -

- The BJT4 device offers one more terminal (substrate) which it writes on "tS". "tS" is - a copy of the emitter shape but connected to the substrate terminal: -

- -

- -

- -

Lateral bipolar transistors

- -

- Lateral bipolar transistors also take their inputs from "B" (base), "C" (collector) - and "E" (emitter). For lateral transistors, "C" is not optional and must not fully cover - the base region. Apart from this, the use model for BJT3 and BJT4 extractors is - identical for vertical and lateral transistors. -

- -

- A typical lateral transistor is formed by a collector ring and emitter - island inside the base region: -

- -

- -

- -

- The terminals produced by the bipolar transistor extractor in the lateral case are - the same than for the vertical case, but with a different geometry: -

- -

- -

- -

- -

- -

- -

- -

- Again, for BJT4, "tS" is a copy of the emitter shape but connected to the substrate terminal: -

- -

- -

+

Device extractors are documented here: .

 diff --git a/src/lay/lay/doc/manual/lvs_io.xml b/src/lay/lay/doc/manual/lvs_io.xml new file mode 100644 index 000000000..a5a76e174 --- /dev/null +++ b/src/lay/lay/doc/manual/lvs_io.xml @@ -0,0 +1,240 @@ + + + + + + LVS Input/Output + + + + + + +

+ LVS (and also DRC as far as netlist extraction is concerned) provides interfaces + to write and read netlists/schematics, annotated layout and LVS results. + There are three major categories of I/O: +

+ +
    +
  • Netlist: this is the plain circuit information. With subcircuit this + forms a hierarchical netlist. Currently, the format available to import and export + netlists is a certain SPICE netlist flavor. It's possible to customize the reading + and writing process to achieve some flexibility. +
    • +
  • Layout-to-netlist database (L2N DB): also called extracted netlist or annotated layout. + This is the netlist taken from the original layout together with the corresponding shapes. + This database allows reconstructing a net geometrically as far as non-device shapes + are involved. Devices are abstracted by their terminal geometries. +
    • +
  • LVS result database (LVS DB): this is the L2N database plus the reference netlist + and a "cross reference": a list of paired circuits, nets, devices, pins and subcircuits + and status information. The cross-reference is both a lookup table and a debugging + aid. +
    • +
+ +

Writing netlists

+ +

+ You can write a netlist file to supply netlists for (functional) simulators for example. + Within LVS scripts, the global "target_netlist" statement triggers writing of a netlist + (see target_netlist for details). +

+ + 
target_netlist("output.cir", write_spice, "Created by KLayout")
+ +

+ This statement can basically appear anywhere in the LVS script. The netlist will + written after the script has executed successfully. The first argument is + the file's path (by default relative to the original layout file). The second + argument is the "writer". "write_spice" creates a netlist writer writing SPICE + format with a limited degree of flexbility. See below for customizing the writer. + The third argument finally is an (optional) comment which will be written into + the netlist as a header. +

+ +

+ The "write_spice" configuration function has two options: +

+ + 
write_spice(use_net_names, with_comments)
+ +

+ Both options are boolean values. If true and present, the first option will make + the writer use the real net's names instead of numerical IDs. If true and present, + "with_comments" will embed debug comments into the netlist showing instance + locations, pin names etc. +

+ +

+ Further customization can be achieved by providing an explicit SPICE writer + with a delegate (see ). For + doing so, subclass NetlistSpiceWriterDelegate and reimplement one + or several of the methods provided for reimplementation. Those are + , + and + . +

+ +

+ Here is an example that supplied subcircuit models rather than + device elements: +

+ + 
# Write extracted netlist to extracted.cir using a special
+# writer delegate
+
+# This delegate makes the writer emit subcicuit calls instead of 
+# standard elements for the devices
+class SubcircuitModels < RBA::NetlistSpiceWriterDelegate
+
+  def write_header
+    emit_line(".INCLUDE 'models.cir'")
+  end
+
+  def write_device(device)
+    str = "X" + device.expanded_name
+    device_class = device.device_class
+    device_class.terminal_definitions.each do |td|
+      str += " " + net_to_string(device.net_for_terminal(td.id))
+    end
+    str += " " + device_class.name
+    str += " PARAMS:"
+    device_class.parameter_definitions.each do |pd|
+      str += " " + pd.name + ("=%.12g" % device.parameter(pd.id))
+    end
+    emit_line(str)
+  end      
+
+end
+
+# Prepare a writer using the new delegate
+custom_spice_writer = RBA::NetlistSpiceWriter::new(SubcircuitModels::new)
+custom_spice_writer.use_net_names= true
+custom_spice_writer.with_comments = false
+
+# The declaration of netlist production using the new custom writer
+target_netlist("extracted.cir", custom_spice_writer, "Extracted by KLayout")
+ +

+ This script will produce the following netlist for the simple inverter + from the LVS introduction. Instead of printing "M" elements - which is the + default - subcircuit calls are produced. This allows putting more elaborate + models into subcircuits. The device class name addresses these model + subcircuits: +

+ + 
* Extracted by KLayout
+.INCLUDE 'models.cir'
+
+.SUBCKT INVERTER
+X$1 VDD IN OUT NWELL PMOS PARAMS: L=0.25 W=1.5 AS=0.675 AD=0.675 PS=3.9 PD=3.9
+X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.9 AS=0.405 AD=0.405 PS=2.7
++ PD=2.7
+.ENDS INVERTER
+ +

+ Netlists can be written directly from the netlist object. Within the script, the + netlist object can be obtained with the netlist function. + This function will first trigger a netlist extraction unless this was done already and + return a object. Use to + write this netlist object then. Unlike "target_netlist", this method is executed immediately and + this way, a single netlist can be written to multiple files in different flavours. +

+ +

Reading netlists

+ +

+ The main use case for reading netlists is for comparison in LVS. + Reference netlists are read with the "schematic" function + (see schematic): +

+ + 
schematic("inverter.cir")
+ +

+ Currently SPICE is understood with some limitations: +

+ +
    +
  • Parametrized circuits are not permitted except for device subcircuits + (with a delegate)
    • +
  • Only a subset of elements is implemented by default. These are + "M" (gives "MOS4" device classes), "Q" (gives BJT3 or BJT4 device + classes), "R" (gives Resistor device classes), "C" (gives + Capacitor device classes) and "D" (gives diode device classes).
    • +
+ +

+ As for the SPICE reader, a delegate can be provided to customize the reader. + For doing so, subclass the + class and reimplement the methods provided. These are: + , + , + and + +

+ +

+ This example customizes a reader to pull MOS devices from + subcircuit models rather than from "M" elements. Basically this + customization does the opposite part of the writer customization + before (only for MOS devices). +

+ + 
# Provides a SPICE netlist reader delegate which turns
+# some subcircuit models (for subcircuits NMOS and PMOS)
+# into devices
+
+class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
+
+  # says we want to catch these subcircuits as devices
+  def wants_subcircuit(name)
+    name == "NMOS" || name == "PMOS"
+  end
+
+  # translate the element
+  def element(circuit, el, name, model, value, nets, params)
+
+    if el != "X"
+      # all other elements are left to the standard implementation
+      return super
+    end
+
+    if nets.size != 4
+      error("Subcircuit #{model} needs four nodes")
+    end
+
+    # provide a device class
+    cls = circuit.netlist.device_class_by_name(model)
+    if ! cls
+      cls = RBA::DeviceClassMOS4Transistor::new
+      cls.name = model
+      circuit.netlist.add(cls)
+    end
+
+    # create a device
+    device = circuit.create_device(cls, name)
+
+    # and configure the device
+    [ "S", "G", "D", "B" ].each_with_index do |t,index|
+      device.connect_terminal(t, nets[index])
+    end
+    params.each do |p,value|
+      device.set_parameter(p, value)
+    end
+
+  end
+
+end
+
+# Instantiate a reader using the new delegate
+reader = RBA::NetlistSpiceReader::new(SubcircuitModelsReader::new)
+
+# Import the schematic with this reader
+schematic("inv_xmodels.cir", reader)
+ + + + diff --git a/src/lay/lay/doc/manual/lvs_tweaks.xml b/src/lay/lay/doc/manual/lvs_tweaks.xml new file mode 100644 index 000000000..b23365003 --- /dev/null +++ b/src/lay/lay/doc/manual/lvs_tweaks.xml @@ -0,0 +1,17 @@ + + + + + + LVS Device Classes + + + + + +

+ LVS (and also DRC as far as netlist extraction is concerned) provides + +

+ + diff --git a/src/lay/lay/layHelpResources.qrc b/src/lay/lay/layHelpResources.qrc index 252839eac..643c51236 100644 --- a/src/lay/lay/layHelpResources.qrc +++ b/src/lay/lay/layHelpResources.qrc @@ -174,6 +174,11 @@ doc/manual/lvs_intro.xml doc/manual/lvs_browser.png doc/manual/lvs_devices.xml + doc/manual/lvs_device_classes.xml + doc/manual/lvs_device_extractors.xml + doc/manual/lvs_io.xml + doc/manual/lvs_compare.xml + doc/manual/lvs_tweaks.xml doc/manual/inv.png doc/manual/inv_no_transistors.png doc/manual/inv_transistors.png