klayout/testdata/lvs/ringo_mixed_hierarchy.lvsdb

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#%lvsdb-klayout
# Layout
layout(
top(RINGO)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
layer(l3 '1/0')
layer(l4 '5/0')
layer(l8 '8/0')
layer(l11 '9/0')
layer(l12 '10/0')
layer(l13 '11/0')
layer(l7)
layer(l2)
layer(l9)
layer(l6)
layer(l10)
# Mask layer connectivity
connect(l3 l3 l9)
connect(l4 l4 l8)
connect(l8 l4 l8 l11 l2 l9 l6 l10)
connect(l11 l8 l11 l12)
connect(l12 l11 l12 l13)
connect(l13 l12 l13)
connect(l7 l7)
connect(l2 l8 l2)
connect(l9 l3 l8 l9)
connect(l6 l8 l6)
connect(l10 l8 l10)
# Global nets and connectivity
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Device abstracts section
# Device abstracts list the pin shapes of the devices.
device(D$PMOS PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (450 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$1 PMOS
terminal(S
rect(l2 (-575 -750) (450 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$PMOS$2 PMOS
terminal(S
rect(l2 (-550 -750) (425 1500))
)
terminal(G
rect(l4 (-125 -750) (250 1500))
)
terminal(D
rect(l2 (125 -750) (425 1500))
)
terminal(B
rect(l3 (-125 -750) (250 1500))
)
)
device(D$NMOS NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (450 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$1 NMOS
terminal(S
rect(l6 (-575 -475) (450 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
device(D$NMOS$2 NMOS
terminal(S
rect(l6 (-550 -475) (425 950))
)
terminal(G
rect(l4 (-125 -475) (250 950))
)
terminal(D
rect(l6 (125 -475) (425 950))
)
terminal(B
rect(l7 (-125 -475) (250 950))
)
)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INVX1
# Circuit boundary
rect((-100 400) (2000 7600))
# Nets with their geometries
net(1 name(VDD)
rect(l8 (410 6260) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l11 (-240 -240) (300 1400))
rect(l11 (-650 300) (1800 800))
rect(l11 (-1450 -1100) (300 300))
rect(l11 (300 400) (0 0))
rect(l2 (-650 -2150) (425 1500))
)
net(2 name(OUT)
rect(l8 (1110 5160) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -4120) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -790) (300 4790))
rect(l11 (-150 -2500) (0 0))
rect(l2 (-225 1050) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(3 name(VSS)
rect(l8 (410 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-240 -1300) (300 1360))
rect(l11 (-650 -2160) (1800 800))
rect(l11 (-850 -400) (0 0))
rect(l6 (-650 860) (425 950))
)
net(4
rect(l3 (-100 4500) (2000 3500))
)
net(5 name(IN)
rect(l4 (725 2860) (250 1940))
rect(l4 (-525 -1850) (300 300))
rect(l4 (-25 -1840) (250 1450))
rect(l4 (-250 1940) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l8 (-465 -3790) (180 180))
rect(l11 (-90 -90) (0 0))
rect(l11 (-150 -150) (300 300))
)
net(6 name(SUBSTRATE))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4)
pin(5 name(IN))
pin(6 name(SUBSTRATE))
# Devices and their connections
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device(1 D$PMOS$2
location(850 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.6375)
param(PS 3.85)
param(PD 3.85)
terminal(S 1)
terminal(G 5)
terminal(D 2)
terminal(B 4)
)
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device(2 D$NMOS$2
location(850 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.40375)
param(PS 2.75)
param(PD 2.75)
terminal(S 3)
terminal(G 5)
terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Circuit boundary
rect((0 350) (25800 7650))
# Nets with their geometries
net(1 name('B,FB')
rect(l4 (3225 2860) (250 1940))
rect(l4 (-345 -950) (300 300))
rect(l4 (-205 650) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l4 (-250 -5390) (250 1450))
rect(l8 (-285 1050) (180 180))
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rect(l11 (-240 -240) (300 300))
rect(l11 (-130 -150) (0 0))
rect(l11 (18450 -1050) (900 300))
rect(l11 (-1390 590) (320 320))
rect(l11 (-18460 -320) (320 320))
rect(l12 (17880 -260) (200 200))
rect(l12 (-18340 -200) (200 200))
rect(l13 (100 -300) (17740 400))
rect(l13 (-17920 -200) (0 0))
rect(l13 (17920 -200) (400 400))
rect(l13 (-18540 -400) (400 400))
)
net(2 name('A,ENABLE')
rect(l4 (2525 2860) (250 1940))
rect(l4 (-325 -1850) (300 300))
rect(l4 (-225 -1840) (250 1450))
rect(l4 (-250 1940) (250 2000))
rect(l4 (-250 -2000) (250 2000))
rect(l8 (-265 -3790) (180 180))
rect(l11 (-240 -240) (300 300))
rect(l11 (-150 -150) (0 0))
rect(l11 (-160 -160) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(3 name(VDD)
rect(l3 (1700 4500) (2600 3500))
rect(l3 (-3800 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (23300 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-22890 -2840) (180 180))
rect(l8 (-180 920) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-1980 870) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-21840 -1290) (300 1700))
rect(l11 (-1350 0) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l11 (-100 50) (0 0))
rect(l11 (-2350 -450) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23400 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (550 -400) (600 800))
rect(l2 (-23025 -2550) (450 1500))
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rect(l9 (-2275 -450) (500 1500))
rect(l9 (22900 -1500) (500 1500))
)
net(4
rect(l8 (3610 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1580 3760) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (-180 -730) (180 180))
rect(l8 (1220 920) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
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polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
rect(l11 (-110 1390) (300 1400))
rect(l11 (0 -1550) (610 300))
polygon(l11 (-2500 1250) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
rect(l11 (-1890 600) (300 1400))
rect(l11 (1100 -1700) (300 300))
rect(l11 (-300 0) (300 1400))
rect(l2 (-1750 -1450) (425 1500))
rect(l2 (950 -1500) (425 1500))
rect(l6 (-425 -4890) (425 950))
)
net(5 name($7)
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rect(l11 (5550 2950) (900 300))
)
net(6 name($8)
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rect(l11 (7350 2950) (900 300))
)
net(7 name($9)
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rect(l11 (9150 2950) (900 300))
)
net(8 name($10)
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rect(l11 (10950 2950) (900 300))
)
net(9 name($11)
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rect(l11 (12750 2950) (900 300))
)
net(10 name($12)
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rect(l11 (14550 2950) (900 300))
)
net(11 name($13)
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rect(l11 (16350 2950) (900 300))
)
net(12 name($14)
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rect(l11 (18150 2950) (900 300))
)
net(13 name($15)
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rect(l11 (19950 2950) (900 300))
)
net(14 name(OUT)
rect(l11 (23440 3840) (320 320))
rect(l12 (-260 -260) (200 200))
rect(l13 (-100 -100) (0 0))
rect(l13 (-200 -200) (400 400))
)
net(15 name($21)
rect(l6 (2775 1660) (450 950))
)
net(16 name(VSS)
rect(l8 (2210 1770) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-1280 -890) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (23220 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (-22540 -40) (300 1360))
rect(l11 (-650 -2160) (2400 800))
rect(l11 (-1150 -400) (0 0))
rect(l11 (-100 50) (0 0))
rect(l11 (-1900 -400) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (23850 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l6 (-23700 460) (425 950))
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rect(l10 (-1575 -2210) (500 1500))
rect(l10 (22900 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
pin(1 name('B,FB'))
pin(2 name('A,ENABLE'))
pin(3 name(VDD))
pin(14 name(OUT))
pin(16 name(VSS))
# Devices and their connections
device(1 D$PMOS
location(2650 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.6375)
param(AD 0.3375)
param(PS 3.85)
param(PD 1.95)
terminal(S 4)
terminal(G 2)
terminal(D 3)
terminal(B 3)
)
device(2 D$PMOS$1
location(3350 5800)
param(L 0.25)
param(W 1.5)
param(AS 0.3375)
param(AD 0.6375)
param(PS 1.95)
param(PD 3.85)
terminal(S 3)
terminal(G 1)
terminal(D 4)
terminal(B 3)
)
device(3 D$NMOS
location(2650 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.40375)
param(AD 0.21375)
param(PS 2.75)
param(PD 1.4)
terminal(S 16)
terminal(G 2)
terminal(D 15)
terminal(B 16)
)
device(4 D$NMOS$1
location(3350 2135)
param(L 0.25)
param(W 0.95)
param(AS 0.21375)
param(AD 0.40375)
param(PS 1.4)
param(PD 2.75)
terminal(S 15)
terminal(G 1)
terminal(D 4)
terminal(B 16)
)
# Subcircuits and their connections
circuit(1 INVX1 location(22200 0)
pin(0 3)
pin(1 14)
pin(2 16)
pin(3 3)
pin(4 1)
pin(5 16)
)
circuit(2 INVX1 location(20400 0)
pin(0 3)
pin(1 1)
pin(2 16)
pin(3 3)
pin(4 13)
pin(5 16)
)
circuit(8 INVX1 location(4200 0)
pin(0 3)
pin(1 5)
pin(2 16)
pin(3 3)
pin(4 4)
pin(5 16)
)
circuit(9 INVX1 location(6000 0)
pin(0 3)
pin(1 6)
pin(2 16)
pin(3 3)
pin(4 5)
pin(5 16)
)
circuit(10 INVX1 location(7800 0)
pin(0 3)
pin(1 7)
pin(2 16)
pin(3 3)
pin(4 6)
pin(5 16)
)
circuit(11 INVX1 location(9600 0)
pin(0 3)
pin(1 8)
pin(2 16)
pin(3 3)
pin(4 7)
pin(5 16)
)
circuit(12 INVX1 location(11400 0)
pin(0 3)
pin(1 9)
pin(2 16)
pin(3 3)
pin(4 8)
pin(5 16)
)
circuit(13 INVX1 location(13200 0)
pin(0 3)
pin(1 10)
pin(2 16)
pin(3 3)
pin(4 9)
pin(5 16)
)
circuit(14 INVX1 location(15000 0)
pin(0 3)
pin(1 11)
pin(2 16)
pin(3 3)
pin(4 10)
pin(5 16)
)
circuit(15 INVX1 location(16800 0)
pin(0 3)
pin(1 12)
pin(2 16)
pin(3 3)
pin(4 11)
pin(5 16)
)
circuit(16 INVX1 location(18600 0)
pin(0 3)
pin(1 13)
pin(2 16)
pin(3 3)
pin(4 12)
pin(5 16)
)
)
)
# Reference netlist
reference(
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
circuit(INVX1
# Nets
net(1 name(VDD))
net(2 name(OUT))
net(3 name(VSS))
net(4 name(NWELL))
net(5 name(IN))
net(6 name(BULK))
# Outgoing pins and their connections to nets
pin(1 name(VDD))
pin(2 name(OUT))
pin(3 name(VSS))
pin(4 name(NWELL))
pin(5 name(IN))
pin(6 name(BULK))
# Devices and their connections
device(1 PMOS
name($1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 1)
terminal(G 5)
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terminal(D 2)
terminal(B 4)
)
device(2 NMOS
name($2)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 3)
terminal(G 5)
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terminal(D 2)
terminal(B 6)
)
)
circuit(RINGO
# Nets
net(1 name(VSS))
net(2 name(VDD))
net(3 name(FB))
net(4 name(ENABLE))
net(5 name(OUT))
net(6 name('1'))
net(7 name('2'))
net(8 name('3'))
net(9 name('4'))
net(10 name('5'))
net(11 name('6'))
net(12 name('7'))
net(13 name('8'))
net(14 name('9'))
net(15 name('10'))
net(16 name($1.1))
# Outgoing pins and their connections to nets
pin(1 name(VSS))
pin(2 name(VDD))
pin(3 name(FB))
pin(4 name(ENABLE))
pin(5 name(OUT))
# Devices and their connections
device(1 PMOS
name($1.$1)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 2)
terminal(G 4)
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terminal(D 6)
terminal(B 2)
)
device(2 PMOS
name($1.$2)
param(L 0.25)
param(W 1.5)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 2)
terminal(G 3)
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terminal(D 6)
terminal(B 2)
)
device(3 NMOS
name($1.$3)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 1)
terminal(G 4)
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terminal(D 16)
terminal(B 1)
)
device(4 NMOS
name($1.$4)
param(L 0.25)
param(W 0.95)
param(AS 0)
param(AD 0)
param(PS 0)
param(PD 0)
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terminal(S 16)
terminal(G 3)
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terminal(D 6)
terminal(B 1)
)
# Subcircuits and their connections
circuit(2 INVX1 name($2)
pin(0 2)
pin(1 7)
pin(2 1)
pin(3 2)
pin(4 6)
pin(5 1)
)
circuit(3 INVX1 name($3)
pin(0 2)
pin(1 8)
pin(2 1)
pin(3 2)
pin(4 7)
pin(5 1)
)
circuit(4 INVX1 name($4)
pin(0 2)
pin(1 9)
pin(2 1)
pin(3 2)
pin(4 8)
pin(5 1)
)
circuit(5 INVX1 name($5)
pin(0 2)
pin(1 10)
pin(2 1)
pin(3 2)
pin(4 9)
pin(5 1)
)
circuit(6 INVX1 name($6)
pin(0 2)
pin(1 11)
pin(2 1)
pin(3 2)
pin(4 10)
pin(5 1)
)
circuit(7 INVX1 name($7)
pin(0 2)
pin(1 12)
pin(2 1)
pin(3 2)
pin(4 11)
pin(5 1)
)
circuit(8 INVX1 name($8)
pin(0 2)
pin(1 13)
pin(2 1)
pin(3 2)
pin(4 12)
pin(5 1)
)
circuit(9 INVX1 name($9)
pin(0 2)
pin(1 14)
pin(2 1)
pin(3 2)
pin(4 13)
pin(5 1)
)
circuit(10 INVX1 name($10)
pin(0 2)
pin(1 15)
pin(2 1)
pin(3 2)
pin(4 14)
pin(5 1)
)
circuit(11 INVX1 name($11)
pin(0 2)
pin(1 3)
pin(2 1)
pin(3 2)
pin(4 15)
pin(5 1)
)
circuit(12 INVX1 name($12)
pin(0 2)
pin(1 5)
pin(2 1)
pin(3 2)
pin(4 3)
pin(5 1)
)
)
)
# Cross reference
xref(
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
net(5 5 match)
net(2 2 match)
net(6 6 match)
net(1 1 match)
net(3 3 match)
pin(3 3 match)
pin(4 4 match)
pin(1 1 match)
pin(5 5 match)
pin(0 0 match)
pin(2 2 match)
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device(2 2 match)
device(1 1 match)
)
)
circuit(RINGO RINGO match
xref(
net(15 16 match)
net(4 6 match)
net(13 15 match)
net(5 7 match)
net(6 8 match)
net(7 9 match)
net(8 10 match)
net(9 11 match)
net(10 12 match)
net(11 13 match)
net(12 14 match)
net(2 4 match)
net(1 3 match)
net(14 5 match)
net(3 2 match)
net(16 1 match)
pin(1 3 match)
pin(0 2 match)
pin(3 4 match)
pin(2 1 match)
pin(4 0 match)
device(3 3 match)
device(4 4 match)
device(1 1 match)
device(2 2 match)
circuit(8 2 match)
circuit(9 3 match)
circuit(10 4 match)
circuit(11 5 match)
circuit(12 6 match)
circuit(13 7 match)
circuit(14 8 match)
circuit(15 9 match)
circuit(16 10 match)
circuit(2 11 match)
circuit(1 12 match)
)
)
)