mirror of https://github.com/KLayout/klayout.git
Added test for mixed-hierarchy LVS case.
This commit is contained in:
Matthias Koefferlein
parent
3ae848bff4
commit
3a93bc2162
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@ -189,12 +189,14 @@ X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.9 AS=0.405 AD=0.405 PS=2.7
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class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
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# implements the delegate interface:
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# says we want to catch these subcircuits as devices
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def wants_subcircuit(name)
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name == "NMOS" || name == "PMOS"
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end
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# translate the element
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# implements the delegate interface:
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# take and translate the element
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def element(circuit, el, name, model, value, nets, params)
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if el != "X"
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@ -221,9 +223,13 @@ class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
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[ "S", "G", "D", "B" ].each_with_index do |t,index|
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device.connect_terminal(t, nets[index])
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end
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params.each do |p,value|
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device.set_parameter(p, value)
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end
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# parameters in the model are given in micrometer units, so
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# we need to translate the parameter values from SI to um values:
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device.set_parameter("W", (params["W"] || 0.0) * 1e6)
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device.set_parameter("L", (params["L"] || 0.0) * 1e6)
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return true
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end
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@ -138,3 +138,8 @@ TEST(13_simple_ringo_device_subcircuits)
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{
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run_test (_this, "ringo_device_subcircuits", "ringo.gds");
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}
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TEST(14_simple_ringo_mixed_hierarchy)
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{
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run_test (_this, "ringo_mixed_hierarchy", "ringo_mixed_hierarchy.gds");
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}
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@ -44,8 +44,8 @@ class SubcircuitModelsReader < RBA::NetlistSpiceReaderDelegate
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# parameters in the model are given in micrometer units, so
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# we need to translate the parameter values from SI to um values:
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device.set_parameter("W", (params["W"] || 1.0e-6) * 1e6)
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device.set_parameter("L", (params["L"] || 1.0e-6) * 1e6)
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device.set_parameter("W", (params["W"] || 0.0) * 1e6)
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device.set_parameter("L", (params["L"] || 0.0) * 1e6)
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return true
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@ -0,0 +1,64 @@
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* Extracted by KLayout
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* cell RINGO
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* pin B,FB
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* pin A,ENABLE
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* pin VDD
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* pin OUT
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* pin VSS
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.SUBCKT RINGO 1 2 3 14 16
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* net 1 B,FB
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* net 2 A,ENABLE
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* net 3 VDD
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* net 14 OUT
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* net 16 VSS
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* cell instance $1 r0 *1 22.2,0
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X$1 3 14 16 3 1 16 INVX1
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* cell instance $2 r0 *1 20.4,0
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X$2 3 1 16 3 13 16 INVX1
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* cell instance $8 r0 *1 4.2,0
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X$8 3 5 16 3 4 16 INVX1
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* cell instance $9 r0 *1 6,0
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X$9 3 6 16 3 5 16 INVX1
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* cell instance $10 r0 *1 7.8,0
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X$10 3 7 16 3 6 16 INVX1
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* cell instance $11 r0 *1 9.6,0
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X$11 3 8 16 3 7 16 INVX1
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* cell instance $12 r0 *1 11.4,0
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X$12 3 9 16 3 8 16 INVX1
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* cell instance $13 r0 *1 13.2,0
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X$13 3 10 16 3 9 16 INVX1
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* cell instance $14 r0 *1 15,0
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X$14 3 11 16 3 10 16 INVX1
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* cell instance $15 r0 *1 16.8,0
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X$15 3 12 16 3 11 16 INVX1
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* cell instance $16 r0 *1 18.6,0
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X$16 3 13 16 3 12 16 INVX1
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* device instance $1 r0 *1 2.65,5.8 PMOS
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M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
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* device instance $2 r0 *1 3.35,5.8 PMOS
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M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
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* device instance $3 r0 *1 2.65,2.135 NMOS
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M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
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* device instance $4 r0 *1 3.35,2.135 NMOS
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M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
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.ENDS RINGO
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* cell INVX1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin IN
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* pin SUBSTRATE
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.SUBCKT INVX1 1 2 3 4 5 6
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* net 1 VDD
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* net 2 OUT
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* net 3 VSS
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* net 5 IN
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* net 6 SUBSTRATE
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* device instance $1 r0 *1 0.85,2.135 NMOS
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M$1 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
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* device instance $2 r0 *1 0.85,5.8 PMOS
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M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
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.ENDS INVX1
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Binary file not shown.
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@ -0,0 +1,76 @@
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("ringo.cir")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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align
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compare
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@ -0,0 +1,872 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
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layer(l13 '11/0')
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l2 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$2 PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (450 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l6 (-575 -475) (450 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$2 NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INVX1
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# Circuit boundary
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rect((-100 400) (2000 7600))
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# Nets with their geometries
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net(1 name(VDD)
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rect(l8 (410 6260) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-240 -240) (300 1400))
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rect(l11 (-650 300) (1800 800))
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rect(l11 (-1450 -1100) (300 300))
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rect(l11 (299 399) (2 2))
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rect(l2 (-651 -2151) (425 1500))
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)
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net(2 name(OUT)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -4120) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -790) (300 4790))
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rect(l11 (-151 -2501) (2 2))
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rect(l2 (-226 1049) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(3 name(VSS)
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rect(l8 (410 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -1300) (300 1360))
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rect(l11 (-650 -2160) (1800 800))
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rect(l11 (-851 -401) (2 2))
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rect(l6 (-651 859) (425 950))
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)
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net(4
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rect(l3 (-100 4500) (2000 3500))
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)
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net(5 name(IN)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-525 -1850) (300 300))
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rect(l4 (-25 -1840) (250 1450))
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rect(l4 (-250 1940) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l8 (-465 -3790) (180 180))
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rect(l11 (-91 -91) (2 2))
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rect(l11 (-151 -151) (300 300))
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)
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net(6 name(SUBSTRATE))
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# Outgoing pins and their connections to nets
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pin(1 name(VDD))
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pin(2 name(OUT))
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pin(3 name(VSS))
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pin(4)
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pin(5 name(IN))
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pin(6 name(SUBSTRATE))
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# Devices and their connections
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device(1 D$NMOS$2
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.40375)
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param(PS 2.75)
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param(PD 2.75)
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terminal(S 3)
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terminal(G 5)
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terminal(D 2)
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terminal(B 6)
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)
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device(2 D$PMOS$2
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.6375)
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param(PS 3.85)
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param(PD 3.85)
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terminal(S 1)
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terminal(G 5)
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terminal(D 2)
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terminal(B 4)
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)
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)
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circuit(RINGO
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# Circuit boundary
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rect((0 350) (25800 7650))
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# Nets with their geometries
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net(1 name('B,FB')
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rect(l4 (3225 2860) (250 1940))
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rect(l4 (-345 -950) (300 300))
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rect(l4 (-205 650) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-285 1050) (180 180))
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rect(l8 (19340 -1080) (180 180))
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rect(l11 (-19760 660) (300 300))
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rect(l11 (-131 -151) (2 2))
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rect(l11 (18449 -1051) (900 300))
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rect(l11 (-1390 590) (320 320))
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rect(l11 (-18460 -320) (320 320))
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rect(l12 (17880 -260) (200 200))
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rect(l12 (-18340 -200) (200 200))
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rect(l13 (100 -300) (17740 400))
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rect(l13 (-17921 -201) (2 2))
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rect(l13 (17919 -201) (400 400))
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rect(l13 (-18540 -400) (400 400))
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rect(l2 (17895 850) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(2 name('A,ENABLE')
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rect(l4 (2525 2860) (250 1940))
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rect(l4 (-325 -1850) (300 300))
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rect(l4 (-225 -1840) (250 1450))
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rect(l4 (-250 1940) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l8 (-265 -3790) (180 180))
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rect(l11 (-240 -240) (300 300))
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rect(l11 (-151 -151) (2 2))
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rect(l11 (-161 -161) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-101 -101) (2 2))
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rect(l13 (-201 -201) (400 400))
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)
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net(3 name(VDD)
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rect(l3 (1700 4500) (2600 3500))
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rect(l3 (-3800 -3500) (1400 3500))
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rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-22890 -2840) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-1980 870) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21840 -1290) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l11 (-102 48) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l2 (-23025 -2550) (450 1500))
|
||||
rect(l2 (1275 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (1375 -1500) (425 1500))
|
||||
rect(l2 (3175 -1500) (425 1500))
|
||||
rect(l2 (-2225 -1500) (425 1500))
|
||||
rect(l9 (-20175 -450) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (3610 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (920 -2880) (180 180))
|
||||
polygon(l11 (-1340 -1480) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
rect(l11 (0 -1550) (610 300))
|
||||
polygon(l11 (-2500 1250) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-1890 600) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l2 (-1750 -1450) (425 1500))
|
||||
rect(l2 (950 -1500) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(5
|
||||
rect(l8 (6510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(6
|
||||
rect(l8 (8310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(7
|
||||
rect(l8 (10110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(8
|
||||
rect(l8 (11910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(9
|
||||
rect(l8 (13710 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(10
|
||||
rect(l8 (15510 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(11
|
||||
rect(l8 (17310 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(12
|
||||
rect(l8 (19110 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(13
|
||||
rect(l8 (20910 3010) (180 180))
|
||||
rect(l11 (-1140 -240) (900 300))
|
||||
rect(l2 (-1275 1800) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(14 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
rect(l2 (-625 850) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(15
|
||||
rect(l6 (2775 1660) (450 950))
|
||||
)
|
||||
net(16 name(VSS)
|
||||
rect(l8 (2210 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1280 -890) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-22540 -40) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l11 (-102 48) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l6 (-23700 460) (425 950))
|
||||
rect(l6 (1975 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (1375 -950) (425 950))
|
||||
rect(l6 (3175 -950) (425 950))
|
||||
rect(l6 (-2225 -950) (425 950))
|
||||
rect(l10 (-20175 -2210) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('B,FB'))
|
||||
pin(2 name('A,ENABLE'))
|
||||
pin(3 name(VDD))
|
||||
pin(14 name(OUT))
|
||||
pin(16 name(VSS))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(2650 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 3)
|
||||
terminal(B 3)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(3350 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 3)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 3)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(2650 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 16)
|
||||
terminal(G 2)
|
||||
terminal(D 15)
|
||||
terminal(B 16)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(3350 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 15)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 16)
|
||||
)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INVX1 location(22200 0)
|
||||
pin(0 3)
|
||||
pin(1 14)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 1)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(2 INVX1 location(20400 0)
|
||||
pin(0 3)
|
||||
pin(1 1)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 13)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(8 INVX1 location(4200 0)
|
||||
pin(0 3)
|
||||
pin(1 5)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 4)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(9 INVX1 location(6000 0)
|
||||
pin(0 3)
|
||||
pin(1 6)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 5)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(10 INVX1 location(7800 0)
|
||||
pin(0 3)
|
||||
pin(1 7)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 6)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(11 INVX1 location(9600 0)
|
||||
pin(0 3)
|
||||
pin(1 8)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 7)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(12 INVX1 location(11400 0)
|
||||
pin(0 3)
|
||||
pin(1 9)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 8)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(13 INVX1 location(13200 0)
|
||||
pin(0 3)
|
||||
pin(1 10)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 9)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(14 INVX1 location(15000 0)
|
||||
pin(0 3)
|
||||
pin(1 11)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 10)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(15 INVX1 location(16800 0)
|
||||
pin(0 3)
|
||||
pin(1 12)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 11)
|
||||
pin(5 16)
|
||||
)
|
||||
circuit(16 INVX1 location(18600 0)
|
||||
pin(0 3)
|
||||
pin(1 13)
|
||||
pin(2 16)
|
||||
pin(3 3)
|
||||
pin(4 12)
|
||||
pin(5 16)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
net(16 name($1.1))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1.$1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(G 4)
|
||||
terminal(D 2)
|
||||
terminal(B 2)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($1.$2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 3)
|
||||
terminal(D 6)
|
||||
terminal(B 2)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($1.$3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 4)
|
||||
terminal(D 16)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($1.$4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 16)
|
||||
terminal(G 3)
|
||||
terminal(D 6)
|
||||
terminal(B 1)
|
||||
)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(1 2 match)
|
||||
device(2 1 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(15 16 match)
|
||||
net(4 6 match)
|
||||
net(13 15 match)
|
||||
net(5 7 match)
|
||||
net(6 8 match)
|
||||
net(7 9 match)
|
||||
net(8 10 match)
|
||||
net(9 11 match)
|
||||
net(10 12 match)
|
||||
net(11 13 match)
|
||||
net(12 14 match)
|
||||
net(2 4 match)
|
||||
net(1 3 match)
|
||||
net(14 5 match)
|
||||
net(3 2 match)
|
||||
net(16 1 match)
|
||||
pin(1 3 match)
|
||||
pin(0 2 match)
|
||||
pin(3 4 match)
|
||||
pin(2 1 match)
|
||||
pin(4 0 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
circuit(8 2 match)
|
||||
circuit(9 3 match)
|
||||
circuit(10 4 match)
|
||||
circuit(11 5 match)
|
||||
circuit(12 6 match)
|
||||
circuit(13 7 match)
|
||||
circuit(14 8 match)
|
||||
circuit(15 9 match)
|
||||
circuit(16 10 match)
|
||||
circuit(2 11 match)
|
||||
circuit(1 12 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue