mirror of https://github.com/KLayout/klayout.git
More test data updates
This commit is contained in:
Matthias Koefferlein
parent
ceb82a15d8
commit
1ce221794b
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@ -159,6 +159,7 @@ TEST(11_device_scaling)
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TEST(12_simple_dmos)
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{
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run_test (_this, "ringo_simple_dmos", "ringo.gds");
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run_test (_this, "ringo_simple_dmos_fixed", "ringo_fixed_sources.gds");
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}
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TEST(13_simple_ringo_device_subcircuits)
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@ -447,9 +447,9 @@ reference(
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param(AD 1.4)
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param(PS 6.85)
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param(PD 6.85)
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terminal(S 3)
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terminal(S 5)
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terminal(G 2)
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terminal(D 5)
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terminal(D 3)
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terminal(B 1)
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)
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device(2 NMOS
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@ -460,9 +460,9 @@ reference(
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param(AD 1.4)
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param(PS 6.85)
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param(PD 6.85)
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terminal(S 3)
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terminal(S 4)
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terminal(G 2)
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terminal(D 4)
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terminal(D 3)
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terminal(B 6)
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)
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@ -1,646 +0,0 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(bulk)
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layer(nwell '1/0')
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layer(poly '3/0')
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layer(poly_lbl '3/1')
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layer(diff_cont '4/0')
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layer(poly_cont '5/0')
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layer(metal1 '6/0')
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layer(metal1_lbl '6/1')
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layer(via1 '7/0')
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layer(metal2 '8/0')
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layer(metal2_lbl '8/1')
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layer(ntie)
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layer(psd)
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layer(ptie)
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layer(nsd)
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# Mask layer connectivity
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connect(nwell nwell ntie)
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connect(poly poly poly_lbl poly_cont)
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connect(poly_lbl poly)
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connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
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connect(poly_cont poly poly_cont metal1)
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connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
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connect(metal1_lbl metal1)
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connect(via1 metal1 via1 metal2)
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connect(metal2 via1 metal2 metal2_lbl)
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connect(metal2_lbl metal2)
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connect(ntie nwell diff_cont ntie)
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connect(psd diff_cont psd)
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connect(ptie diff_cont ptie)
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connect(nsd diff_cont nsd)
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# Global nets and connectivity
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global(bulk BULK)
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global(ptie BULK)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(psd (-650 -875) (525 1750))
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)
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terminal(G
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rect(poly (-125 -875) (250 1750))
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)
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terminal(D
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rect(psd (125 -875) (550 1750))
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)
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terminal(B
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rect(nwell (-125 -875) (250 1750))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(psd (-675 -875) (550 1750))
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)
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terminal(G
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rect(poly (-125 -875) (250 1750))
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)
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terminal(D
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rect(psd (125 -875) (525 1750))
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)
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terminal(B
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rect(nwell (-125 -875) (250 1750))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(nsd (-650 -875) (525 1750))
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)
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terminal(G
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rect(poly (-125 -875) (250 1750))
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)
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terminal(D
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rect(nsd (125 -875) (550 1750))
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)
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terminal(B
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rect(bulk (-125 -875) (250 1750))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(nsd (-675 -875) (550 1750))
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)
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terminal(G
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rect(poly (-125 -875) (250 1750))
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)
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terminal(D
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rect(nsd (125 -875) (525 1750))
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)
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terminal(B
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rect(bulk (-125 -875) (250 1750))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(INV2
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# Circuit boundary
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rect((-1700 -2440) (3100 7820))
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# Nets with their geometries
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net(1
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rect(nwell (-1400 1800) (2800 3580))
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rect(diff_cont (-1510 -650) (220 220))
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rect(ntie (-510 -450) (800 680))
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)
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net(2 name(IN)
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rect(poly (-525 -250) (250 2500))
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rect(poly (-1425 -630) (2100 360))
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rect(poly (-125 -2230) (250 2500))
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rect(poly (-1050 -3850) (250 2400))
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rect(poly (550 1200) (250 2400))
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rect(poly (-250 -6000) (250 2400))
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rect(poly (-1050 1200) (250 2400))
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rect(poly_lbl (-525 -2600) (0 0))
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rect(poly_cont (-830 -110) (220 220))
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)
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net(3 name(OUT)
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rect(diff_cont (-910 90) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (1380 3380) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 -3820) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-1820 3380) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(metal1 (1310 -3710) (360 2220))
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rect(metal1 (-1900 -800) (2220 360))
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rect(metal1 (-2280 -2400) (360 2840))
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rect(metal1 (-360 -3600) (360 1560))
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rect(metal1 (1240 2040) (360 1560))
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rect(metal1 (-360 -5160) (360 1560))
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rect(metal1 (-1960 2040) (360 1560))
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rect(metal1_lbl (1420 -2180) (0 0))
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rect(psd (-1850 525) (525 1750))
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rect(psd (1050 -1750) (525 1750))
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rect(nsd (-2100 -5350) (525 1750))
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rect(nsd (1050 -1750) (525 1750))
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)
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net(4 name(VSS)
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rect(diff_cont (-110 90) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 980) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(diff_cont (-220 -620) (220 220))
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rect(metal1 (-290 -290) (360 1560))
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rect(metal1 (-360 -1560) (360 1560))
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rect(via1 (-305 -705) (250 250))
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rect(via1 (-250 150) (250 250))
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rect(via1 (-250 -1450) (250 250))
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rect(via1 (-250 150) (250 250))
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rect(metal2 (-1525 -775) (2800 1700))
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rect(metal2_lbl (-160 -540) (0 0))
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rect(nsd (-1515 -1185) (550 1750))
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)
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net(5 name(VDD)
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rect(diff_cont (-110 2490) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 -1420) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(diff_cont (-220 180) (220 220))
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rect(metal1 (-290 -1490) (360 1560))
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rect(metal1 (-360 -1560) (360 1560))
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rect(via1 (-305 -1505) (250 250))
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rect(via1 (-250 150) (250 250))
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rect(via1 (-250 150) (250 250))
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rect(via1 (-250 150) (250 250))
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rect(metal2 (-1525 -1575) (2800 1700))
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rect(metal2_lbl (-150 -1250) (0 0))
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rect(psd (-1525 -475) (550 1750))
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)
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net(6 name(BULK)
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rect(diff_cont (-110 -2160) (220 220))
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rect(ptie (-510 -450) (800 680))
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)
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# Outgoing pins and their connections to nets
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pin(1)
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pin(2 name(IN))
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pin(3 name(OUT))
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pin(4 name(VSS))
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pin(5 name(VDD))
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pin(6 name(BULK))
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# Devices and their connections
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device(1 D$PMOS
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device(D$PMOS$1 location(800 0))
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connect(0 S S)
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connect(1 S D)
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connect(0 G G)
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connect(1 G G)
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connect(0 D D)
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connect(1 D S)
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connect(0 B B)
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connect(1 B B)
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location(-400 3200)
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param(L 0.25)
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param(W 3.5)
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param(AS 1.4)
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param(AD 1.4)
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param(PS 6.85)
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param(PD 6.85)
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terminal(S 3)
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terminal(G 2)
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terminal(D 5)
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terminal(B 1)
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)
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device(2 D$NMOS
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device(D$NMOS$1 location(800 0))
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connect(0 S S)
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connect(1 S D)
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connect(0 G G)
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connect(1 G G)
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connect(0 D D)
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connect(1 D S)
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connect(0 B B)
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connect(1 B B)
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location(-400 -400)
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param(L 0.25)
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param(W 3.5)
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param(AS 1.4)
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param(AD 1.4)
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param(PS 6.85)
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param(PD 6.85)
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terminal(S 3)
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terminal(G 2)
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terminal(D 4)
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terminal(B 6)
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)
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)
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circuit(INV2PAIR
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# Circuit boundary
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rect((0 -1640) (5740 7820))
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# Nets with their geometries
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net(1 name(BULK))
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net(2)
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net(3)
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net(4)
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net(5)
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net(6)
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net(7)
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# Outgoing pins and their connections to nets
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pin(1 name(BULK))
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pin(2)
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pin(3)
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pin(4)
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pin(5)
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pin(6)
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pin(7)
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# Subcircuits and their connections
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circuit(1 INV2 location(1700 800)
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pin(0 7)
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pin(1 5)
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pin(2 4)
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pin(3 3)
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pin(4 2)
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pin(5 1)
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)
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circuit(2 INV2 location(4340 800)
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pin(0 7)
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pin(1 4)
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pin(2 6)
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pin(3 3)
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pin(4 2)
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pin(5 1)
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)
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)
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circuit(RINGO
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# Circuit boundary
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rect((-1720 -2440) (26880 7820))
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# Nets with their geometries
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net(1 name(FB)
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rect(metal1 (-1700 1620) (360 360))
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rect(via1 (-305 -305) (250 250))
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rect(via1 (23190 -250) (250 250))
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rect(metal2 (-23765 -325) (23840 400))
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rect(metal2_lbl (-22120 -200) (0 0))
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)
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net(2 name(OSC)
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rect(via1 (24435 1675) (250 250))
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rect(metal2 (-325 -325) (400 400))
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rect(metal2_lbl (-200 -200) (0 0))
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)
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net(3 name(VDD)
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rect(metal1 (-180 3900) (360 1120))
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rect(metal1 (2280 -1120) (360 1120))
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
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rect(metal1 (2280 -1120) (360 1120))
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rect(metal2_lbl (-23940 -2220) (0 0))
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)
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net(4 name(VSS)
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rect(metal1 (-180 -2220) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal1 (2280 -1120) (360 1120))
|
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rect(metal2_lbl (-23940 1100) (0 0))
|
||||
)
|
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net(5)
|
||||
net(6)
|
||||
net(7)
|
||||
net(8)
|
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net(9)
|
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net(10)
|
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net(11)
|
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net(12)
|
||||
|
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# Outgoing pins and their connections to nets
|
||||
pin(1 name(FB))
|
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pin(2 name(OSC))
|
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pin(3 name(VDD))
|
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pin(4 name(VSS))
|
||||
|
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# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR location(19420 -800)
|
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pin(0 4)
|
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pin(1 3)
|
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pin(2 4)
|
||||
pin(3 1)
|
||||
pin(4 10)
|
||||
pin(5 2)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(2 INV2PAIR location(-1700 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 8)
|
||||
pin(4 1)
|
||||
pin(5 9)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(3 INV2PAIR location(3580 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 7)
|
||||
pin(4 9)
|
||||
pin(5 12)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(4 INV2PAIR location(8860 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 6)
|
||||
pin(4 12)
|
||||
pin(5 11)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(5 INV2PAIR location(14140 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 5)
|
||||
pin(4 11)
|
||||
pin(5 10)
|
||||
pin(6 3)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('5'))
|
||||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('5'))
|
||||
net(6 name('6'))
|
||||
net(7 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
pin(7 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($1)
|
||||
pin(0 7)
|
||||
pin(1 5)
|
||||
pin(2 4)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(2 INV2 name($2)
|
||||
pin(0 7)
|
||||
pin(1 4)
|
||||
pin(2 6)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('6'))
|
||||
net(6 name('100'))
|
||||
net(7 name('5'))
|
||||
net(8 name('101'))
|
||||
net(9 name('8'))
|
||||
net(10 name('102'))
|
||||
net(11 name('7'))
|
||||
net(12 name('103'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 1)
|
||||
pin(4 5)
|
||||
pin(5 2)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(2 INV2PAIR name($2)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 6)
|
||||
pin(4 1)
|
||||
pin(5 7)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(3 INV2PAIR name($3)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 8)
|
||||
pin(4 7)
|
||||
pin(5 9)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(4 INV2PAIR name($4)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 10)
|
||||
pin(4 9)
|
||||
pin(5 11)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(5 INV2PAIR name($5)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 5)
|
||||
pin(6 3)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INV2 INV2 match
|
||||
xref(
|
||||
net(1 1 match)
|
||||
net(6 6 match)
|
||||
net(2 2 match)
|
||||
net(3 3 match)
|
||||
net(5 5 match)
|
||||
net(4 4 match)
|
||||
pin(0 0 match)
|
||||
pin(5 5 match)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(4 4 match)
|
||||
pin(3 3 match)
|
||||
device(2 2 match)
|
||||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(INV2PAIR INV2PAIR match
|
||||
xref(
|
||||
net(2 2 match)
|
||||
net(3 3 match)
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(6 6 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(5 5 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
circuit(1 1 match)
|
||||
circuit(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(8 6 match)
|
||||
net(7 8 match)
|
||||
net(6 10 match)
|
||||
net(5 12 match)
|
||||
net(9 7 match)
|
||||
net(10 5 match)
|
||||
net(11 11 match)
|
||||
net(12 9 match)
|
||||
net(1 1 match)
|
||||
net(2 2 match)
|
||||
net(3 3 match)
|
||||
net(4 4 match)
|
||||
pin(0 0 match)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 3 match)
|
||||
circuit(1 1 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -447,9 +447,9 @@ reference(
|
|||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(S 5)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(D 3)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -460,9 +460,9 @@ reference(
|
|||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(D 3)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -1,677 +0,0 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(bulk)
|
||||
layer(nwell '1/0')
|
||||
layer(poly '3/0')
|
||||
layer(poly_lbl '3/1')
|
||||
layer(diff_cont '4/0')
|
||||
layer(poly_cont '5/0')
|
||||
layer(metal1 '6/0')
|
||||
layer(metal1_lbl '6/1')
|
||||
layer(via1 '7/0')
|
||||
layer(metal2 '8/0')
|
||||
layer(metal2_lbl '8/1')
|
||||
layer(ntie)
|
||||
layer(psd)
|
||||
layer(ptie)
|
||||
layer(nsd)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(nwell nwell ntie)
|
||||
connect(poly poly poly_lbl poly_cont)
|
||||
connect(poly_lbl poly)
|
||||
connect(diff_cont diff_cont metal1 ntie psd ptie nsd)
|
||||
connect(poly_cont poly poly_cont metal1)
|
||||
connect(metal1 diff_cont poly_cont metal1 metal1_lbl via1)
|
||||
connect(metal1_lbl metal1)
|
||||
connect(via1 metal1 via1 metal2)
|
||||
connect(metal2 via1 metal2 metal2_lbl)
|
||||
connect(metal2_lbl metal2)
|
||||
connect(ntie nwell diff_cont ntie)
|
||||
connect(psd diff_cont psd)
|
||||
connect(ptie diff_cont ptie)
|
||||
connect(nsd diff_cont nsd)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(bulk BULK)
|
||||
global(ptie BULK)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(psd (-650 -875) (525 1750))
|
||||
)
|
||||
terminal(G
|
||||
rect(poly (-125 -875) (250 1750))
|
||||
)
|
||||
terminal(D
|
||||
rect(psd (125 -875) (550 1750))
|
||||
)
|
||||
terminal(B
|
||||
rect(nwell (-125 -875) (250 1750))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(psd (-675 -875) (550 1750))
|
||||
)
|
||||
terminal(G
|
||||
rect(poly (-125 -875) (250 1750))
|
||||
)
|
||||
terminal(D
|
||||
rect(psd (125 -875) (525 1750))
|
||||
)
|
||||
terminal(B
|
||||
rect(nwell (-125 -875) (250 1750))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(nsd (-650 -875) (525 1750))
|
||||
)
|
||||
terminal(G
|
||||
rect(poly (-125 -875) (250 1750))
|
||||
)
|
||||
terminal(D
|
||||
rect(nsd (125 -875) (550 1750))
|
||||
)
|
||||
terminal(B
|
||||
rect(bulk (-125 -875) (250 1750))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(nsd (-675 -875) (550 1750))
|
||||
)
|
||||
terminal(G
|
||||
rect(poly (-125 -875) (250 1750))
|
||||
)
|
||||
terminal(D
|
||||
rect(nsd (125 -875) (525 1750))
|
||||
)
|
||||
terminal(B
|
||||
rect(bulk (-125 -875) (250 1750))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1700 -2440) (3100 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(nwell (-1400 1800) (2800 3580))
|
||||
rect(diff_cont (-1510 -650) (220 220))
|
||||
rect(ntie (-510 -450) (800 680))
|
||||
)
|
||||
net(2 name(IN)
|
||||
rect(poly (-525 -250) (250 2500))
|
||||
rect(poly (-1425 -630) (2100 360))
|
||||
rect(poly (-125 -2230) (250 2500))
|
||||
rect(poly (-1050 -3850) (250 2400))
|
||||
rect(poly (550 1200) (250 2400))
|
||||
rect(poly (-250 -6000) (250 2400))
|
||||
rect(poly (-1050 1200) (250 2400))
|
||||
rect(poly_lbl (-525 -2600) (0 0))
|
||||
rect(poly_cont (-830 -110) (220 220))
|
||||
)
|
||||
net(3 name(OUT)
|
||||
rect(diff_cont (-910 90) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (1380 3380) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 -3820) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-1820 3380) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(metal1 (1310 -3710) (360 2220))
|
||||
rect(metal1 (-1900 -800) (2220 360))
|
||||
rect(metal1 (-2280 -2400) (360 2840))
|
||||
rect(metal1 (-360 -3600) (360 1560))
|
||||
rect(metal1 (1240 2040) (360 1560))
|
||||
rect(metal1 (-360 -5160) (360 1560))
|
||||
rect(metal1 (-1960 2040) (360 1560))
|
||||
rect(metal1_lbl (1420 -2180) (0 0))
|
||||
rect(psd (-1850 525) (525 1750))
|
||||
rect(psd (1050 -1750) (525 1750))
|
||||
rect(nsd (-2100 -5350) (525 1750))
|
||||
rect(nsd (1050 -1750) (525 1750))
|
||||
)
|
||||
net(4 name(VSS)
|
||||
rect(diff_cont (-110 90) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 980) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(diff_cont (-220 -620) (220 220))
|
||||
rect(metal1 (-290 -290) (360 1560))
|
||||
rect(metal1 (-360 -1560) (360 1560))
|
||||
rect(via1 (-305 -705) (250 250))
|
||||
rect(via1 (-250 150) (250 250))
|
||||
rect(via1 (-250 -1450) (250 250))
|
||||
rect(via1 (-250 150) (250 250))
|
||||
rect(metal2 (-1525 -775) (2800 1700))
|
||||
rect(metal2_lbl (-160 -540) (0 0))
|
||||
rect(nsd (-1515 -1185) (550 1750))
|
||||
)
|
||||
net(5 name(VDD)
|
||||
rect(diff_cont (-110 2490) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 -1420) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(diff_cont (-220 180) (220 220))
|
||||
rect(metal1 (-290 -1490) (360 1560))
|
||||
rect(metal1 (-360 -1560) (360 1560))
|
||||
rect(via1 (-305 -1505) (250 250))
|
||||
rect(via1 (-250 150) (250 250))
|
||||
rect(via1 (-250 150) (250 250))
|
||||
rect(via1 (-250 150) (250 250))
|
||||
rect(metal2 (-1525 -1575) (2800 1700))
|
||||
rect(metal2_lbl (-150 -1250) (0 0))
|
||||
rect(psd (-1525 -475) (550 1750))
|
||||
)
|
||||
net(6 name(BULK)
|
||||
rect(diff_cont (-110 -2160) (220 220))
|
||||
rect(ptie (-510 -450) (800 680))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1)
|
||||
pin(2 name(IN))
|
||||
pin(3 name(OUT))
|
||||
pin(4 name(VSS))
|
||||
pin(5 name(VDD))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
device(D$PMOS$1 location(800 0))
|
||||
connect(0 S S)
|
||||
connect(1 S D)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D S)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(-400 3200)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(2 D$NMOS
|
||||
device(D$NMOS$1 location(800 0))
|
||||
connect(0 S S)
|
||||
connect(1 S D)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D S)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(-400 -400)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 -1640) (5740 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(BULK))
|
||||
net(2)
|
||||
net(3)
|
||||
net(4)
|
||||
net(5)
|
||||
net(6)
|
||||
net(7)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(BULK))
|
||||
pin(2)
|
||||
pin(3)
|
||||
pin(4)
|
||||
pin(5)
|
||||
pin(6)
|
||||
pin(7)
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 location(1700 800)
|
||||
pin(0 7)
|
||||
pin(1 5)
|
||||
pin(2 4)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(2 INV2 location(4340 800)
|
||||
pin(0 7)
|
||||
pin(1 4)
|
||||
pin(2 6)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((-1720 -2440) (26880 7820))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(FB)
|
||||
rect(metal1 (-1700 1620) (360 360))
|
||||
rect(via1 (-305 -305) (250 250))
|
||||
rect(via1 (23190 -250) (250 250))
|
||||
rect(metal2 (-23765 -325) (23840 400))
|
||||
rect(metal2_lbl (-22120 -200) (0 0))
|
||||
)
|
||||
net(2 name(OSC)
|
||||
rect(via1 (24435 1675) (250 250))
|
||||
rect(metal2 (-325 -325) (400 400))
|
||||
rect(metal2_lbl (-200 -200) (0 0))
|
||||
)
|
||||
net(3 name(VDD)
|
||||
rect(metal1 (-180 3900) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal2_lbl (-23940 -2220) (0 0))
|
||||
)
|
||||
net(4 name(VSS)
|
||||
rect(metal1 (-180 -2220) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal1 (2280 -1120) (360 1120))
|
||||
rect(metal2_lbl (-23940 1100) (0 0))
|
||||
)
|
||||
net(5)
|
||||
net(6)
|
||||
net(7)
|
||||
net(8)
|
||||
net(9)
|
||||
net(10)
|
||||
net(11)
|
||||
net(12)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(FB))
|
||||
pin(2 name(OSC))
|
||||
pin(3 name(VDD))
|
||||
pin(4 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR location(19420 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 1)
|
||||
pin(4 10)
|
||||
pin(5 2)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(2 INV2PAIR location(-1700 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 8)
|
||||
pin(4 1)
|
||||
pin(5 9)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(3 INV2PAIR location(3580 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 7)
|
||||
pin(4 9)
|
||||
pin(5 12)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(4 INV2PAIR location(8860 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 6)
|
||||
pin(4 12)
|
||||
pin(5 11)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(5 INV2PAIR location(14140 -800)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 5)
|
||||
pin(4 11)
|
||||
pin(5 10)
|
||||
pin(6 3)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(INV2
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('5'))
|
||||
net(6 name('6'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 3.5)
|
||||
param(AS 1.4)
|
||||
param(AD 1.4)
|
||||
param(PS 6.85)
|
||||
param(PD 6.85)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INV2PAIR
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('5'))
|
||||
net(6 name('6'))
|
||||
net(7 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
pin(7 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
pin(0 7)
|
||||
pin(1 4)
|
||||
pin(2 6)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INV2PAIRX
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('5'))
|
||||
net(6 name('6'))
|
||||
net(7 name('7'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
pin(5 name('5'))
|
||||
pin(6 name('6'))
|
||||
pin(7 name('7'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2 name($2)
|
||||
pin(0 7)
|
||||
pin(1 4)
|
||||
pin(2 6)
|
||||
pin(3 3)
|
||||
pin(4 2)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name('1'))
|
||||
net(2 name('2'))
|
||||
net(3 name('3'))
|
||||
net(4 name('4'))
|
||||
net(5 name('6'))
|
||||
net(6 name('5'))
|
||||
net(7 name('101'))
|
||||
net(8 name('8'))
|
||||
net(9 name('102'))
|
||||
net(10 name('7'))
|
||||
net(11 name('103'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name('1'))
|
||||
pin(2 name('2'))
|
||||
pin(3 name('3'))
|
||||
pin(4 name('4'))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 INV2PAIR name($1)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 1)
|
||||
pin(4 5)
|
||||
pin(5 2)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(2 INV2PAIR name($2)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 1)
|
||||
pin(4 1)
|
||||
pin(5 6)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(3 INV2PAIR name($3)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 7)
|
||||
pin(4 6)
|
||||
pin(5 8)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(4 INV2PAIR name($4)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 9)
|
||||
pin(4 8)
|
||||
pin(5 10)
|
||||
pin(6 3)
|
||||
)
|
||||
circuit(5 INV2PAIR name($5)
|
||||
pin(0 4)
|
||||
pin(1 3)
|
||||
pin(2 4)
|
||||
pin(3 11)
|
||||
pin(4 10)
|
||||
pin(5 5)
|
||||
pin(6 3)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(() INV2PAIRX mismatch
|
||||
xref(
|
||||
)
|
||||
)
|
||||
circuit(INV2 INV2 match
|
||||
xref(
|
||||
net(1 1 match)
|
||||
net(6 6 match)
|
||||
net(2 2 match)
|
||||
net(3 3 match)
|
||||
net(5 5 match)
|
||||
net(4 4 match)
|
||||
pin(0 0 match)
|
||||
pin(5 5 match)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(4 4 match)
|
||||
pin(3 3 match)
|
||||
device(2 2 match)
|
||||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(INV2PAIR INV2PAIR nomatch
|
||||
xref(
|
||||
net(2 2 mismatch)
|
||||
net(3 3 mismatch)
|
||||
net(4 4 mismatch)
|
||||
net(5 5 mismatch)
|
||||
net(6 6 match)
|
||||
net(7 7 mismatch)
|
||||
net(1 1 mismatch)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(5 5 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
circuit(1 () mismatch)
|
||||
circuit(2 1 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO nomatch
|
||||
log(
|
||||
entry(error description('Net $I22 is not matching any net from reference netlist'))
|
||||
entry(error description('Net FB is not matching any net from reference netlist'))
|
||||
)
|
||||
xref(
|
||||
net(8 () mismatch)
|
||||
net(7 7 match)
|
||||
net(6 9 match)
|
||||
net(5 11 match)
|
||||
net(9 6 match)
|
||||
net(10 5 match)
|
||||
net(11 10 match)
|
||||
net(12 8 match)
|
||||
net(1 1 mismatch)
|
||||
net(2 2 match)
|
||||
net(3 3 match)
|
||||
net(4 4 match)
|
||||
pin(0 0 match)
|
||||
pin(1 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 3 match)
|
||||
circuit(() 2 mismatch)
|
||||
circuit(2 () mismatch)
|
||||
circuit(1 1 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,3 +1,3 @@
|
|||
m$1 1 5 2 4 mlvpmos w=1.5um l=0.25um
|
||||
m$2 3 5 2 6 mlvnmos w=0.95um l=0.25um
|
||||
m$1 2 5 1 4 mlvpmos w=1.5um l=0.25um
|
||||
m$2 2 5 3 6 mlvnmos w=0.95um l=0.25um
|
||||
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ X$2 3 5 2 6 INVX1
|
|||
* net 3 IN
|
||||
* net 4 VSS
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 3 1 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 1 3 2 2 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 4 3 1 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 1 3 4 4 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
|
|
|||
|
|
@ -197,9 +197,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 3)
|
||||
terminal(D 6)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -210,9 +210,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(S 1)
|
||||
terminal(G 2)
|
||||
terminal(D 1)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -167,9 +167,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 4)
|
||||
T(S 3)
|
||||
T(G 2)
|
||||
T(D 3)
|
||||
T(D 4)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 NMOS
|
||||
|
|
@ -180,9 +180,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 3)
|
||||
T(S 1)
|
||||
T(G 2)
|
||||
T(D 1)
|
||||
T(D 3)
|
||||
T(B 1)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -13,11 +13,11 @@
|
|||
* net 5 VDD
|
||||
* net 6 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
* device instance $2 r0 *1 1.775,4.95 PMOS
|
||||
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
* device instance $3 r0 *1 1.025,2 NMOS
|
||||
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
* device instance $4 r0 *1 1.775,2 NMOS
|
||||
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
.ENDS NAND2_WITH_DIODES
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell NAND2_WITH_DIODES
|
||||
* pin B
|
||||
* pin A
|
||||
* pin OUT
|
||||
* pin VDD
|
||||
* pin VSS
|
||||
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
|
||||
* net 1 B
|
||||
* net 2 A
|
||||
* net 4 OUT
|
||||
* net 5 VDD
|
||||
* net 6 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
* device instance $2 r0 *1 1.775,4.95 PMOS
|
||||
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
* device instance $3 r0 *1 1.025,0.65 NMOS
|
||||
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
* device instance $4 r0 *1 1.775,0.65 NMOS
|
||||
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
.ENDS NAND2_WITH_DIODES
|
||||
|
|
@ -13,11 +13,11 @@
|
|||
* net 5 VDD
|
||||
* net 6 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
M$1 4 1 5 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
* device instance $2 r0 *1 1.775,4.95 PMOS
|
||||
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
M$2 5 2 4 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
* device instance $3 r0 *1 1.025,2 NMOS
|
||||
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
M$3 3 1 6 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
* device instance $4 r0 *1 1.775,2 NMOS
|
||||
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
M$4 4 2 3 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
.ENDS NAND2_WITH_DIODES
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell NAND2_WITH_DIODES
|
||||
* pin B
|
||||
* pin A
|
||||
* pin OUT
|
||||
* pin VDD
|
||||
* pin VSS
|
||||
.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
|
||||
* net 1 B
|
||||
* net 2 A
|
||||
* net 4 OUT
|
||||
* net 5 VDD
|
||||
* net 6 VSS
|
||||
* device instance $1 r0 *1 1.025,4.95 PMOS
|
||||
M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
|
||||
* device instance $2 r0 *1 1.775,4.95 PMOS
|
||||
M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
|
||||
* device instance $3 r0 *1 1.025,0.65 NMOS
|
||||
M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
|
||||
* device instance $4 r0 *1 1.775,0.65 NMOS
|
||||
M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
|
||||
.ENDS NAND2_WITH_DIODES
|
||||
|
|
@ -16,12 +16,12 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
|
|||
|
||||
.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
|
||||
M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 VDD B OUT NWELL PMOS L=0.25U W=1.5U
|
||||
M$3 VSS A 1 BULK NMOS L=0.25U W=0.95U
|
||||
M$4 1 B OUT BULK NMOS L=0.25U W=0.95U
|
||||
M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$3 1 A VSS BULK NMOS L=0.25U W=0.95U
|
||||
M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U
|
||||
.ENDS ND2X1
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS NWELL IN BULK
|
||||
M$1 VDD IN OUT NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 VSS IN OUT BULK NMOS L=0.25U W=0.95U
|
||||
M$1 OUT IN VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 OUT IN VSS BULK NMOS L=0.25U W=0.95U
|
||||
.ENDS INVX1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1B
|
||||
|
||||
* cell INVX1
|
||||
|
|
@ -71,9 +71,9 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -705,9 +705,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -718,9 +718,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -731,9 +731,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -765,9 +765,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -778,9 +778,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -35,13 +35,13 @@ X$15 3 12 16 3 11 16 INVX1
|
|||
* cell instance $16 r0 *1 18.6,0
|
||||
X$16 3 13 16 3 12 16 INVX1
|
||||
* device instance $1 r0 *1 2.65,5.8 PMOS
|
||||
M$1 4 2 3 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 3 2 4 3 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 3.35,5.8 PMOS
|
||||
M$2 3 1 4 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 4 1 3 3 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 2.65,2.135 NMOS
|
||||
M$3 16 2 15 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 15 2 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 3.35,2.135 NMOS
|
||||
M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 4 1 15 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX1
|
||||
|
|
@ -58,7 +58,7 @@ M$4 15 1 4 16 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
|
|
|||
|
|
@ -560,9 +560,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -573,9 +573,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
@ -629,9 +629,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(S 2)
|
||||
terminal(G 3)
|
||||
terminal(D 2)
|
||||
terminal(D 6)
|
||||
terminal(B 2)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -642,9 +642,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 16)
|
||||
terminal(S 1)
|
||||
terminal(G 4)
|
||||
terminal(D 1)
|
||||
terminal(D 16)
|
||||
terminal(B 1)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -655,9 +655,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(S 16)
|
||||
terminal(G 3)
|
||||
terminal(D 16)
|
||||
terminal(D 6)
|
||||
terminal(B 1)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -618,9 +618,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -631,9 +631,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -644,9 +644,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -678,9 +678,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -691,9 +691,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -618,9 +618,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -631,9 +631,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -644,9 +644,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -678,9 +678,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -691,9 +691,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
|
||||
M$1 2 5 1 4 PMOS L=0.5U W=3U AS=2.55P AD=2.55P PS=7.7U PD=7.7U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
|
||||
M$2 2 5 3 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.5U W=1.9U AS=1.615P AD=1.615P PS=5.5U PD=5.5U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
|
||||
M$1 1 6 2 4 PMOS L=0.5U W=3U AS=2.55P AD=1.35P PS=7.7U PD=3.9U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
|
||||
M$2 2 5 1 4 PMOS L=0.5U W=3U AS=1.35P AD=2.55P PS=3.9U PD=7.7U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
|
||||
M$3 8 6 3 7 NMOS L=0.5U W=1.9U AS=1.615P AD=0.855P PS=5.5U PD=2.8U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
|
||||
M$4 2 5 8 7 NMOS L=0.5U W=1.9U AS=0.855P AD=1.615P PS=2.8U PD=5.5U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 7 A
|
||||
* net 8 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 7 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 6 2 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$3 3 7 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 4 6 2 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -609,9 +609,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
|
|
@ -851,62 +851,36 @@ xref(
|
|||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 nomatch
|
||||
log(
|
||||
entry(error description('No equivalent pin VSS from netlist found in reference netlist.\nThis is an indication that additional physical connections are made to the subcircuit cell.'))
|
||||
entry(info description('Potential invalid connection in circuit RINGO, subcircuit cell reference at r0 *1 1.8,0'))
|
||||
entry(error description('No equivalent pin VSS from reference netlist found in netlist.\nThis is an indication that a physical connection is not made to the subcircuit.'))
|
||||
)
|
||||
xref(
|
||||
net(4 8 mismatch)
|
||||
net(5 4 mismatch)
|
||||
net(5 4 match)
|
||||
net(4 3 mismatch)
|
||||
net(7 6 match)
|
||||
net(6 5 match)
|
||||
net(2 2 mismatch)
|
||||
net(2 2 match)
|
||||
net(8 7 mismatch)
|
||||
net(1 1 mismatch)
|
||||
net(3 3 mismatch)
|
||||
net(1 1 match)
|
||||
net(3 8 mismatch)
|
||||
pin(() 2 mismatch)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(3 3 mismatch)
|
||||
device(4 4 match)
|
||||
pin(2 () mismatch)
|
||||
device(3 3 match)
|
||||
device(4 4 mismatch)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(1 1 mismatch)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
circuit(RINGO RINGO skipped description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1')
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,83 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VSS
|
||||
.SUBCKT RINGO 11 12 13 14 15
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 13 OUT
|
||||
* net 14 ENABLE
|
||||
* net 15 VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 15 12 11 14 15 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 15 12 1 15 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 15 12 2 15 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 15 12 3 15 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 15 12 4 15 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 15 12 5 15 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 15 12 6 15 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 15 12 7 15 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 15 12 8 15 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 15 12 9 15 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 15 12 10 15 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 13 15 12 11 15 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT ND2X1 1 2 3 5 6 7 8
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 6 B
|
||||
* net 7 A
|
||||
* net 8 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 7 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 2 6 1 5 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 4 7 3 8 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.22135P PS=2.75U PD=2.366U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 2 6 4 8 NMOS L=0.25U W=0.95U AS=0.20615P AD=0.40375P PS=2.334U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -31,11 +31,11 @@ layout(
|
|||
connect(l14 l13 l14 l15)
|
||||
connect(l15 l14 l15)
|
||||
connect(l9 l9)
|
||||
connect(l3 l10 l3)
|
||||
connect(l1 l10 l1)
|
||||
connect(l3 l10 l3 l1)
|
||||
connect(l1 l10 l3 l1)
|
||||
connect(l11 l4 l10 l11)
|
||||
connect(l8 l10 l8)
|
||||
connect(l6 l10 l6)
|
||||
connect(l8 l10 l8 l6)
|
||||
connect(l6 l10 l8 l6)
|
||||
connect(l12 l10 l12)
|
||||
|
||||
# Global nets and connectivity
|
||||
|
|
@ -92,13 +92,13 @@ layout(
|
|||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l8 (125 -475) (450 950))
|
||||
rect(l8 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l5 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (-550 -475) (425 950))
|
||||
rect(l6 (125 -475) (233 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l9 (-125 -475) (250 950))
|
||||
|
|
@ -106,7 +106,7 @@ layout(
|
|||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l8 (-575 -475) (450 950))
|
||||
rect(l8 (-342 -475) (217 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l5 (-125 -475) (250 950))
|
||||
|
|
@ -148,8 +148,8 @@ layout(
|
|||
rect(l13 (-240 -790) (300 1700))
|
||||
rect(l13 (-1350 0) (2400 800))
|
||||
rect(l13 (-1150 -400) (0 0))
|
||||
rect(l3 (-250 -2150) (425 1500))
|
||||
rect(l3 (-450 -1500) (425 1500))
|
||||
rect(l3 (-275 -2150) (425 1500))
|
||||
rect(l3 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l10 (1810 1770) (180 180))
|
||||
|
|
@ -169,7 +169,8 @@ layout(
|
|||
rect(l13 (-300 0) (300 1400))
|
||||
rect(l1 (-1750 -1450) (425 1500))
|
||||
rect(l1 (950 -1500) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
rect(l6 (-192 -4890) (192 950))
|
||||
rect(l6 (-425 -950) (233 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l10 (410 1770) (180 180))
|
||||
|
|
@ -177,11 +178,14 @@ layout(
|
|||
rect(l13 (-240 -1300) (300 1360))
|
||||
rect(l13 (-650 -2160) (2400 800))
|
||||
rect(l13 (-1150 -400) (0 0))
|
||||
rect(l6 (-950 860) (425 950))
|
||||
rect(l8 (-950 860) (208 950))
|
||||
rect(l8 (0 -950) (217 950))
|
||||
)
|
||||
net(4
|
||||
rect(l8 (1000 1660) (425 950))
|
||||
rect(l8 (-450 -950) (425 950))
|
||||
rect(l8 (1208 1660) (192 950))
|
||||
rect(l8 (-192 -950) (217 950))
|
||||
rect(l6 (-425 -950) (208 950))
|
||||
rect(l6 (-233 -950) (233 950))
|
||||
)
|
||||
net(5
|
||||
rect(l4 (-100 4500) (2600 3500))
|
||||
|
|
@ -248,22 +252,22 @@ layout(
|
|||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 4)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.22135)
|
||||
param(PS 2.75)
|
||||
param(PD 2.366)
|
||||
terminal(S 3)
|
||||
terminal(G 7)
|
||||
terminal(D 3)
|
||||
terminal(D 4)
|
||||
terminal(B 8)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AS 0.20615)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PS 2.334)
|
||||
param(PD 2.75)
|
||||
terminal(S 4)
|
||||
terminal(G 6)
|
||||
|
|
@ -297,7 +301,8 @@ layout(
|
|||
rect(l13 (-240 -790) (300 4790))
|
||||
rect(l13 (-150 -2500) (0 0))
|
||||
rect(l1 (-225 1050) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
rect(l6 (-192 -4890) (192 950))
|
||||
rect(l6 (-425 -950) (233 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l10 (410 1770) (180 180))
|
||||
|
|
@ -305,7 +310,8 @@ layout(
|
|||
rect(l13 (-240 -1300) (300 1360))
|
||||
rect(l13 (-650 -2160) (1800 800))
|
||||
rect(l13 (-850 -400) (0 0))
|
||||
rect(l8 (-650 860) (425 950))
|
||||
rect(l8 (-650 860) (208 950))
|
||||
rect(l8 (0 -950) (217 950))
|
||||
)
|
||||
net(4
|
||||
rect(l4 (-100 4500) (2000 3500))
|
||||
|
|
@ -609,9 +615,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
|
|
@ -850,16 +856,16 @@ xref(
|
|||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 nomatch
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(4 8 mismatch)
|
||||
net(5 4 mismatch)
|
||||
net(4 8 match)
|
||||
net(5 4 match)
|
||||
net(7 6 match)
|
||||
net(6 5 match)
|
||||
net(2 2 mismatch)
|
||||
net(8 7 mismatch)
|
||||
net(1 1 mismatch)
|
||||
net(3 3 mismatch)
|
||||
net(2 2 match)
|
||||
net(8 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
|
|
@ -867,10 +873,10 @@ xref(
|
|||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(3 3 mismatch)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
device(1 1 mismatch)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
|
|
@ -54,9 +54,9 @@ M$1 16 1 16 16 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -75,11 +75,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -637,9 +637,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -650,9 +650,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -663,9 +663,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -697,9 +697,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -710,9 +710,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
|
|||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
M$1 OUT IN VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 OUT IN VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
M$1 VDD A OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 OUT B VDD \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 \$I3 A VSS SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I3 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
M$4 OUT B \$I3 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -1,31 +0,0 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I5 B OUT SUBSTRATE NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -559,9 +559,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 1)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(3 NMOS
|
||||
|
|
@ -572,9 +572,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 8)
|
||||
T(S 3)
|
||||
T(G 6)
|
||||
T(D 3)
|
||||
T(D 8)
|
||||
T(B 7)
|
||||
)
|
||||
D(4 NMOS
|
||||
|
|
@ -585,9 +585,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(S 8)
|
||||
T(G 5)
|
||||
T(D 8)
|
||||
T(D 2)
|
||||
T(B 7)
|
||||
)
|
||||
)
|
||||
|
|
@ -612,9 +612,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(S 1)
|
||||
T(G 5)
|
||||
T(D 1)
|
||||
T(D 2)
|
||||
T(B 4)
|
||||
)
|
||||
D(2 NMOS
|
||||
|
|
@ -625,9 +625,9 @@ H(
|
|||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(S 3)
|
||||
T(G 5)
|
||||
T(D 3)
|
||||
T(D 2)
|
||||
T(B 6)
|
||||
)
|
||||
)
|
||||
|
|
|
|||
|
|
@ -618,9 +618,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -631,9 +631,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -644,9 +644,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -678,9 +678,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -691,9 +691,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INV
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INV
|
||||
|
||||
* cell nd2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS nd2X1
|
||||
|
|
|
|||
|
|
@ -618,9 +618,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -631,9 +631,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -644,9 +644,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -678,9 +678,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -691,9 +691,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -16,16 +16,16 @@ X$12 VDD OUT VSS VDD FB VSS INVX1
|
|||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
M$1 OUT IN VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 OUT IN VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
M$1 VDD A OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 OUT B VDD \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 \$I3 A VSS SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I3 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
M$4 OUT B \$I3 SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -1,31 +0,0 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT RINGO FB VDD OUT ENABLE VSS
|
||||
X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
|
||||
X$2 VDD \$2 VSS VDD \$1 VSS INVX1
|
||||
X$3 VDD \$3 VSS VDD \$2 VSS INVX1
|
||||
X$4 VDD \$4 VSS VDD \$3 VSS INVX1
|
||||
X$5 VDD \$5 VSS VDD \$4 VSS INVX1
|
||||
X$6 VDD \$6 VSS VDD \$5 VSS INVX1
|
||||
X$7 VDD \$7 VSS VDD \$6 VSS INVX1
|
||||
X$8 VDD \$8 VSS VDD \$7 VSS INVX1
|
||||
X$9 VDD \$9 VSS VDD \$8 VSS INVX1
|
||||
X$10 VDD \$10 VSS VDD \$9 VSS INVX1
|
||||
X$11 VDD FB VSS VDD \$10 VSS INVX1
|
||||
X$12 VDD OUT VSS VDD FB VSS INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
|
||||
M$1 VDD IN OUT \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$2 VSS IN OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U
|
||||
+ PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
|
||||
M$1 OUT A VDD \$4 PM L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$2 VDD B OUT \$4 PM L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$3 VSS A \$I5 SUBSTRATE NM L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U
|
||||
+ PD=1.4U
|
||||
M$4 \$I5 B OUT SUBSTRATE NM L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U
|
||||
+ PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -620,9 +620,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
|
|
@ -633,9 +633,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 3)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
|
|
@ -646,9 +646,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 8)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
|
|
@ -680,9 +680,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 1)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
|
|
@ -693,9 +693,9 @@ reference(
|
|||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 3)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$21 6 11 9 6 15 9 INVX1
|
|||
* net 4 VSS
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
|
||||
M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
||||
M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
||||
.ENDS INVX2
|
||||
|
||||
* cell INVX1
|
||||
|
|
@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$17 6 11 9 6 15 9 INVX1
|
|||
* net 4 VSS
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 1 3 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
|
||||
M$1 3 1 2 5 PMOS L=0.25U W=3U AS=0.975P AD=0.975P PS=5.8U PD=5.8U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
||||
M$3 3 1 4 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
||||
.ENDS INVX2
|
||||
|
||||
* cell INVX1
|
||||
|
|
@ -71,9 +71,9 @@ M$3 4 1 3 6 NMOS L=0.25U W=1.9U AS=0.6175P AD=0.6175P PS=4.15U PD=4.15U
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -92,11 +92,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ X$12 12 13 15 12 11 15 INVX1
|
|||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
M$1 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
M$2 2 5 3 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
|
|
@ -73,11 +73,11 @@ M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
|||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
|
|||
Loading…
Reference in New Issue