iverilog/vhdlpp
Maciej Suminski 9ff9cbf4aa vhdlpp: Smarter determining the direction in for loops. 2014-10-10 18:39:14 +02:00
..
Makefile.in Rearrange compiler warning flags 2014-07-09 09:04:17 -07:00
README.txt Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
architec.cc Rework scope types and constants so we can tell imported from local names. 2013-06-12 14:09:07 -07:00
architec.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
architec_debug.cc updated FSF-address 2012-08-29 10:12:10 -07:00
architec_elaborate.cc vhdlpp: Aggregate expression are elaborated if 2014-08-20 14:18:16 +02:00
architec_emit.cc vhdlpp: Subprogram class inherits from ScopeBase. 2014-09-30 15:00:55 +02:00
compiler.cc updated FSF-address 2012-08-29 10:12:10 -07:00
compiler.h vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration. 2014-10-01 14:56:32 +02:00
debug.cc vhdlpp: Subprogram class inherits from ScopeBase. 2014-09-30 15:00:55 +02:00
entity.cc Fixed vhdlpp segfault if it processes an entity without any ports declared. 2014-08-04 20:27:21 -07:00
entity.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
entity_elaborate.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
entity_emit.cc updated FSF-address 2012-08-29 10:12:10 -07:00
entity_stream.cc updated FSF-address 2012-08-29 10:12:10 -07:00
expression.cc Removed ExpReal::evaluate().Its signature does not match the one meant to be overridden. 2014-08-22 16:55:47 +02:00
expression.h vhdlpp: Elaboration & emit support for aggregate initializer expressions in records. 2014-09-17 11:24:16 +02:00
expression_debug.cc updated FSF-address 2012-08-29 10:12:10 -07:00
expression_elaborate.cc vhdlpp: Support for 'left & 'right attributes. 2014-10-08 10:05:04 +02:00
expression_emit.cc vhdlpp: Support for 'left & 'right attributes. 2014-10-08 10:05:04 +02:00
expression_evaluate.cc vhdlpp: Evaluation for 'left and 'right attributes. 2014-10-10 18:35:17 +02:00
expression_stream.cc vhdlpp: Added ExpAttribute::write_to_stream(). 2014-10-08 10:21:03 +02:00
ivl_assert.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
lexor.lex Add the string terminator for binary bitstrings. 2014-08-08 09:52:57 +02:00
lexor_keyword.gperf vhdlpp: Support for 'range and 'reverse_range attributes. 2014-10-08 11:18:06 +02:00
library.cc vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'. 2014-10-09 10:29:14 +02:00
library.h vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration. 2014-10-01 14:56:32 +02:00
main.cc vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration. 2014-10-01 14:56:32 +02:00
package.cc vhdlpp: Skip signed & unsigned in types dump in packages. 2014-10-09 10:28:35 +02:00
package.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
package_emit.cc vhdlpp: Subprogram class inherits from ScopeBase. 2014-09-30 15:00:55 +02:00
parse.y vhdlpp: Smarter determining the direction in for loops. 2014-10-10 18:39:14 +02:00
parse_api.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
parse_misc.cc vhdlpp: Corrected VTypeArray::write_to_stream(). 2014-09-15 12:10:05 +02:00
parse_misc.h vhdlpp: Minor cleaning, fixed copyright notices. 2014-08-25 17:29:35 +02:00
parse_types.h vhdlpp: prange_t may have the direction determined automatically. 2014-10-08 10:26:37 +02:00
parse_wrap.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
scope.cc vhdlpp: Added ScopeBase::transfer_from() method. 2014-09-30 15:00:55 +02:00
scope.h vhdlpp: Added ScopeBase::transfer_from() method. 2014-09-30 15:00:55 +02:00
sequential.cc Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
sequential.h vhdlpp: Support for std_logic_vector return type in functions. 2014-09-30 15:58:26 +02:00
sequential_debug.cc Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
sequential_elaborate.cc updated FSF-address 2012-08-29 10:12:10 -07:00
sequential_emit.cc vhdlpp: Smarter determining the direction in for loops. 2014-10-10 18:39:14 +02:00
subprogram.cc vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header. 2014-09-30 15:59:46 +02:00
subprogram.h vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header. 2014-09-30 15:59:46 +02:00
subprogram_emit.cc vhdlpp: Added ExpAttribute::write_to_stream(). 2014-10-08 10:21:03 +02:00
vhdlint.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlint.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlnum.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlpp_config.h.in Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vhdlreal.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlreal.h Update header files to use a more standard name to prevent rereading 2014-07-23 13:42:56 -07:00
vsignal.cc vhdlpp: Simplified the initalization for signals/variables. 2014-09-16 16:31:18 +02:00
vsignal.h vhdlpp: Aggregate expression are elaborated if 2014-08-20 14:18:16 +02:00
vtype.cc vhdlpp: Aggregate expressions for records can be specified in any order. 2014-09-17 16:32:56 +02:00
vtype.h vhdlpp: Fix array typedefs in packages. 2014-10-09 10:37:33 +02:00
vtype_elaborate.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
vtype_emit.cc vhdlpp: Emit VHDL 'integer' as SystemVerilog 'int'. 2014-10-09 10:29:14 +02:00
vtype_match.cc Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
vtype_stream.cc vhdlpp: Fix array typedefs in packages. 2014-10-09 10:37:33 +02:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therein.