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Lars-Peter Clausen
28e121c040
Check that SystemVerilog net declarations can mix entries with and without initialization. Check that in SystemVerilog it is possible to do assignments within net array declarations. Signed-off-by: Lars-Peter Clausen <[email protected]>
10 lines
231 B
JSON
10 lines
231 B
JSON
{
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"type" : "normal",
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"source" : "sv_net_array_decl_assign.v",
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"iverilog-args" : [ "-g2005-sv" ],
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"vlog95" : {
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"__comment" : "Array nets are not supported",
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"type" : "CE"
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}
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}
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