iverilog

History

steve a71dbd3987 Draw AND NOR and NOT gates.		2001-03-25 19:36:12 +00:00
..
.cvsignore	Add the tgt-vvp code generator target.	2001-03-19 01:20:46 +00:00
Makefile.in	Recursive make check target.	2001-03-25 05:59:46 +00:00
README.txt	Add a README for notes about the vvp target.	2001-03-25 18:10:39 +00:00
configure.in	Add the tgt-vvp code generator target.	2001-03-19 01:20:46 +00:00
eval_expr.c	Assure that operands are the correct width.	2001-03-23 01:10:24 +00:00
vvp.c	Generate :module statements.	2001-03-23 02:41:04 +00:00
vvp_priv.h	Geneate code for conditional statements.	2001-03-22 05:06:21 +00:00
vvp_process.c	Skip true clause if condition ix 0, x or z	2001-03-25 03:53:24 +00:00
vvp_scope.c	Draw AND NOR and NOT gates.	2001-03-25 19:36:12 +00:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.