560fbeeae4
Allow to omit trailing module ports in ordered list connection |
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| .. | ||
| README.txt | ||
| array_packed_write_read.json | ||
| br_gh13a-vlog95.json | ||
| br_gh13a.json | ||
| br_gh939.json | ||
| case1.json | ||
| case2-S.json | ||
| case2.json | ||
| case3.json | ||
| casex_synth.json | ||
| constfunc16.json | ||
| constfunc17.json | ||
| constfunc18.json | ||
| constfunc19.json | ||
| constfunc20.json | ||
| dffsynth-S.json | ||
| dffsynth.json | ||
| dffsynth2.json | ||
| dffsynth3.json | ||
| dffsynth4.json | ||
| dffsynth5.json | ||
| dffsynth6.json | ||
| dffsynth7.json | ||
| dffsynth8.json | ||
| dffsynth9.json | ||
| dffsynth10.json | ||
| dffsynth11.json | ||
| dumpfile.json | ||
| final3.json | ||
| macro_str_esc.json | ||
| memsynth1.json | ||
| module_ordered_list1.json | ||
| module_ordered_list2.json | ||
| module_port_array1.json | ||
| param-width-vlog95.json | ||
| param-width.json | ||
| pr903-vlog95.json | ||
| pr903.json | ||
| pr1388974-vlog95.json | ||
| pr1388974.json | ||
| pv_wr_fn_vec2.json | ||
| pv_wr_fn_vec4.json | ||
| sdf_header.json | ||
| struct_packed_write_read.json | ||
| struct_packed_write_read2.json | ||
| sv_array_cassign6.json | ||
| sv_array_cassign7.json | ||
| sv_foreach9.json | ||
| sv_foreach10.json | ||
| sv_wildcard_import8.json | ||
| task_return1.json | ||
| task_return2.json | ||
| task_return_fail1.json | ||
| task_return_fail2.json | ||
README.txt
This directory contains configurations for thet tests that test the iverilog
compiler with the vvp simulation engine. Eash test file is actually a JSON
file that calls out the test type, names the source file, the gold file, any
command argument flags.
{
"type" : "normal",
"source" : "macro_str_esc.v",
"gold" : "macro_str_esc"
}