Prepare for 20021207 snapshot

Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.137 2002/11/13 01:50:11 steve Exp $"
+#ident "$Id: Makefile.in,v 1.139 2002/12/08 03:06:30 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -25,7 +25,7 @@ SHELL = /bin/sh
 # by the compiler. It reflects the assigned version number for the
 # product as a whole. Most components also print the CVS Name: token
 # in order to get a more automatic version stamp as well.
-VERSION = 0.6
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -83,7 +83,10 @@ all: dosify.exe
 dosify.exe: dosify.c
 	$(CC) -o dosify.exe dosify.c
 
+ifeq (@MINGW32@,yes)
 SUBDIRS += driver-vpi
+endif
+
 else
 all: iverilog-vpi
 endif

configure.in

@@ -190,6 +190,8 @@ if test "$CYGWIN" = "yes" -o "$MINGW32" = "yes"
 then
     WIN32=yes
 fi
+
+AC_SUBST(MINGW32)
 AC_SUBST(WIN32)
 AC_MSG_RESULT($WIN32)
 AC_SUBST(EXEEXT)

driver-vpi/Makefile.in

@@ -3,9 +3,7 @@
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software
 #    Foundation; either version 2 of the License, or (at your option)
-#    any later version. In order to redistribute the software in
-#    binary form, you will need a Picture Elements Binary Software
-#    License.
+#    any later version.
 #
 #    This program is distributed in the hope that it will be useful,
 #    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,12 +16,12 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.3 2002/11/13 17:25:10 steve Exp $"
+#ident "$Id: Makefile.in,v 1.5 2002/12/08 03:06:30 steve Exp $"
 #
 #
 SHELL = /bin/sh
 
-VERSION = 0.6
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@
@@ -55,6 +53,9 @@ clean:
 	rm -f *.o
 	rm -f iverilog-vpi@EXEEXT@
 
+distclean: clean
+	rm -f Makefile
+
 O = main.o res.o
 
 iverilog-vpi@EXEEXT@: $O

driver/Makefile.in

@@ -3,9 +3,7 @@
 #    and/or modify it in source code form under the terms of the GNU
 #    Library General Public License as published by the Free Software
 #    Foundation; either version 2 of the License, or (at your option)
-#    any later version. In order to redistribute the software in
-#    binary form, you will need a Picture Elements Binary Software
-#    License.
+#    any later version.
 #
 #    This program is distributed in the hope that it will be useful,
 #    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -18,12 +16,12 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.15 2002/08/10 22:36:59 steve Exp $"
+#ident "$Id: Makefile.in,v 1.16 2002/12/08 03:06:30 steve Exp $"
 #
 #
 SHELL = /bin/sh
 
-VERSION = 0.6
+VERSION = 0.7
 
 prefix = @prefix@
 exec_prefix = @exec_prefix@

driver/main.c

@@ -16,7 +16,7 @@
  *    along with this program; if not, write to the Free Software
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
-#ident "$Id: main.c,v 1.47 2002/08/12 01:27:48 steve Exp $"
+#ident "$Id: main.c,v 1.49 2002/12/04 03:26:59 steve Exp $"
 
 # include "config.h"
 
@@ -119,6 +119,35 @@ char tmp[MAXSIZE];
 
 static char ivl_root[MAXSIZE];
 
+#ifdef __MINGW32__
+# include  <io.h>
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = _open(path, _O_WRONLY|_O_CREAT|_O_EXCL, 0700);
+      if (fd != -1)
+	    file = _fdopen(fd, "w");
+
+       return file;
+}
+#else
+# include  <fcntl.h>
+static FILE*fopen_safe(const char*path)
+{
+      FILE*file = 0;
+      int fd;
+
+      fd = open(path, O_WRONLY|O_CREAT|O_EXCL, 0700);
+      if (fd != -1)
+	    file = fdopen(fd, "w");
+
+       return file;
+}
+#endif
+
 static const char*my_tempfile(const char*str, FILE**fout)
 {
       FILE*file;
@@ -148,7 +177,7 @@ static const char*my_tempfile(const char*str, FILE**fout)
       while ((retry > 0) && (file == NULL)) {
 	    unsigned code = rand();
 	    sprintf(pathbuf, "%s%c%s%04x", tmpdir, sep, str, code);
-	    file = fopen(pathbuf, "w");
+	    file = fopen_safe(pathbuf);
 	    retry -= 1;
       }
 
@@ -657,6 +686,12 @@ int main(int argc, char **argv)
 
 /*
  * $Log: main.c,v $
+ * Revision 1.49  2002/12/04 03:26:59  steve
+ *  Mingw32 compatible temp file management.
+ *
+ * Revision 1.48  2002/12/04 02:29:36  steve
+ *  Use O_EXCL when opening temp files.
+ *
  * Revision 1.47  2002/08/12 01:27:48  steve
  *  Escape the backslash in the windows file name.
  *

elab_lval.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_lval.cc,v 1.21 2002/11/02 01:10:49 steve Exp $"
+#ident "$Id: elab_lval.cc,v 1.23 2002/11/21 23:27:51 steve Exp $"
 #endif
 
 # include "config.h"
@@ -170,16 +170,20 @@ NetAssign_* PEIdent::elaborate_lval(Design*des, NetScope*scope) const
 	    verinum*vl = lsb_->eval_const(des, scope);
 	    if (vl == 0) {
 		  cerr << lsb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *lsb_;
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << lsb_->get_line() << ":      : This lsb expression "
+			"violates the rule: " << *lsb_ << endl;
 		  des->errors += 1;
 		  return 0;
 	    }
 	    verinum*vm = msb_->eval_const(des, scope);
-	    if (vl == 0) {
+	    if (vm == 0) {
 		  cerr << msb_->get_line() << ": error: "
-			"Part select expressions must be constant: "
-		       << *msb_;
+			"Part select expressions must be constant."
+		       << endl;
+		  cerr << msb_->get_line() << ":      : This msb expression "
+			"violates the rule: " << *msb_ << endl;
 		  des->errors += 1;
 		  return 0;
 	    }
@@ -298,6 +302,17 @@ NetAssign_* PEIdent::elaborate_mem_lval_(Design*des, NetScope*scope,
       if (ix == 0)
 	    return 0;
 
+	/* Evaluate the memory index expression down as must as
+	   possible. Ideally, we can get it down to a constant. */
+      if (! dynamic_cast<NetEConst*>(ix)) {
+	    NetExpr*tmp = ix->eval_tree();
+	    if (tmp) {
+		  tmp->set_line(*ix);
+		  delete ix;
+		  ix = tmp;
+	    }
+      }
+
       NetAssign_*lv = new NetAssign_(mem);
       lv->set_bmux(ix);
       lv->set_part(0, mem->width());
@@ -314,6 +329,12 @@ NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*) const
 
 /*
  * $Log: elab_lval.cc,v $
+ * Revision 1.23  2002/11/21 23:27:51  steve
+ *  Precalculate indices to l-value arrays.
+ *
+ * Revision 1.22  2002/11/21 18:15:40  steve
+ *  Fix const test of msb in assignment l-values.
+ *
  * Revision 1.21  2002/11/02 01:10:49  steve
  *  Detect memories without work index in l-value.
  *

elab_net.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_net.cc,v 1.102 2002/11/09 19:20:48 steve Exp $"
+#ident "$Id: elab_net.cc,v 1.103 2002/12/06 03:08:19 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1538,18 +1538,17 @@ NetNet* PEIdent::elaborate_lnet(Design*des, NetScope*scope,
 
 	/* Don't allow registers as assign l-values. */
       if (sig->type() == NetNet::REG) {
-	    cerr << get_line() << ": error: registers (" << sig->name()
-		 << ") cannot be l-values in continuous"
+	    cerr << get_line() << ": error: reg " << sig->name()
+		 << "; cannot be an L-value in continuous"
 		 << " assignments." << endl;
 	    return 0;
       }
 
       if (sig->port_type() == NetNet::PINPUT) {
-	    cerr << get_line() << ": warning: assign l-value ``"
-		 << sig->name() << "'' is also an input to "
-		 << sig->scope()->name() << "." << endl;
-	    cerr << sig->get_line() << ": warning: input ``"
-		 << sig->name() << "'' is coerced to inout." << endl;
+	    cerr << get_line() << ": warning: L-value ``"
+		 << sig->name() << "'' is also an input port." << endl;
+	    cerr << sig->get_line() << ": warning: input "
+		 << sig->name() << "; is coerced to inout." << endl;
 	    sig->port_type(NetNet::PINOUT);
       }
 
@@ -2279,6 +2278,9 @@ NetNet* PEUnary::elaborate_net(Design*des, NetScope*scope,
 
 /*
  * $Log: elab_net.cc,v $
+ * Revision 1.103  2002/12/06 03:08:19  steve
+ *  Reword some error messages for clarity.
+ *
  * Revision 1.102  2002/11/09 19:20:48  steve
  *  Port expressions for output ports are lnets, not nets.
  *

elab_pexpr.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elab_pexpr.cc,v 1.17 2002/11/09 01:40:19 steve Exp $"
+#ident "$Id: elab_pexpr.cc,v 1.18 2002/12/05 02:14:33 steve Exp $"
 #endif
 
 # include "config.h"
@@ -145,15 +145,26 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
 	    return 0;
       }
 
-      if (msb_ || lsb_ || idx_) {
-	    cerr << get_line() << ": error: Cannot bit/part select "
-		  "bits of parameters." << endl;
-	    des->errors += 1;
-      }
-
       NetExpr*res = new NetEParam(des, pscope, hname_t(name));
       assert(res);
       delete name;
+
+      assert(idx_ == 0);
+      if (msb_ && lsb_) {
+	    cerr << get_line() << ": sorry: Cannot part select "
+		  "bits of parameters." << endl;
+	    des->errors += 1;
+
+      } else if (msb_) {
+
+	      /* We have here a bit select. Insert a NetESelect node
+		 to handle it. */
+	    NetExpr*tmp = msb_->elaborate_pexpr(des, scope);
+	    if (tmp != 0) {
+		  res = new NetESelect(res, tmp, 1);
+	    }
+      }
+
       return res;
 }
 
@@ -217,6 +228,9 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
 
 /*
  * $Log: elab_pexpr.cc,v $
+ * Revision 1.18  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
  * Revision 1.17  2002/11/09 01:40:19  steve
  *  Postpone parameter width check to evaluation.
  *

elaborate.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: elaborate.cc,v 1.264 2002/11/09 19:20:48 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.266 2002/12/05 04:15:14 steve Exp $"
 #endif
 
 # include "config.h"
@@ -975,7 +975,7 @@ NetProc* PAssign::elaborate(Design*des, NetScope*scope) const
 	    rv->set_width(wid);
 	    rv = pad_to_width(rv, wid);
 
-	    if (! rv->set_width(wid)) {
+	    if (wid != rv->expr_width()) {
 		  cerr << get_line() << ": error: Unable to match "
 			"expression width of " << rv->expr_width() <<
 			" to l-value width of " << wid << "." << endl;
@@ -1076,6 +1076,12 @@ NetProc* PAssignNB::elaborate(Design*des, NetScope*scope) const
 
       assert(rv);
 
+	/* Try to evaluate the expression, at least as far as possible. */
+      if (NetExpr*tmp = rv->eval_tree()) {
+	    delete rv;
+	    rv = tmp;
+      }
+
       { unsigned wid = count_lval_width(lv);
         rv->set_width(wid);
 	rv = pad_to_width(rv, wid);
@@ -1351,6 +1357,17 @@ NetProc* PCallTask::elaborate_sys(Design*des, NetScope*scope) const
       for (unsigned idx = 0 ;  idx < parm_count ;  idx += 1) {
 	    PExpr*ex = parm(idx);
 	    eparms[idx] = ex? ex->elaborate_expr(des, scope, true) : 0;
+
+	      /* Attempt to pre-evaluate the parameters. It may be
+		 possible to at least partially reduce the
+		 expression. */
+	    if (eparms[idx] && !dynamic_cast<NetEConst*>(eparms[idx])) {
+		  NetExpr*tmp = eparms[idx]->eval_tree();
+		  if (tmp != 0) {
+			delete eparms[idx];
+			eparms[idx] = tmp;
+		  }
+	    }
       }
 
       NetSTask*cur = new NetSTask(path_.peek_name(0), eparms);
@@ -2472,6 +2489,12 @@ Design* elaborate(list<const char*>roots)
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.266  2002/12/05 04:15:14  steve
+ *  precalculate r-values of nb assignments and task arguments.
+ *
+ * Revision 1.265  2002/11/26 03:35:13  steve
+ *  Do not set width if width is already OK.
+ *
  * Revision 1.264  2002/11/09 19:20:48  steve
  *  Port expressions for output ports are lnets, not nets.
  *

eval_tree.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: eval_tree.cc,v 1.43 2002/11/09 01:40:19 steve Exp $"
+#ident "$Id: eval_tree.cc,v 1.44 2002/12/05 02:14:33 steve Exp $"
 #endif
 
 # include "config.h"
@@ -894,6 +894,53 @@ NetExpr* NetEParam::eval_tree()
       return res->dup_expr();
 }
 
+NetEConst* NetESelect::eval_tree()
+{
+      NetEConst*expr = dynamic_cast<NetEConst*>(expr_);
+      if (expr == 0) {
+	    NetExpr*tmp = expr_->eval_tree();
+	    if (tmp != 0) {
+		  delete expr_;
+		  expr_ = tmp;
+	    }
+
+	    expr = dynamic_cast<NetEConst*>(expr_);
+      }
+
+      NetEConst*base = dynamic_cast<NetEConst*>(base_);
+      if (base == 0) {
+	    NetExpr*tmp = base_->eval_tree();
+	    if (tmp != 0) {
+		  delete base_;
+		  base_ = tmp;
+	    }
+
+	    base = dynamic_cast<NetEConst*>(base_);
+      }
+
+      if (expr == 0)
+	    return 0;
+      if (base == 0)
+	    return 0;
+
+      verinum eval = expr->value();
+      verinum oval (verinum::V0, expr_width(), true);
+      long bval = base->value().as_long();
+
+      for (long idx = 0 ;  idx < expr_width() ;  idx += 1) {
+	    if ((bval >= eval.len()) || (bval < 0))
+		  oval.set(idx, verinum::Vx);
+	    else 
+		  oval.set(idx, eval.get(bval));
+
+	    bval += 1;
+      }
+
+      NetEConst*res = new NetEConst(oval);
+      return res;
+}
+
+
 /*
  * A ternary expression evaluation is controlled by the condition
  * expression. If the condition evaluates to true or false, then
@@ -1140,6 +1187,9 @@ NetEConst* NetEUReduce::eval_tree()
 
 /*
  * $Log: eval_tree.cc,v $
+ * Revision 1.44  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
  * Revision 1.43  2002/11/09 01:40:19  steve
  *  Postpone parameter width check to evaluation.
  *

expr_synth.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: expr_synth.cc,v 1.36 2002/08/12 01:34:59 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.37 2002/11/17 23:37:55 steve Exp $"
 #endif
 
 # include "config.h"
@@ -192,6 +192,33 @@ NetNet* NetEBComp::synthesize(Design*des)
 		  gate = new NetLogic(scope, des->local_symbol(path),
 				      lsig->pin_count()+1, NetLogic::OR);
 		  break;
+
+		case '>':
+		    /* sig > 0 is true if any bit in sig is set. This
+		       is very much like sig != 0. (0 > sig) shouldn't
+		       happen. */
+		  if (rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
+		case '<':
+		    /* 0 < sig is handled like sig > 0. */
+		  if (! rcon) {
+			gate = new NetLogic(scope, des->local_symbol(path),
+					    lsig->pin_count()+1, NetLogic::OR);
+		  } else {
+			assert(0);
+			gate = new NetLogic(scope, des->local_symbol(path),
+				      lsig->pin_count()+1, NetLogic::NOR);
+		  }
+		  break;
+
 		default:
 		  assert(0);
 	    }
@@ -608,6 +635,9 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.37  2002/11/17 23:37:55  steve
+ *  Magnitude compare to 0.
+ *
  * Revision 1.36  2002/08/12 01:34:59  steve
  *  conditional ident string using autoconfig.
  *

iverilog-vpi.man

@@ -1,4 +1,4 @@
-.TH iverilog-vpi 1 "$Date: 2002/07/05 17:17:20 $" Version "$Date: 2002/07/05 17:17:20 $"
+.TH iverilog-vpi 1 "$Date: 2002/11/23 00:51:53 $" Version "$Date: 2002/11/23 00:51:53 $"
 .SH NAME
 iverilog-vpi - Compile front end for VPI modules
 
@@ -32,13 +32,37 @@ VPI modules to further reference external libraries.
 Normally, the output VPI module will be named after the first source
 file passed to the command. This flag sets the name (without the .vpi
 suffix) of the output vpi module.
+
+.SH "PC-ONLY OPTIONS"
+
+The PC port of \fIiverilog-vpi\fP includes two special flags needed to
+support the more intractable development environment. These flags help
+the program locate parts that it needs.
+
+.TP 8
+.B -mingw=\fIpath\fP
+Tell the program the root of the Mingw compiler tool suite. The
+\fBvvp\fP runtime is compiled with this compiler, and this is the
+compiler that \fIiverilog-vpi\fP expects to use to compile your source
+code. This is notmally not needed, and if you do use it, it is only
+needed once. The compiler will save the \fIpath\fP in the registry for
+use later.
+
+.TP 8
+.B -ivl=\fIpath\fP
+Set for the use during compilation the root if the Icarus Verilog
+install. This is the place where you installed Icarus Verilog when you
+ran the installer. This flag is also only needed once, and the path is
+stored in the registry for future use.
+
 .SH "AUTHOR"
 .nf
 Steve Williams ([email protected])
 
 .SH SEE ALSO
 iverilog(1), vvp(1),
-.BR "<http://www.icarus.com/eda/verilog/>"
+.BR "<http://www.icarus.com/eda/verilog/>",
+.BR "<http://www.mingw.org>",
 
 .SH COPYRIGHT
 .nf

lexor.lex

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: lexor.lex,v 1.73 2002/06/06 18:57:18 steve Exp $"
+#ident "$Id: lexor.lex,v 1.74 2002/12/04 02:07:00 steve Exp $"
 #endif
 
 # include "config.h"
@@ -375,7 +375,7 @@ W [ \t\b\f\r]+
       if (isgraph(yytext[0]))
 	    cerr << yytext[0];
       else
-	    cerr << (unsigned)yytext[0];
+	    cerr << "hex " << hex << (0xffU & ((unsigned) (yytext[0])));
 
       cerr << ")" << endl; }
 

net_design.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: net_design.cc,v 1.29 2002/11/02 03:27:52 steve Exp $"
+#ident "$Id: net_design.cc,v 1.30 2002/12/07 02:49:24 steve Exp $"
 #endif
 
 # include "config.h"
@@ -501,24 +501,27 @@ NetScope* Design::find_task(const hname_t&key)
       return 0;
 }
 
-NetEvent* Design::find_event(NetScope*scope, const hname_t&path)
+NetEvent* Design::find_event(NetScope*scope, const hname_t&p)
 {
+      hname_t path = p;
       assert(scope);
 
+      char*key = path.remove_tail_name();
+      if (path.peek_name(0))
+	    scope = find_scope(scope, path);
+
       while (scope) {
-	    if (NetEvent*ev = scope->find_event(path)) {
+	    if (NetEvent*ev = scope->find_event(key)) {
+		  delete key;
 		  return ev;
 	    }
 
-	      // If this is a simple name, then do not scan up scopes
-	      // past a module scope. This is a Verilog scoping rule.
-	    if ((path.component_count() == 1)
-		&& (scope->type() == NetScope::MODULE))
+	    if (scope->type() == NetScope::MODULE)
 		  break;
-
 	    scope = scope->parent();
       }
 
+      delete key;
       return 0;
 }
 
@@ -597,6 +600,9 @@ void Design::delete_process(NetProcTop*top)
 
 /*
  * $Log: net_design.cc,v $
+ * Revision 1.30  2002/12/07 02:49:24  steve
+ *  Named event triggers can take hierarchical names.
+ *
  * Revision 1.29  2002/11/02 03:27:52  steve
  *  Allow named events to be referenced by
  *  hierarchical names.

net_scope.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: net_scope.cc,v 1.20 2002/10/19 22:59:49 steve Exp $"
+#ident "$Id: net_scope.cc,v 1.21 2002/12/07 02:49:24 steve Exp $"
 #endif
 
 # include "config.h"
@@ -255,10 +255,10 @@ void NetScope::rem_event(NetEvent*ev)
 }
 
 
-NetEvent* NetScope::find_event(const hname_t&name)
+NetEvent* NetScope::find_event(const char*name)
 {
       for (NetEvent*cur = events_;  cur ;  cur = cur->snext_)
-	    if (strcmp(cur->name(), name.peek_tail_name()) == 0)
+	    if (strcmp(cur->name(), name) == 0)
 		  return cur;
 
       return 0;
@@ -432,6 +432,9 @@ string NetScope::local_hsymbol()
 
 /*
  * $Log: net_scope.cc,v $
+ * Revision 1.21  2002/12/07 02:49:24  steve
+ *  Named event triggers can take hierarchical names.
+ *
  * Revision 1.20  2002/10/19 22:59:49  steve
  *  Redo the parameter vector support to allow
  *  parameter names in range expressions.

netlist.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: netlist.h,v 1.269 2002/11/09 01:40:19 steve Exp $"
+#ident "$Id: netlist.h,v 1.271 2002/12/07 02:49:24 steve Exp $"
 #endif
 
 /*
@@ -2494,6 +2494,7 @@ class NetESelect  : public NetExpr {
       virtual bool set_width(unsigned w);
       virtual bool has_width() const;
       virtual void expr_scan(struct expr_scan_t*) const;
+      virtual NetEConst* eval_tree();
       virtual NetESelect* dup_expr() const;
 
     private:
@@ -2794,7 +2795,7 @@ class NetScope {
 
       void add_event(NetEvent*);
       void rem_event(NetEvent*);
-      NetEvent*find_event(const hname_t&name);
+      NetEvent*find_event(const char*name);
 
 
 	/* These methods manage signals. The add_ and rem_signal
@@ -3084,6 +3085,12 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.271  2002/12/07 02:49:24  steve
+ *  Named event triggers can take hierarchical names.
+ *
+ * Revision 1.270  2002/12/05 02:14:33  steve
+ *  Support bit select in constant expressions.
+ *
  * Revision 1.269  2002/11/09 01:40:19  steve
  *  Postpone parameter width check to evaluation.
  *

parse.y

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: parse.y,v 1.164 2002/11/09 02:22:07 steve Exp $"
+#ident "$Id: parse.y,v 1.167 2002/12/07 02:49:24 steve Exp $"
 #endif
 
 # include "config.h"
@@ -2084,6 +2084,7 @@ specify_item_list
 
 specify_edge_path_decl
 	: specify_edge_path '=' '(' specify_delay_value_list ')'
+	| specify_edge_path '=' delay_value_simple
 	;
 
 specify_edge_path
@@ -2139,9 +2140,9 @@ specparam
 		  delete $5;
 		  delete $7;
 		}
-	| PATHPULSE_IDENTIFIER '=' '(' expression ')'
+	| PATHPULSE_IDENTIFIER '=' expression
 		{ delete $1;
-		  delete $4;
+		  delete $3;
 		}
 	| PATHPULSE_IDENTIFIER '=' '(' expression ',' expression ')'
 		{ delete $1;
@@ -2315,8 +2316,8 @@ statement
 		  delete $2;
 		  $$ = tmp;
 		}
-	| K_TRIGGER IDENTIFIER ';'
-		{ PTrigger*tmp = new PTrigger(hname_t($2));
+	| K_TRIGGER identifier ';'
+		{ PTrigger*tmp = new PTrigger(*$2);
 		  tmp->set_file(@2.text);
 		  tmp->set_lineno(@2.first_line);
 		  delete $2;

tgt-fpga/d-virtex.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: d-virtex.c,v 1.18 2002/11/01 02:36:34 steve Exp $"
+#ident "$Id: d-virtex.c,v 1.21 2002/11/24 02:26:14 steve Exp $"
 #endif
 
 # include  "device.h"
@@ -38,6 +38,8 @@
  *     place-and-route step, as it is not normally needed within an
  *     FPGA net.
  *
+ *   BUFT       O, I, T
+ *
  *   INV        O, I
  *     Inverting buffer.
  *
@@ -74,6 +76,13 @@ static const char*virtex_library_text =
 "              (interface\n"
 "                 (port O (direction OUTPUT))\n"
 "                 (port I (direction INPUT)))))\n"
+"      (cell BUFT (cellType GENERIC)\n"
+"            (view net\n"
+"              (viewType NETLIST)\n"
+"              (interface\n"
+"                 (port O (direction OUTPUT))\n"
+"                 (port I (direction OUTPUT))\n"
+"                 (port T (direction INPUT)))))\n"
 "      (cell FDCE (cellType GENERIC)\n"
 "            (view net\n"
 "              (viewType NETLIST)\n"
@@ -422,6 +431,227 @@ void edif_show_cellref_logic(ivl_net_logic_t net, const char*cellref)
       }
 }
 
+/*
+ * This function draw wide AND-like devices. The input must have at
+ * least 5 bits.
+ */
+static void wide_AND_logic(ivl_net_logic_t net, unsigned edif_uref)
+{
+      char jbuf[1024];
+
+	/* This is the number of input bits left to connect. */
+      unsigned ibits = ivl_logic_pins(net) - 1;
+	/* Index to the next input bit. */
+      unsigned idx = 1;
+      unsigned slice = 0;
+
+      const char*lut4_init;
+      const char*lut3_init;
+      const char*lut2_init;
+      const char*lut1_dev;
+
+      switch (ivl_logic_type(net)) {
+	  case IVL_LO_AND:
+	    lut4_init = "\"8000\"";
+	    lut3_init = "\"80\"";
+	    lut2_init = "\"8\"";
+	    lut1_dev  = "BUF";
+	    break;
+	  case IVL_LO_NOR:
+	    lut4_init = "\"0001\"";
+	    lut3_init = "\"01\"";
+	    lut2_init = "\"1\"";
+	    lut1_dev  = "INV";
+	    break;
+	  default:
+	    assert(0);
+      }
+
+      assert(ibits > 4);
+
+      while (ibits >= 4) {
+
+	      /* The least significant bits are ANDed together 4 at a
+		 time with LUT4 devices. The output of the LUT4 device
+		 connects to a MUXCY device that passes its output
+		 up to the next stage.
+
+		 The DI input of the MUXCY (S==0) is connected to
+		 ground, so that the ouput of the chain is pinned to 0
+		 if this slice does not AND to 1.
+
+		 If the LUT emits 1, S==1 and this slice passes the
+		 compare from below. So the CI of the MUXCY gets the O
+		 of the MUXCY one slice back. */
+
+	    fprintf(xnf, "(instance U%uL%u"
+		    " (viewRef net"
+		    " (cellRef LUT4 (libraryRef VIRTEX)))"
+		    " (property INIT (string %s)))\n",
+		    edif_uref, slice, lut4_init);
+
+	    fprintf(xnf, "(instance U%uM%u"
+		    " (viewRef net"
+		    " (cellRef MUXCY (libraryRef VIRTEX))))\n",
+		    edif_uref, slice);
+
+	    fprintf(xnf, "(instance U%uG%u"
+		    " (viewRef net"
+		    " (cellRef GND (libraryRef VIRTEX))))\n",
+		    edif_uref, slice);
+
+	    fprintf(xnf, "(net U%uLM%u (joined"
+		    " (portRef O (instanceRef U%uL%u))"
+		    " (portRef S (instanceRef U%uM%u))))\n",
+		    edif_uref, slice,
+		    edif_uref, slice,
+		    edif_uref, slice);
+
+	    fprintf(xnf, "(net U%uGM%u (joined"
+		    " (portRef GROUND (instanceRef U%uG%u))"
+		    " (portRef DI (instanceRef U%uM%u))))\n",
+		    edif_uref, slice,
+		    edif_uref, slice,
+		    edif_uref, slice);
+
+	    if (slice == 0) {
+		  fprintf(xnf, "(instance U%uV%u"
+			  " (viewRef net"
+			  " (cellRef VCC (libraryRef VIRTEX))))\n",
+			  edif_uref, slice);
+
+		  fprintf(xnf, "(net U%uMM%u (joined"
+			  " (portRef VCC (instanceRef U%uG%u))"
+			  " (portRef CI (instanceRef U%uM%u))))\n",
+			  edif_uref, slice,
+			  edif_uref, slice,
+			  edif_uref, slice);
+	    } else {
+		  fprintf(xnf, "(net U%uMM%u (joined"
+			  " (portRef O (instanceRef U%uM%u))"
+			  " (portReg CI (instanceRef U%uM%u))))\n",
+			  edif_uref, slice,
+			  edif_uref, slice-1,
+			  edif_uref, slice);
+	    }
+
+	    sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
+
+	    sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
+
+	    sprintf(jbuf, "(portRef I2 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+2), jbuf);
+
+	    sprintf(jbuf, "(portRef I3 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+3), jbuf);
+
+	    ibits -= 4;
+	    idx   += 4;
+	    slice += 1;
+      }
+
+      if (ibits == 0) {
+	    sprintf(jbuf, "(portRef O (instanceRef U%uM%u))",
+		    edif_uref, slice-1);
+	    edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
+	    return;
+      }
+
+      switch (ibits) {
+
+	  case 1:
+	    fprintf(xnf, "(instance U%uL%u"
+		    " (viewRef net"
+		    " (cellRef %s (libraryRef VIRTEX))))\n",
+		    edif_uref, slice, lut1_dev);
+
+	    sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
+	    break;
+
+	  case 2:
+	    fprintf(xnf, "(instance U%uL%u"
+		   " (viewRef net"
+		   " (cellRef LUT2 (libraryRef VIRTEX)))"
+		   " (property INIT (string %s)))\n",
+		   edif_uref, slice, lut2_init);
+
+	    sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
+
+	    sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
+	    break;
+
+	  case 3:
+	    fprintf(xnf, "(instance U%uL%u"
+		   " (viewRef net"
+		   " (cellRef LUT3 (libraryRef VIRTEX)))"
+		   " (property INIT (string %s)))\n",
+		   edif_uref, slice, lut3_init);
+
+	    sprintf(jbuf, "(portRef I0 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+0), jbuf);
+
+	    sprintf(jbuf, "(portRef I1 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+1), jbuf);
+
+	    sprintf(jbuf, "(portRef I2 (instanceRef U%uL%u))",
+		    edif_uref, slice);
+	    edif_set_nexus_joint(ivl_logic_pin(net, idx+2), jbuf);
+	    break;
+
+	  default:
+	    assert(0);
+      }
+
+      fprintf(xnf, "(instance U%uM%u"
+	     " (viewRef net"
+	     " (cellRef MUXCY (libraryRef VIRTEX))))\n",
+	     edif_uref, slice);
+
+      fprintf(xnf, "(instance U%uG%u"
+	      " (viewRef net"
+	      " (cellRef GND (libraryRef VIRTEX))))\n",
+	      edif_uref, slice);
+
+      fprintf(xnf, "(net U%uLM%u (joined"
+	      " (portRef O (instanceRef U%uL%u))"
+	      " (portRef S (instanceRef U%uM%u))))\n",
+	      edif_uref, slice,
+	      edif_uref, slice,
+	      edif_uref, slice);
+
+      fprintf(xnf, "(net U%uGM%u (joined"
+	      " (portRef GROUND (instanceRef U%uG%u))"
+	      " (portRef DI (instanceRef U%uM%u))))\n",
+	      edif_uref, slice,
+	      edif_uref, slice,
+	      edif_uref, slice);
+
+      fprintf(xnf, "(net U%uMM%u (joined"
+	      " (portRef O (instanceRef U%uM%u))"
+	      " (portReg CI (instanceRef U%uM%u))))\n",
+	      edif_uref, slice,
+	      edif_uref, slice-1,
+	      edif_uref, slice);
+
+      sprintf(jbuf, "(portRef O (instanceRef U%uM%u))",
+	      edif_uref, slice);
+      edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
+}
+
 static void edif_show_virtex_logic(ivl_net_logic_t net)
 {
       char jbuf[1024];
@@ -438,7 +668,6 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
       switch (ivl_logic_type(net)) {
 
 	  case IVL_LO_AND:
-	    assert(ivl_logic_pins(net) <= 5);
 	    assert(ivl_logic_pins(net) >= 3);
 
 	    switch (ivl_logic_pins(net)) {
@@ -463,6 +692,9 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
 				 ivl_logic_pin(net, 3),
 				 ivl_logic_pin(net, 4), "8000");
 		  break;
+		default:
+		  wide_AND_logic(net, edif_uref);
+		  break;
 	    }
 	    break;
 
@@ -481,8 +713,24 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
 	    edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
 	    break;
 
+	  case IVL_LO_BUFIF1:
+	    assert(ivl_logic_pins(net) == 3);
+	    fprintf(xnf, "(instance (rename U%u \"%s\")",
+		    edif_uref, ivl_logic_name(net));
+	    fprintf(xnf, " (viewRef net"
+		    " (cellRef TBUF (libraryRef VIRTEX))))\n");
+
+	    sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
+	    edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
+
+	    sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
+	    edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
+
+	    sprintf(jbuf, "(portRef T (instanceRef U%u))", edif_uref);
+	    edif_set_nexus_joint(ivl_logic_pin(net, 2), jbuf);
+	    break;
+
 	  case IVL_LO_NOR:
-	    assert(ivl_logic_pins(net) <= 5);
 	    assert(ivl_logic_pins(net) >= 3);
 
 	    switch (ivl_logic_pins(net)) {
@@ -507,6 +755,9 @@ static void edif_show_virtex_logic(ivl_net_logic_t net)
 				 ivl_logic_pin(net, 3),
 				 ivl_logic_pin(net, 4), "0001");
 		  break;
+		default:
+		  wide_AND_logic(net, edif_uref);
+		  break;
 	    }
 	    break;
 
@@ -1657,6 +1908,15 @@ const struct device_s d_virtex_edif = {
 
 /*
  * $Log: d-virtex.c,v $
+ * Revision 1.21  2002/11/24 02:26:14  steve
+ *  Fix instanceRef spelling.
+ *
+ * Revision 1.20  2002/11/22 05:46:06  steve
+ *  Handle wide AND/NOR devices with Virtex carry logic.
+ *
+ * Revision 1.19  2002/11/22 01:45:40  steve
+ *  Implement bufif1 as BUFT
+ *
  * Revision 1.18  2002/11/01 02:36:34  steve
  *  Fix bottom bit of ADD/SUB device.
  *

tgt-vvp/eval_expr.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: eval_expr.c,v 1.84 2002/11/07 03:12:17 steve Exp $"
+#ident "$Id: eval_expr.c,v 1.86 2002/11/22 00:01:50 steve Exp $"
 #endif
 
 # include  "vvp_priv.h"
@@ -661,15 +661,51 @@ static struct vector_info draw_binary_expr_lrs(ivl_expr_t exp, unsigned wid)
 	    }
       }
 
-      lv = draw_eval_expr_wid(le, wid, 0);
 
       switch (ivl_expr_opcode(exp)) {
 
 	  case 'l': /* << (left shift) */
+	    lv = draw_eval_expr_wid(le, wid, 0);
+
+	      /* shifting 0 gets 0. */
+	    if (lv.base == 0)
+		  break;
+
+	    if (lv.base < 4) {
+		  struct vector_info tmp;
+		  tmp.base = allocate_vector(lv.wid);
+		  tmp.wid = lv.wid;
+		  fprintf(vvp_out, "    %%mov %u, %u, %u;\n",
+			  tmp.base, lv.base, lv.wid);
+		  lv = tmp;
+	    }
 	    fprintf(vvp_out, "    %%shiftl/i0  %u, %u;\n", lv.base, lv.wid);
 	    break;
 
 	  case 'r': /* >> (unsigned right shift) */
+
+	      /* with the right shift, there may be high bits that are
+		 shifted into the desired width of the expression, so
+		 we let the expression size itself, if it is bigger
+		 then what is requested of us. */
+	    if (wid > ivl_expr_width(le)) {
+		  lv = draw_eval_expr_wid(le, wid, 0);
+	    } else {
+		  lv = draw_eval_expr_wid(le, ivl_expr_width(le), 0);
+	    }
+
+	      /* shifting 0 gets 0. */
+	    if (lv.base == 0)
+		  break;
+
+	    if (lv.base < 4) {
+		  struct vector_info tmp;
+		  tmp.base = allocate_vector(lv.wid);
+		  tmp.wid = lv.wid;
+		  fprintf(vvp_out, "    %%mov %u, %u, %u;\n",
+			  tmp.base, lv.base, lv.wid);
+		  lv = tmp;
+	    }
 	    fprintf(vvp_out, "    %%shiftr/i0  %u, %u;\n", lv.base, lv.wid);
 	    break;
 
@@ -1927,6 +1963,12 @@ struct vector_info draw_eval_expr(ivl_expr_t exp, int stuff_ok_flag)
 
 /*
  * $Log: eval_expr.c,v $
+ * Revision 1.86  2002/11/22 00:01:50  steve
+ *  Careful of left operands to shift that are constant.
+ *
+ * Revision 1.85  2002/11/21 22:42:48  steve
+ *  Allow right values of right shift to shift in.
+ *
  * Revision 1.84  2002/11/07 03:12:17  steve
  *  Vectorize load from REG variables.
  *

tgt-vvp/vvp_process.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: vvp_process.c,v 1.75 2002/11/17 18:31:09 steve Exp $"
+#ident "$Id: vvp_process.c,v 1.76 2002/11/21 22:43:13 steve Exp $"
 #endif
 
 # include  "vvp_priv.h"
@@ -79,8 +79,8 @@ static void set_to_lvariable(ivl_lval_t lval, unsigned idx,
 
       if (ivl_lval_mux(lval)) {
 	    assert(wid == 1);
-	    fprintf(vvp_out, "    %%set/x V_%s, %u, 0;\n",
-		    vvp_signal_label(sig), bit);
+	    fprintf(vvp_out, "    %%set/x0 V_%s, %u, %u;\n",
+		    vvp_signal_label(sig), bit, ivl_signal_pins(sig)-1);
       } else if (wid == 1) {
 	    fprintf(vvp_out, "    %%set V_%s[%u], %u;\n",
 		    vvp_signal_label(sig), idx+part_off, bit);
@@ -191,6 +191,8 @@ static int show_stmt_assign(ivl_statement_t net)
 		       value and write it into index0. */
 		  if (ivl_lval_mux(lval)) {
 			calculate_into_x0(ivl_lval_mux(lval));
+			  /* Generate code to skip around the set
+			     if the index has X values. */
 			fprintf(vvp_out, "    %%jmp/1 t_%u, 4;\n", skip_set);
 			skip_set_flag = 1;
 		  }
@@ -198,6 +200,8 @@ static int show_stmt_assign(ivl_statement_t net)
 		  mem = ivl_lval_mem(lval);
 		  if (mem) {
 			draw_memory_index_expr(mem, ivl_lval_idx(lval));
+			  /* Generate code to skip around the set
+			     if the index has X values. */
 			fprintf(vvp_out, "    %%jmp/1 t_%u, 4;\n", skip_set);
 			skip_set_flag = 1;
 		  }
@@ -234,14 +238,7 @@ static int show_stmt_assign(ivl_statement_t net)
 			      idx += cnt;
 			}
 
-#if 0
-			for (idx = 0 ;  idx < bit_limit ;  idx += 1) {
-			      set_to_lvariable(lval, idx,
-					       bitchar_to_idx(bits[cur_rbit]), 1);
 
-			      cur_rbit += 1;
-			}
-#endif
 			if (bit_limit < ivl_lval_pins(lval)) {
 			      unsigned cnt = ivl_lval_pins(lval) - bit_limit;
 			      set_to_lvariable(lval, bit_limit, 0, cnt);
@@ -1452,6 +1449,9 @@ int draw_func_definition(ivl_scope_t scope)
 
 /*
  * $Log: vvp_process.c,v $
+ * Revision 1.76  2002/11/21 22:43:13  steve
+ *  %set/x0 instruction to support bounds checking.
+ *
  * Revision 1.75  2002/11/17 18:31:09  steve
  *  Generate unique labels for force functors.
  *

tgt-vvp/vvp_scope.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: vvp_scope.c,v 1.80 2002/10/23 04:39:35 steve Exp $"
+#ident "$Id: vvp_scope.c,v 1.81 2002/11/21 18:08:09 steve Exp $"
 #endif
 
 # include  "vvp_priv.h"
@@ -1367,10 +1367,21 @@ static void draw_lpm_ff(ivl_lpm_t net)
 static void draw_lpm_shiftl(ivl_lpm_t net)
 {
       unsigned idx, width, selects;
+      unsigned selwid;
 
       width = ivl_lpm_width(net);
       selects = ivl_lpm_selects(net);
 
+	/* The .shift device can only take as many select inputs as
+	   the width of the device.
+
+	   XXXX I should make some sort of overflow gate for this? If
+	   any high bits are set, then the shift is certain to be
+	   *way* beyond the width of the left shifted value. XXXX */
+      selwid = selects;
+      if (selwid > width)
+	    selwid = width;
+
       if (ivl_lpm_type(net) == IVL_LPM_SHIFTR)
 	    fprintf(vvp_out, "L_%s .shift/r %u", 
 		    vvp_mangle_id(ivl_lpm_name(net)), width);
@@ -1383,11 +1394,15 @@ static void draw_lpm_shiftl(ivl_lpm_t net)
 	    draw_input_from_net(ivl_lpm_data(net, idx));
       }
 
-      for (idx = 0 ;  idx < selects ;  idx += 1) {
+      for (idx = 0 ;  idx < selwid ;  idx += 1) {
 	    fprintf(vvp_out, ", ");
 	    draw_input_from_net(ivl_lpm_select(net, idx));
       }
 
+      for (idx = selwid ;  idx < width ;  idx += 1) {
+	    fprintf(vvp_out, ", C<0>");
+      }
+
       fprintf(vvp_out, ";\n");
 }
 
@@ -1592,6 +1607,9 @@ int draw_scope(ivl_scope_t net, ivl_scope_t parent)
 
 /*
  * $Log: vvp_scope.c,v $
+ * Revision 1.81  2002/11/21 18:08:09  steve
+ *  Better handling of select width of shifters.
+ *
  * Revision 1.80  2002/10/23 04:39:35  steve
  *  draw lpm ff with aset_expr taken into account.
  *

verilog.spec

@@ -1,10 +1,10 @@
 Summary: Icarus Verilog
 Name: verilog
-Version: 0.6.20021117
+Version: 0.6.20021207
 Release: 0
 Copyright: GPL
 Group: Applications/Engineering
-Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20021117.tar.gz
+Source: ftp://icarus.com/pub/eda/verilog/snapshots/verilog-20021207.tar.gz
 URL: http://www.icarus.com/eda/verilog/index.html
 Packager: Stephen Williams <[email protected]>
 
@@ -20,7 +20,7 @@ engineering formats, including simulation. It strives to be true
 to the IEEE-1364 standard.
 
 %prep
-%setup -n verilog-20021117
+%setup -n verilog-20021207
 
 %build
 ./configure --prefix=/usr

vpi/sys_lxt.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: sys_lxt.c,v 1.11 2002/08/15 02:12:20 steve Exp $"
+#ident "$Id: sys_lxt.c,v 1.12 2002/11/17 22:28:42 steve Exp $"
 #endif
 
 # include "config.h"
@@ -460,6 +460,9 @@ static int sys_dumpfile_calltf(char*name)
 	    path = strdup("dumpfile.lxt");
       }
 
+      if (dump_file)
+	    close_dumpfile();
+
       assert(dump_file == 0);
       open_dumpfile(path);
 
@@ -814,6 +817,9 @@ void sys_lxt_register()
 
 /*
  * $Log: sys_lxt.c,v $
+ * Revision 1.12  2002/11/17 22:28:42  steve
+ *  Close old file if $dumpfile is called again.
+ *
  * Revision 1.11  2002/08/15 02:12:20  steve
  *  add dumpvars_compiletf to check first argument.
  *

vpi/sys_vcd.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: sys_vcd.c,v 1.38 2002/11/14 22:43:58 steve Exp $"
+#ident "$Id: sys_vcd.c,v 1.39 2002/11/17 22:28:42 steve Exp $"
 #endif
 
 # include "config.h"
@@ -449,6 +449,11 @@ static int sys_dumpfile_calltf(char*name)
 	    path = strdup("dumpfile.vcd");
       }
 
+      if (dump_file) {
+	    fclose(dump_file);
+	    dump_file = 0;
+      }
+
       assert(dump_file == 0);
       open_dumpfile(path);
 
@@ -844,6 +849,9 @@ void sys_vcd_register()
 
 /*
  * $Log: sys_vcd.c,v $
+ * Revision 1.39  2002/11/17 22:28:42  steve
+ *  Close old file if $dumpfile is called again.
+ *
  * Revision 1.38  2002/11/14 22:43:58  steve
  *  Save vpiFullName results.
  *

vvp/codes.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: codes.h,v 1.53 2002/11/08 04:59:57 steve Exp $"
+#ident "$Id: codes.h,v 1.54 2002/11/21 22:43:13 steve Exp $"
 #endif
 
 
@@ -92,7 +92,7 @@ extern bool of_RELEASE(vthread_t thr, vvp_code_t code);
 extern bool of_SET(vthread_t thr, vvp_code_t code);
 extern bool of_SET_MEM(vthread_t thr, vvp_code_t code);
 extern bool of_SET_VEC(vthread_t thr, vvp_code_t code);
-extern bool of_SET_X(vthread_t thr, vvp_code_t code);
+extern bool of_SET_X0(vthread_t thr, vvp_code_t code);
 extern bool of_SHIFTL_I0(vthread_t thr, vvp_code_t code);
 extern bool of_SHIFTR_I0(vthread_t thr, vvp_code_t code);
 extern bool of_SUB(vthread_t thr, vvp_code_t code);
@@ -160,6 +160,9 @@ extern vvp_code_t codespace_index(vvp_cpoint_t ptr);
 
 /*
  * $Log: codes.h,v $
+ * Revision 1.54  2002/11/21 22:43:13  steve
+ *  %set/x0 instruction to support bounds checking.
+ *
  * Revision 1.53  2002/11/08 04:59:57  steve
  *  Add the %assign/v0 instruction.
  *

vvp/compile.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: compile.cc,v 1.145 2002/11/08 04:59:58 steve Exp $"
+#ident "$Id: compile.cc,v 1.146 2002/11/21 22:43:13 steve Exp $"
 #endif
 
 # include  "arith.h"
@@ -137,7 +137,7 @@ const static struct opcode_table_s opcode_table[] = {
       { "%set",    of_SET,    2,  {OA_FUNC_PTR, OA_BIT1,     OA_NONE} },
       { "%set/m",  of_SET_MEM,2,  {OA_MEM_PTR,  OA_BIT1,     OA_NONE} },
       { "%set/v",  of_SET_VEC,3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
-      { "%set/x",  of_SET_X,  3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
+      { "%set/x0", of_SET_X0, 3,  {OA_FUNC_PTR, OA_BIT1,     OA_BIT2} },
       { "%shiftl/i0", of_SHIFTL_I0, 2, {OA_BIT1,OA_NUMBER,   OA_NONE} },
       { "%shiftr/i0", of_SHIFTR_I0, 2, {OA_BIT1,OA_NUMBER,   OA_NONE} },
       { "%sub",    of_SUB,    3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
@@ -1483,6 +1483,9 @@ void compile_net(char*label, char*name, int msb, int lsb, bool signed_flag,
 
 /*
  * $Log: compile.cc,v $
+ * Revision 1.146  2002/11/21 22:43:13  steve
+ *  %set/x0 instruction to support bounds checking.
+ *
  * Revision 1.145  2002/11/08 04:59:58  steve
  *  Add the %assign/v0 instruction.
  *

vvp/opcodes.txt

@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2001 Stephen Williams ([email protected])
  *
- *  $Id: opcodes.txt,v 1.44 2002/11/08 04:59:58 steve Exp $
+ *  $Id: opcodes.txt,v 1.45 2002/11/21 22:43:13 steve Exp $
  */
 
 
@@ -459,15 +459,17 @@ address zero is the LSB of the first memory word.  This instruction
 sets only a single bit.
 
 
-* %set/x <var-label>, <bit>, <idx>
+* %set/x0 <var-label>, <bit>, <top>
 
 This sets the bit of a variable functor, the address calculated by
-using the index register <idx> (0, 1, 2 or 3) to index the functor
-address of <var-label>.
+using the index register 0 to index the functor address of
+<var-label>.
 
-If the index value in index register <idx> is <0 (for example if
-%ix/get converted an unknown value into the register) then the set is
-not performed.
+If the index value in index register is <0 (for example if %ix/get
+converted an unknown value into the register) then the set is not
+performed. Also, if the index value is > the immediate top value, then
+the set is not performed. The 0 and <top> values suffice to provide
+complete bounds checking.
 
 
 * %shiftl/i0 <bit>, <wid>

vvp/vpi_signal.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: vpi_signal.cc,v 1.49 2002/09/11 16:06:57 steve Exp $"
+#ident "$Id: vpi_signal.cc,v 1.50 2002/11/25 23:33:45 steve Exp $"
 #endif
 
 /*
@@ -428,9 +428,10 @@ static void signal_get_value(vpiHandle ref, s_vpi_value*vp)
 	  }
 
 	  default:
-	    fprintf(stderr, "vvp internal error: signal_get_value: "
-		    "value type %u not implemented.\n", vp->format);
-
+	    fprintf(stderr, "vvp internal error: get_value: "
+		    "value type %u not implemented."
+		    " Signal is %s in scope %s\n",
+		    vp->format, rfp->name, rfp->scope->name);
 	    assert(0);
       }
 }
@@ -450,6 +451,36 @@ static void functor_poke(struct __vpiSignal*rfp, unsigned idx,
       fu->put_ostr(val, str, true);
 }
 
+static void signal_put_stringval(struct __vpiSignal*rfp, unsigned wid,
+				 const char*str)
+{
+      unsigned idx;
+      const char*cp;
+
+      cp = str + strlen(str);
+      idx = 0;
+
+      while ((idx < wid) && (cp > str)) {
+	    unsigned byte = *--cp;
+	    int bit;
+
+	    for (bit = 0 ;  bit < 8 ;  bit += 1) {
+		  if (byte & 1)
+			functor_poke(rfp, idx, 1, St1);
+		  else
+			functor_poke(rfp, idx, 0, St0);
+
+		  byte >>= 1;
+		  idx += 1;
+	    }
+      }
+
+      while (idx < wid) {
+	    functor_poke(rfp, 0, 0, St0);
+	    idx += 1;
+      }
+}
+
 static vpiHandle signal_put_value(vpiHandle ref, s_vpi_value*vp,
 				  p_vpi_time when, int flags)
 {
@@ -641,7 +672,15 @@ static vpiHandle signal_put_value(vpiHandle ref, s_vpi_value*vp,
 		break;
 	  }
 
+	  case vpiStringVal:
+	    signal_put_stringval(rfp, wid, vp->value.str);
+	    break;
+
 	  default:
+	    fprintf(stderr, "vvp internal error: put_value: "
+		    "value type %u not implemented."
+		    " Signal is %s in scope %s\n",
+		    vp->format, rfp->name, rfp->scope->name);
 	    assert(0);
 
       }
@@ -722,6 +761,9 @@ vpiHandle vpip_make_net(const char*name, int msb, int lsb,
 
 /*
  * $Log: vpi_signal.cc,v $
+ * Revision 1.50  2002/11/25 23:33:45  steve
+ *  Support put of vpiStringVal to signals.
+ *
  * Revision 1.49  2002/09/11 16:06:57  steve
  *  Fix wrecked rbuf in vpi_get_str of signals and memories.
  *

vvp/vthread.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: vthread.cc,v 1.93 2002/11/08 04:59:58 steve Exp $"
+#ident "$Id: vthread.cc,v 1.95 2002/11/22 00:01:50 steve Exp $"
 #endif
 
 # include  "vthread.h"
@@ -2191,17 +2191,19 @@ bool of_SET_VEC(vthread_t thr, vvp_code_t cp)
  * The single bit goes into the indexed functor. Abort the instruction
  * if the index is <0.
  */
-bool of_SET_X(vthread_t thr, vvp_code_t cp)
+bool of_SET_X0(vthread_t thr, vvp_code_t cp)
 {
       unsigned char bit_val = thr_get_bit(thr, cp->bit_idx[0]);
-      long idx = thr->index[cp->bit_idx[1]&3];
+      long idx = thr->index[0];
 
 	/* If idx < 0, then the index value is probably generated from
 	   an undefined value. At any rate, this is defined to have no
 	   effect so quit now. */
-      if (idx < 0) {
+      if (idx < 0)
+	    return true;
+
+      if (idx > cp->bit_idx[1])
 	    return true;
-      }
 
 	/* Form the functor pointer from the base pointer and the
 	   index from the index register. */
@@ -2219,6 +2221,8 @@ bool of_SHIFTL_I0(vthread_t thr, vvp_code_t cp)
       unsigned wid = cp->number;
       unsigned long shift = thr->index[0];
 
+      assert(base >= 4);
+
       if (shift >= wid) {
 	    for (unsigned idx = 0 ;  idx < wid ;  idx += 1)
 		  thr_put_bit(thr, base+idx, 0);
@@ -2492,6 +2496,12 @@ bool of_CALL_UFUNC(vthread_t thr, vvp_code_t cp)
 
 /*
  * $Log: vthread.cc,v $
+ * Revision 1.95  2002/11/22 00:01:50  steve
+ *  Careful of left operands to shift that are constant.
+ *
+ * Revision 1.94  2002/11/21 22:43:14  steve
+ *  %set/x0 instruction to support bounds checking.
+ *
  * Revision 1.93  2002/11/08 04:59:58  steve
  *  Add the %assign/v0 instruction.
  *