mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-24 23:06:56 +02:00
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Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 github-actions[bot]
|
9d8472d60b |
@@ -0,0 +1,4 @@
|
||||
# Sphinx build info version 1
|
||||
# This file records the configuration used when building these files. When it is not found, a full rebuild will be done.
|
||||
config: 6b92c0fcad0ee5df433166b877bb31df
|
||||
tags: 645f666f9bcd5a90fca523b33c5a78b7
|
||||
@@ -1,2 +0,0 @@
|
||||
# gperf in MSYS chokes on DOS line endings
|
||||
*.gperf text eol=lf
|
||||
-116
@@ -1,116 +0,0 @@
|
||||
# Lines that start with '#' are comments.
|
||||
#
|
||||
# This file is for the development branch of Icarus Verilog.
|
||||
#
|
||||
# The following files will be ignored by git.
|
||||
|
||||
# Normal editor rules
|
||||
*.swp
|
||||
*~
|
||||
|
||||
# Top level generic files
|
||||
tags
|
||||
TAGS
|
||||
cscope.*
|
||||
*.patch
|
||||
*.orig
|
||||
|
||||
# Object files and libraries
|
||||
*.[oa]
|
||||
|
||||
gmon*.out
|
||||
gmon*.txt
|
||||
|
||||
# From autoconf
|
||||
configure
|
||||
config.log
|
||||
config.status
|
||||
Makefile
|
||||
|
||||
/_pli_types.h
|
||||
config.h
|
||||
/tgt-pcb/pcb_config.h
|
||||
/tgt-pcb/fp.cc
|
||||
/tgt-pcb/fp.h
|
||||
/tgt-pcb/fp.output
|
||||
/tgt-pcb/fp_lex.cc
|
||||
/tgt-vvp/vvp_config.h
|
||||
/tgt-vhdl/vhdl_config.h
|
||||
/vpi/vpi_config.h
|
||||
stamp-*-h
|
||||
/version.h
|
||||
/version_tag.h
|
||||
|
||||
# Directories
|
||||
autom4te.cache
|
||||
dep
|
||||
|
||||
# Compiler back end and library files
|
||||
/tgt-vvp/*.conf
|
||||
*.tgt
|
||||
*.vpi
|
||||
/cadpli/cadpli.vpl
|
||||
|
||||
/tgt-blif/Makefile
|
||||
|
||||
# lex, yacc and gperf output
|
||||
/driver/cflexor.c
|
||||
/driver/cfparse.c
|
||||
/driver/cfparse.h
|
||||
/driver/cfparse.output
|
||||
|
||||
/ivlpp/lexor.c
|
||||
|
||||
/vhdlpp/lexor.cc
|
||||
/vhdlpp/lexor_keyword.cc
|
||||
/vhdlpp/parse.cc
|
||||
/vhdlpp/parse.h
|
||||
/vhdlpp/parse.output
|
||||
/vhdlpp/vhdlpp_config.h
|
||||
/vhdlpp/vhdlpp
|
||||
|
||||
/lexor.cc
|
||||
/lexor_keyword.cc
|
||||
/parse.cc
|
||||
/parse.h
|
||||
/parse.output
|
||||
/syn-rules.cc
|
||||
/syn-rules.output
|
||||
|
||||
/vpi/sdf_lexor.c
|
||||
/vpi/sdf_parse.c
|
||||
/vpi/sdf_parse.h
|
||||
/vpi/sdf_parse.output
|
||||
/vpi/sys_readmem_lex.c
|
||||
/vpi/table_mod_lexor.c
|
||||
/vpi/table_mod_parse.c
|
||||
/vpi/table_mod_parse.h
|
||||
/vpi/table_mod_parse.output
|
||||
|
||||
/vvp/dump.*
|
||||
/vvp/lexor.cc
|
||||
/vvp/parse.cc
|
||||
/vvp/parse.h
|
||||
/vvp/parse.output
|
||||
|
||||
# Program created files
|
||||
/vvp/tables.cc
|
||||
|
||||
/iverilog-vpi.man
|
||||
/driver-vpi/res.rc
|
||||
/driver/iverilog.man
|
||||
/vvp/vvp.man
|
||||
|
||||
# The executables.
|
||||
*.exe
|
||||
/driver/iverilog
|
||||
/iverilog-vpi
|
||||
/ivl
|
||||
/ivlpp/ivlpp
|
||||
/vvp/vvp
|
||||
|
||||
/ivl.exp
|
||||
/vvp/vvp.exp
|
||||
|
||||
# Check output
|
||||
/check.vvp
|
||||
-71
@@ -1,71 +0,0 @@
|
||||
language: cpp
|
||||
sudo: required
|
||||
dist: xenial
|
||||
|
||||
addons:
|
||||
apt:
|
||||
packages:
|
||||
- gperf
|
||||
|
||||
sudo: false
|
||||
|
||||
notifications:
|
||||
email: false
|
||||
|
||||
jobs:
|
||||
include:
|
||||
|
||||
- stage: Test
|
||||
os: linux
|
||||
dist: xenial
|
||||
before_install:
|
||||
- git clone https://github.com/steveicarus/ivtest.git
|
||||
- export PATH=$HOME/bin:$PATH
|
||||
script:
|
||||
- autoconf
|
||||
- ./configure --prefix=$HOME
|
||||
- make install
|
||||
- make check
|
||||
- cd ivtest
|
||||
- perl vvp_reg.pl
|
||||
- diff regression_report-devel.txt regression_report.txt
|
||||
- perl vpi_reg.pl
|
||||
|
||||
- stage: Test
|
||||
os: linux
|
||||
dist: bionic
|
||||
before_install:
|
||||
- git clone https://github.com/steveicarus/ivtest.git
|
||||
- export PATH=$HOME/bin:$PATH
|
||||
script:
|
||||
- autoconf
|
||||
- ./configure --prefix=$HOME
|
||||
- make install
|
||||
- make check
|
||||
- cd ivtest
|
||||
- perl vvp_reg.pl
|
||||
- diff regression_report-devel.txt regression_report.txt
|
||||
- perl vpi_reg.pl
|
||||
|
||||
- stage: Test
|
||||
os: windows
|
||||
before_install:
|
||||
- git clone https://github.com/steveicarus/ivtest.git
|
||||
- choco uninstall -y mingw
|
||||
- choco upgrade --no-progress -y msys2
|
||||
- export msys2='cmd //C RefreshEnv.cmd '
|
||||
- export msys2+='& set MSYS=winsymlinks:nativestrict '
|
||||
- export msys2+='& C:\\tools\\msys64\\msys2_shell.cmd -defterm -no-start'
|
||||
- export mingw64="$msys2 -mingw64 -full-path -here -c "\"\$@"\" --"
|
||||
- export msys2+=" -msys2 -c "\"\$@"\" --"
|
||||
- $msys2 pacman --sync --noconfirm --needed base-devel mingw-w64-x86_64-toolchain
|
||||
script:
|
||||
- $mingw64 ./autoconf.sh
|
||||
- $mingw64 ./configure
|
||||
- $mingw64 make install
|
||||
- $mingw64 make check
|
||||
- cd ivtest
|
||||
- $mingw64 perl update_msys2_report.pl
|
||||
- $mingw64 perl vvp_reg.pl
|
||||
- diff --strip-trailing-cr regression_report-msys2.txt regression_report.txt
|
||||
- $mingw64 perl vpi_reg.pl
|
||||
@@ -1,37 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2008 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "AStatement.h"
|
||||
|
||||
AContrib::AContrib(PExpr*lv, PExpr*rv)
|
||||
: lval_(lv), rval_(rv)
|
||||
{
|
||||
}
|
||||
|
||||
AContrib::~AContrib()
|
||||
{
|
||||
delete lval_;
|
||||
delete rval_;
|
||||
}
|
||||
|
||||
AProcess::~AProcess()
|
||||
{
|
||||
}
|
||||
@@ -1,85 +0,0 @@
|
||||
#ifndef IVL_AStatement_H
|
||||
#define IVL_AStatement_H
|
||||
/*
|
||||
* Copyright (c) 2008-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include <map>
|
||||
# include "ivl_target.h"
|
||||
# include "StringHeap.h"
|
||||
# include "LineInfo.h"
|
||||
# include "Statement.h"
|
||||
# include "PExpr.h"
|
||||
|
||||
class PExpr;
|
||||
class NetAnalog;
|
||||
class NetScope;
|
||||
class Design;
|
||||
|
||||
/*
|
||||
* A contribution statement is like an assignment: there is an l-value
|
||||
* expression and an r-value expression. The l-value is a branch probe
|
||||
* expression.
|
||||
*/
|
||||
class AContrib : public Statement {
|
||||
|
||||
public:
|
||||
AContrib(PExpr*lval, PExpr*rval);
|
||||
~AContrib();
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
PExpr*lval_;
|
||||
PExpr*rval_;
|
||||
};
|
||||
|
||||
/*
|
||||
* An analog process is not a statement, but contains an analog
|
||||
* statement. The process is where we attach process characteristics
|
||||
* such as initial vs. always, attributes....
|
||||
*/
|
||||
class AProcess : public LineInfo {
|
||||
|
||||
public:
|
||||
AProcess(ivl_process_type_t t, Statement*st)
|
||||
: type_(t), statement_(st) { }
|
||||
|
||||
~AProcess();
|
||||
|
||||
bool elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
ivl_process_type_t type() const { return type_; }
|
||||
Statement*statement() { return statement_; }
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
// Dump the analog process
|
||||
void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
ivl_process_type_t type_;
|
||||
Statement*statement_;
|
||||
|
||||
private: // not implemented
|
||||
AProcess(const AProcess&);
|
||||
AProcess& operator= (const AProcess&);
|
||||
};
|
||||
|
||||
#endif /* IVL_AStatement_H */
|
||||
@@ -1,101 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2000-2010 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "Attrib.h"
|
||||
# include <cassert>
|
||||
|
||||
Attrib::Attrib()
|
||||
{
|
||||
nlist_ = 0;
|
||||
list_ = 0;
|
||||
}
|
||||
|
||||
Attrib::~Attrib()
|
||||
{
|
||||
delete[] list_;
|
||||
}
|
||||
|
||||
|
||||
const verinum& Attrib::attribute(perm_string key) const
|
||||
{
|
||||
for (unsigned idx = 0 ; idx < nlist_ ; idx += 1) {
|
||||
|
||||
if (key == list_[idx].key)
|
||||
return list_[idx].val;
|
||||
}
|
||||
|
||||
static const verinum null;
|
||||
return null;
|
||||
}
|
||||
|
||||
void Attrib::attribute(perm_string key, const verinum&value)
|
||||
{
|
||||
unsigned idx;
|
||||
|
||||
for (idx = 0 ; idx < nlist_ ; idx += 1) {
|
||||
if (key == list_[idx].key) {
|
||||
list_[idx].val = value;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
struct cell_*tmp = new struct cell_[nlist_+1];
|
||||
for (idx = 0 ; idx < nlist_ ; idx += 1)
|
||||
tmp[idx] = list_[idx];
|
||||
|
||||
tmp[nlist_].key = key;
|
||||
tmp[nlist_].val = value;
|
||||
|
||||
nlist_ += 1;
|
||||
delete[]list_;
|
||||
list_ = tmp;
|
||||
}
|
||||
|
||||
bool Attrib::has_compat_attributes(const Attrib&that) const
|
||||
{
|
||||
unsigned idx;
|
||||
|
||||
for (idx = 0 ; idx < that.nlist_ ; idx += 1) {
|
||||
|
||||
verinum tmp = attribute(that.list_[idx].key);
|
||||
if (tmp != that.list_[idx].val)
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned Attrib::attr_cnt() const
|
||||
{
|
||||
return nlist_;
|
||||
}
|
||||
|
||||
perm_string Attrib::attr_key(unsigned idx) const
|
||||
{
|
||||
assert(idx < nlist_);
|
||||
return list_[idx].key;
|
||||
}
|
||||
|
||||
const verinum& Attrib::attr_value(unsigned idx) const
|
||||
{
|
||||
assert(idx < nlist_);
|
||||
return list_[idx].val;
|
||||
}
|
||||
@@ -1,60 +0,0 @@
|
||||
#ifndef IVL_Attrib_H
|
||||
#define IVL_Attrib_H
|
||||
/*
|
||||
* Copyright (c) 2000-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "StringHeap.h"
|
||||
# include "verinum.h"
|
||||
|
||||
/*
|
||||
* This class keeps a map of key/value pairs. The map can be set from
|
||||
* an STL map, or by setting individual mappings.
|
||||
*/
|
||||
class Attrib {
|
||||
|
||||
public:
|
||||
Attrib();
|
||||
virtual ~Attrib();
|
||||
|
||||
const verinum&attribute(perm_string key) const;
|
||||
void attribute(perm_string key, const verinum&value);
|
||||
bool has_compat_attributes(const Attrib&that) const;
|
||||
|
||||
|
||||
/* Provide a means of iterating over the entries in the map. */
|
||||
unsigned attr_cnt() const;
|
||||
perm_string attr_key(unsigned idx) const;
|
||||
const verinum& attr_value(unsigned idx) const;
|
||||
|
||||
|
||||
private:
|
||||
struct cell_ {
|
||||
perm_string key;
|
||||
verinum val;
|
||||
};
|
||||
|
||||
unsigned nlist_;
|
||||
struct cell_*list_;
|
||||
|
||||
private: // not implemented
|
||||
Attrib(const Attrib&);
|
||||
Attrib& operator= (const Attrib&);
|
||||
};
|
||||
|
||||
#endif /* IVL_Attrib_H */
|
||||
@@ -1,174 +0,0 @@
|
||||
|
||||
HOW TO REPORT BUGS
|
||||
|
||||
Before I can fix an error, I need to understand what the problem
|
||||
is. Try to explain what is wrong and why you think it is wrong. Please
|
||||
try to include sample code that demonstrates the problem. Include a
|
||||
description of what Icarus Verilog does that is wrong, and what you
|
||||
expect should happen. And include the command line flags passed to the
|
||||
compiler to make the error happen. (This is often overlooked, and
|
||||
sometimes important.)
|
||||
|
||||
* The Compiler Doesn't Compile
|
||||
|
||||
If Icarus Verilog doesn't compile, I need to know about the
|
||||
compilation tools you are using. Specifically, I need to know:
|
||||
|
||||
- Operating system and processor type,
|
||||
- Compiler w/ version,
|
||||
- Versions of any libraries being linked, and
|
||||
- anything else you think relevant.
|
||||
|
||||
Be aware that I do not have at my disposal a porting lab. I have the
|
||||
workstation on my desk, a Mac laptop, and the Linux/Intel box with a
|
||||
logic analyzer and 'scope hanging off it.
|
||||
|
||||
* The Compiler Crashes
|
||||
|
||||
No compiler should crash, no matter what kind of garbage is fed to
|
||||
it. If the compiler crashes, you definitely found a bug and I need to
|
||||
know about it.
|
||||
|
||||
Icarus Verilog internally checks its state while it works, and if it
|
||||
detects something wrong that it cannot recover from, it will abort
|
||||
intentionally. The "assertion failure" message that the program
|
||||
prints in the process of dying is very important. It tells me where in
|
||||
the source the bad thing happened. Include that message in the bug
|
||||
report.
|
||||
|
||||
If there are no assertion messages, I need to know that as well.
|
||||
|
||||
I also need a complete test program that demonstrates the crash.
|
||||
|
||||
* It Doesn't Like My Perfectly Valid Program(tm)
|
||||
|
||||
I need to know what you think is right that Icarus Verilog gets
|
||||
wrong. Does it reject your "Perfectly Valid Program(tm)" or does it
|
||||
compile it but give incorrect results? The latter is the most
|
||||
insidious as it doesn't scream out to be fixed unless someone is
|
||||
watching closely. However, if I get a sample program from you, and I
|
||||
can compile it, and I run it and nuclear junk doesn't fall from the
|
||||
sky, I'm moving on to the next problem.
|
||||
|
||||
So, if your program doesn't compile, tell me so, tell me where the
|
||||
error occurs, and include a complete Perfectly Valid Test Program(tm).
|
||||
You tell me that it fails to compile for you, and I find that it
|
||||
compiles for me, then hooray I fixed it. It can happen, you
|
||||
know. What's on my disk is more recent than the latest snapshot.
|
||||
|
||||
If your program does compile, but generates incorrect output, I need
|
||||
to know what it says and what you think it should say. From this I can
|
||||
take your sample program and work on Icarus Verilog until it gets the
|
||||
proper results. For this to work, of course, I first need to know what
|
||||
is wrong with the output. Spell it out, because I've been known to
|
||||
miss the obvious. Compiler writers often get buried in the details of
|
||||
the wrong problem.
|
||||
|
||||
* It Generates Incorrect Target Code
|
||||
|
||||
As Icarus Verilog adds target code generators, there will be cases
|
||||
where errors in the output netlist format occur. This is a tough nut
|
||||
because I might not have all the tools to test the target format you
|
||||
are reporting problems with. However, if you clearly explain what is
|
||||
right and wrong about the generated output, I will probably be able
|
||||
to fix the problem. It may take a few iterations.
|
||||
|
||||
In this case, if possible include not only the sample Verilog program,
|
||||
but the generated netlist file(s) and a clear indication of what went
|
||||
wrong or what is expected. If it is not clear to me, I will ask for
|
||||
clarification.
|
||||
|
||||
* The Output is Correct, But Less Than Ideal
|
||||
|
||||
If the output is strictly correct, but just not good enough for
|
||||
practical use, I would like to know. These sorts of problems are
|
||||
likely to be more subjective than a core dump, but are worthy of
|
||||
consideration. However, realize that outright errors will get more
|
||||
attention than missed optimizations.
|
||||
|
||||
THE MAKING OF A GOOD TEST PROGRAM
|
||||
|
||||
If at all possible, please submit a complete source file that
|
||||
demonstrates the problem. If the error occurs after elaboration,
|
||||
please include a top level module in the program that is suitable for
|
||||
the target format. If I have to write the module myself, I might not
|
||||
write it in a way that tickles the bug. So please, send all the
|
||||
Verilog source that I need to invoke the error.
|
||||
|
||||
Also, include the command line you use to invoke the compiler. For
|
||||
example:
|
||||
|
||||
iverilog -o foo.out -tvvp foo.v
|
||||
iverilog foo.vl -s starthere
|
||||
|
||||
If the error occurs with the null target (``-tnull'') then a top level
|
||||
module may not be needed as long as the ``-s <name>'' switch is
|
||||
given.
|
||||
|
||||
So when you send a test case, ask yourself "Can poor overworked Steve
|
||||
invoke the error without any Verilog other than what is included?" And
|
||||
while we are at it, please place a copyright notice in your test
|
||||
program and include a GPL license statement if you can. Your test
|
||||
program may find its way into the test suite, and the notices will
|
||||
make it all nice and legal. Please look at the existing tests in the
|
||||
test suite <http://sourceforge.net/ivtest> for examples of good test
|
||||
programs.
|
||||
|
||||
RESEARCHING EXISTING/PAST BUGS, AND FILING REPORTS
|
||||
|
||||
The URL <https://sourceforge.net/p/iverilog/bugs/> is the main
|
||||
bug tracking system, although some users have reported bugs at
|
||||
<https://github.com/steveicarus/iverilog/issues/>. Once you believe
|
||||
you have found a bug, you may browse the bugs database for existing
|
||||
bugs that may be related to yours. You might find that your bug has
|
||||
already been fixed in a later release or snapshot. If that's the case,
|
||||
then you are set. Also, consider if you are reporting a bug or really
|
||||
asking for a new feature, and use the appropriate tracker.
|
||||
|
||||
system (although you will also find bug rep
|
||||
|
||||
|
||||
The bug database supports basic keyword searches, and you can
|
||||
optionally limit your search to active bugs, or fixed bugs. You may
|
||||
also browse the bug database, just to get an idea what is still
|
||||
broken. You may for example find a related bug that explains your
|
||||
symptom.
|
||||
|
||||
The root page of the bug report database describes how to submit your
|
||||
completed bug report.
|
||||
|
||||
HOW TO SEND PATCHES
|
||||
|
||||
Bug reports with patches are very welcome, especially if they are
|
||||
formatted such that I can inspect them, decide that they are obviously
|
||||
correct, and apply them without worry.
|
||||
|
||||
I prefer patches generated by the git source code tracking system. If
|
||||
you are editing the source, you really should be using the latest
|
||||
version from git. Please see the developer documentation for more
|
||||
detailed instructions -- <http://iverilog.wikia.com/wiki/>.
|
||||
|
||||
When you make a patch, submit it to the "Patches" tracker at
|
||||
<https://sourceforge.net/p/iverilog/patches/>. Patches added to
|
||||
the "Patches" tracker enter the developer workflow, are checked,
|
||||
applied to the appropriate git branch, and are pushed. Then the
|
||||
tracker item is closed.
|
||||
|
||||
If you send patches, *please* tell me what this patch is supposed to
|
||||
accomplish, which branch you intended to be patched, and if
|
||||
appropriate include a test program that demonstrates the efficacy of
|
||||
the patch. (If I have no idea what the patch is for, I will ask for
|
||||
clarification before applying it.)
|
||||
|
||||
COPYRIGHT ISSUES
|
||||
|
||||
Icarus Verilog is Copyright (c) 1998-2018 Stephen Williams except
|
||||
where otherwise noted. Minor patches are covered as derivative works
|
||||
(or editorial comment or whatever the appropriate legal term is) and
|
||||
folded into the rest of ivl. However, if a submission can reasonably
|
||||
be considered independently copyrightable, it's yours and I encourage
|
||||
you to claim it with appropriate copyright notices. This submission
|
||||
then falls under the "otherwise noted" category.
|
||||
|
||||
I must insist that any copyright material submitted for inclusion
|
||||
include the GPL license notice as shown in the rest of the source.
|
||||
@@ -1,339 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
|
||||
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The licenses for most software are designed to take away your
|
||||
freedom to share and change it. By contrast, the GNU General Public
|
||||
License is intended to guarantee your freedom to share and change free
|
||||
software--to make sure the software is free for all its users. This
|
||||
General Public License applies to most of the Free Software
|
||||
Foundation's software and to any other program whose authors commit to
|
||||
using it. (Some other Free Software Foundation software is covered by
|
||||
the GNU Lesser General Public License instead.) You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
this service if you wish), that you receive source code or can get it
|
||||
if you want it, that you can change the software or use pieces of it
|
||||
in new free programs; and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to make restrictions that forbid
|
||||
anyone to deny you these rights or to ask you to surrender the rights.
|
||||
These restrictions translate to certain responsibilities for you if you
|
||||
distribute copies of the software, or if you modify it.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must give the recipients all the rights that
|
||||
you have. You must make sure that they, too, receive or can get the
|
||||
source code. And you must show them these terms so they know their
|
||||
rights.
|
||||
|
||||
We protect your rights with two steps: (1) copyright the software, and
|
||||
(2) offer you this license which gives you legal permission to copy,
|
||||
distribute and/or modify the software.
|
||||
|
||||
Also, for each author's protection and ours, we want to make certain
|
||||
that everyone understands that there is no warranty for this free
|
||||
software. If the software is modified by someone else and passed on, we
|
||||
want its recipients to know that what they have is not the original, so
|
||||
that any problems introduced by others will not reflect on the original
|
||||
authors' reputations.
|
||||
|
||||
Finally, any free program is threatened constantly by software
|
||||
patents. We wish to avoid the danger that redistributors of a free
|
||||
program will individually obtain patent licenses, in effect making the
|
||||
program proprietary. To prevent this, we have made it clear that any
|
||||
patent must be licensed for everyone's free use or not licensed at all.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
|
||||
|
||||
0. This License applies to any program or other work which contains
|
||||
a notice placed by the copyright holder saying it may be distributed
|
||||
under the terms of this General Public License. The "Program", below,
|
||||
refers to any such program or work, and a "work based on the Program"
|
||||
means either the Program or any derivative work under copyright law:
|
||||
that is to say, a work containing the Program or a portion of it,
|
||||
either verbatim or with modifications and/or translated into another
|
||||
language. (Hereinafter, translation is included without limitation in
|
||||
the term "modification".) Each licensee is addressed as "you".
|
||||
|
||||
Activities other than copying, distribution and modification are not
|
||||
covered by this License; they are outside its scope. The act of
|
||||
running the Program is not restricted, and the output from the Program
|
||||
is covered only if its contents constitute a work based on the
|
||||
Program (independent of having been made by running the Program).
|
||||
Whether that is true depends on what the Program does.
|
||||
|
||||
1. You may copy and distribute verbatim copies of the Program's
|
||||
source code as you receive it, in any medium, provided that you
|
||||
conspicuously and appropriately publish on each copy an appropriate
|
||||
copyright notice and disclaimer of warranty; keep intact all the
|
||||
notices that refer to this License and to the absence of any warranty;
|
||||
and give any other recipients of the Program a copy of this License
|
||||
along with the Program.
|
||||
|
||||
You may charge a fee for the physical act of transferring a copy, and
|
||||
you may at your option offer warranty protection in exchange for a fee.
|
||||
|
||||
2. You may modify your copy or copies of the Program or any portion
|
||||
of it, thus forming a work based on the Program, and copy and
|
||||
distribute such modifications or work under the terms of Section 1
|
||||
above, provided that you also meet all of these conditions:
|
||||
|
||||
a) You must cause the modified files to carry prominent notices
|
||||
stating that you changed the files and the date of any change.
|
||||
|
||||
b) You must cause any work that you distribute or publish, that in
|
||||
whole or in part contains or is derived from the Program or any
|
||||
part thereof, to be licensed as a whole at no charge to all third
|
||||
parties under the terms of this License.
|
||||
|
||||
c) If the modified program normally reads commands interactively
|
||||
when run, you must cause it, when started running for such
|
||||
interactive use in the most ordinary way, to print or display an
|
||||
announcement including an appropriate copyright notice and a
|
||||
notice that there is no warranty (or else, saying that you provide
|
||||
a warranty) and that users may redistribute the program under
|
||||
these conditions, and telling the user how to view a copy of this
|
||||
License. (Exception: if the Program itself is interactive but
|
||||
does not normally print such an announcement, your work based on
|
||||
the Program is not required to print an announcement.)
|
||||
|
||||
These requirements apply to the modified work as a whole. If
|
||||
identifiable sections of that work are not derived from the Program,
|
||||
and can be reasonably considered independent and separate works in
|
||||
themselves, then this License, and its terms, do not apply to those
|
||||
sections when you distribute them as separate works. But when you
|
||||
distribute the same sections as part of a whole which is a work based
|
||||
on the Program, the distribution of the whole must be on the terms of
|
||||
this License, whose permissions for other licensees extend to the
|
||||
entire whole, and thus to each and every part regardless of who wrote it.
|
||||
|
||||
Thus, it is not the intent of this section to claim rights or contest
|
||||
your rights to work written entirely by you; rather, the intent is to
|
||||
exercise the right to control the distribution of derivative or
|
||||
collective works based on the Program.
|
||||
|
||||
In addition, mere aggregation of another work not based on the Program
|
||||
with the Program (or with a work based on the Program) on a volume of
|
||||
a storage or distribution medium does not bring the other work under
|
||||
the scope of this License.
|
||||
|
||||
3. You may copy and distribute the Program (or a work based on it,
|
||||
under Section 2) in object code or executable form under the terms of
|
||||
Sections 1 and 2 above provided that you also do one of the following:
|
||||
|
||||
a) Accompany it with the complete corresponding machine-readable
|
||||
source code, which must be distributed under the terms of Sections
|
||||
1 and 2 above on a medium customarily used for software interchange; or,
|
||||
|
||||
b) Accompany it with a written offer, valid for at least three
|
||||
years, to give any third party, for a charge no more than your
|
||||
cost of physically performing source distribution, a complete
|
||||
machine-readable copy of the corresponding source code, to be
|
||||
distributed under the terms of Sections 1 and 2 above on a medium
|
||||
customarily used for software interchange; or,
|
||||
|
||||
c) Accompany it with the information you received as to the offer
|
||||
to distribute corresponding source code. (This alternative is
|
||||
allowed only for noncommercial distribution and only if you
|
||||
received the program in object code or executable form with such
|
||||
an offer, in accord with Subsection b above.)
|
||||
|
||||
The source code for a work means the preferred form of the work for
|
||||
making modifications to it. For an executable work, complete source
|
||||
code means all the source code for all modules it contains, plus any
|
||||
associated interface definition files, plus the scripts used to
|
||||
control compilation and installation of the executable. However, as a
|
||||
special exception, the source code distributed need not include
|
||||
anything that is normally distributed (in either source or binary
|
||||
form) with the major components (compiler, kernel, and so on) of the
|
||||
operating system on which the executable runs, unless that component
|
||||
itself accompanies the executable.
|
||||
|
||||
If distribution of executable or object code is made by offering
|
||||
access to copy from a designated place, then offering equivalent
|
||||
access to copy the source code from the same place counts as
|
||||
distribution of the source code, even though third parties are not
|
||||
compelled to copy the source along with the object code.
|
||||
|
||||
4. You may not copy, modify, sublicense, or distribute the Program
|
||||
except as expressly provided under this License. Any attempt
|
||||
otherwise to copy, modify, sublicense or distribute the Program is
|
||||
void, and will automatically terminate your rights under this License.
|
||||
However, parties who have received copies, or rights, from you under
|
||||
this License will not have their licenses terminated so long as such
|
||||
parties remain in full compliance.
|
||||
|
||||
5. You are not required to accept this License, since you have not
|
||||
signed it. However, nothing else grants you permission to modify or
|
||||
distribute the Program or its derivative works. These actions are
|
||||
prohibited by law if you do not accept this License. Therefore, by
|
||||
modifying or distributing the Program (or any work based on the
|
||||
Program), you indicate your acceptance of this License to do so, and
|
||||
all its terms and conditions for copying, distributing or modifying
|
||||
the Program or works based on it.
|
||||
|
||||
6. Each time you redistribute the Program (or any work based on the
|
||||
Program), the recipient automatically receives a license from the
|
||||
original licensor to copy, distribute or modify the Program subject to
|
||||
these terms and conditions. You may not impose any further
|
||||
restrictions on the recipients' exercise of the rights granted herein.
|
||||
You are not responsible for enforcing compliance by third parties to
|
||||
this License.
|
||||
|
||||
7. If, as a consequence of a court judgment or allegation of patent
|
||||
infringement or for any other reason (not limited to patent issues),
|
||||
conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot
|
||||
distribute so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you
|
||||
may not distribute the Program at all. For example, if a patent
|
||||
license would not permit royalty-free redistribution of the Program by
|
||||
all those who receive copies directly or indirectly through you, then
|
||||
the only way you could satisfy both it and this License would be to
|
||||
refrain entirely from distribution of the Program.
|
||||
|
||||
If any portion of this section is held invalid or unenforceable under
|
||||
any particular circumstance, the balance of the section is intended to
|
||||
apply and the section as a whole is intended to apply in other
|
||||
circumstances.
|
||||
|
||||
It is not the purpose of this section to induce you to infringe any
|
||||
patents or other property right claims or to contest validity of any
|
||||
such claims; this section has the sole purpose of protecting the
|
||||
integrity of the free software distribution system, which is
|
||||
implemented by public license practices. Many people have made
|
||||
generous contributions to the wide range of software distributed
|
||||
through that system in reliance on consistent application of that
|
||||
system; it is up to the author/donor to decide if he or she is willing
|
||||
to distribute software through any other system and a licensee cannot
|
||||
impose that choice.
|
||||
|
||||
This section is intended to make thoroughly clear what is believed to
|
||||
be a consequence of the rest of this License.
|
||||
|
||||
8. If the distribution and/or use of the Program is restricted in
|
||||
certain countries either by patents or by copyrighted interfaces, the
|
||||
original copyright holder who places the Program under this License
|
||||
may add an explicit geographical distribution limitation excluding
|
||||
those countries, so that distribution is permitted only in or among
|
||||
countries not thus excluded. In such case, this License incorporates
|
||||
the limitation as if written in the body of this License.
|
||||
|
||||
9. The Free Software Foundation may publish revised and/or new versions
|
||||
of the General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the Program
|
||||
specifies a version number of this License which applies to it and "any
|
||||
later version", you have the option of following the terms and conditions
|
||||
either of that version or of any later version published by the Free
|
||||
Software Foundation. If the Program does not specify a version number of
|
||||
this License, you may choose any version ever published by the Free Software
|
||||
Foundation.
|
||||
|
||||
10. If you wish to incorporate parts of the Program into other free
|
||||
programs whose distribution conditions are different, write to the author
|
||||
to ask for permission. For software which is copyrighted by the Free
|
||||
Software Foundation, write to the Free Software Foundation; we sometimes
|
||||
make exceptions for this. Our decision will be guided by the two goals
|
||||
of preserving the free status of all derivatives of our free software and
|
||||
of promoting the sharing and reuse of software generally.
|
||||
|
||||
NO WARRANTY
|
||||
|
||||
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
|
||||
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
|
||||
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
|
||||
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
|
||||
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
|
||||
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
|
||||
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
|
||||
REPAIR OR CORRECTION.
|
||||
|
||||
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
|
||||
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
|
||||
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
|
||||
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
|
||||
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
|
||||
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
|
||||
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGES.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
convey the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program is interactive, make it output a short notice like this
|
||||
when it starts in an interactive mode:
|
||||
|
||||
Gnomovision version 69, Copyright (C) year name of author
|
||||
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, the commands you use may
|
||||
be called something other than `show w' and `show c'; they could even be
|
||||
mouse-clicks or menu items--whatever suits your program.
|
||||
|
||||
You should also get your employer (if you work as a programmer) or your
|
||||
school, if any, to sign a "copyright disclaimer" for the program, if
|
||||
necessary. Here is a sample; alter the names:
|
||||
|
||||
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||
|
||||
<signature of Ty Coon>, 1 April 1989
|
||||
Ty Coon, President of Vice
|
||||
|
||||
This General Public License does not permit incorporating your program into
|
||||
proprietary programs. If your program is a subroutine library, you may
|
||||
consider it more useful to permit linking proprietary applications with the
|
||||
library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License.
|
||||
@@ -1,121 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
# include "HName.h"
|
||||
# include <iostream>
|
||||
# include <cstring>
|
||||
# include <cstdlib>
|
||||
|
||||
using namespace std;
|
||||
|
||||
hname_t::hname_t()
|
||||
{
|
||||
}
|
||||
|
||||
hname_t::hname_t(perm_string text)
|
||||
: name_(text)
|
||||
{
|
||||
}
|
||||
|
||||
hname_t::hname_t(perm_string text, int num)
|
||||
: name_(text), number_(1)
|
||||
{
|
||||
number_[0] = num;
|
||||
}
|
||||
|
||||
hname_t::hname_t(perm_string text, const vector<int>&nums)
|
||||
: name_(text), number_(nums)
|
||||
{
|
||||
}
|
||||
|
||||
hname_t::hname_t(const hname_t&that)
|
||||
: name_(that.name_), number_(that.number_)
|
||||
{
|
||||
}
|
||||
|
||||
hname_t& hname_t::operator = (const hname_t&that)
|
||||
{
|
||||
name_ = that.name_;
|
||||
number_ = that.number_;
|
||||
return *this;
|
||||
}
|
||||
|
||||
bool hname_t::operator < (const hname_t&r) const
|
||||
{
|
||||
int cmp = strcmp(name_, r.name_);
|
||||
if (cmp < 0) return true;
|
||||
if (cmp > 0) return false;
|
||||
|
||||
// The text parts are equal, so compare then number
|
||||
// parts. Finish as soon as we find one to be less or more
|
||||
// than the other.
|
||||
size_t idx = 0;
|
||||
while (number_.size() > idx || r.number_.size() > idx) {
|
||||
|
||||
// Ran out of l numbers, so less.
|
||||
if (number_.size() <= idx)
|
||||
return true;
|
||||
|
||||
// Ran out of r numbers, so greater.
|
||||
if (r.number_.size() <= idx)
|
||||
return false;
|
||||
|
||||
if (number_[idx] < r.number_[idx])
|
||||
return true;
|
||||
|
||||
if (number_[idx] > r.number_[idx])
|
||||
return false;
|
||||
|
||||
idx += 1;
|
||||
}
|
||||
|
||||
// Fall-through means that we are equal, including all the
|
||||
// number parts, so not less.
|
||||
return false;
|
||||
}
|
||||
|
||||
bool hname_t::operator == (const hname_t&r) const
|
||||
{
|
||||
if (name_ == r.name_) {
|
||||
if (number_.size() != r.number_.size())
|
||||
return false;
|
||||
|
||||
for (size_t idx = 0 ; idx < number_.size() ; idx += 1)
|
||||
if (number_[idx] != r.number_[idx]) return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
ostream& operator<< (ostream&out, const hname_t&that)
|
||||
{
|
||||
if (that.peek_name() == 0) {
|
||||
out << "";
|
||||
return out;
|
||||
}
|
||||
|
||||
out << that.peek_name();
|
||||
for (size_t idx = 0 ; idx < that.number_.size() ; idx += 1)
|
||||
out << "[" << that.number_[idx] << "]";
|
||||
|
||||
return out;
|
||||
}
|
||||
@@ -1,112 +0,0 @@
|
||||
#ifndef IVL_HName_H
|
||||
#define IVL_HName_H
|
||||
/*
|
||||
* Copyright (c) 2001-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include <iostream>
|
||||
# include <list>
|
||||
# include <vector>
|
||||
# include "StringHeap.h"
|
||||
|
||||
# include <cassert>
|
||||
|
||||
/*
|
||||
* This class represents a component of a Verilog hierarchical name. A
|
||||
* hierarchical component contains a name string (represented here
|
||||
* with a perm_string) and an optional signed number. This signed
|
||||
* number is used if the scope is part of an array, for example an
|
||||
* array of module instances or a loop generated scope.
|
||||
*/
|
||||
|
||||
class hname_t {
|
||||
|
||||
friend ostream& operator<< (ostream&out, const hname_t&that);
|
||||
|
||||
public:
|
||||
hname_t ();
|
||||
explicit hname_t (perm_string text);
|
||||
explicit hname_t (perm_string text, int num);
|
||||
explicit hname_t (perm_string text, const std::vector<int>&nums);
|
||||
hname_t (const hname_t&that);
|
||||
~hname_t();
|
||||
|
||||
hname_t& operator= (const hname_t&);
|
||||
|
||||
bool operator == (const hname_t&that) const;
|
||||
bool operator < (const hname_t&that) const;
|
||||
|
||||
// Return the string part of the hname_t.
|
||||
perm_string peek_name(void) const;
|
||||
|
||||
size_t has_numbers() const;
|
||||
int peek_number(size_t idx) const;
|
||||
const std::vector<int>&peek_numbers() const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
// If this vector has size, then the numbers all together make
|
||||
// up part of the hierarchical name.
|
||||
std::vector<int> number_;
|
||||
|
||||
private: // not implemented
|
||||
};
|
||||
|
||||
inline hname_t::~hname_t()
|
||||
{
|
||||
}
|
||||
|
||||
inline perm_string hname_t::peek_name(void) const
|
||||
{
|
||||
return name_;
|
||||
}
|
||||
|
||||
inline int hname_t::peek_number(size_t idx) const
|
||||
{
|
||||
assert(number_.size() > idx);
|
||||
return number_[idx];
|
||||
}
|
||||
|
||||
inline const std::vector<int>& hname_t::peek_numbers(void) const
|
||||
{
|
||||
return number_;
|
||||
}
|
||||
|
||||
inline size_t hname_t::has_numbers() const
|
||||
{
|
||||
return number_.size();
|
||||
}
|
||||
|
||||
extern ostream& operator<< (ostream&, const hname_t&);
|
||||
|
||||
inline bool operator != (const hname_t&l, const hname_t&r)
|
||||
{ return ! (l == r); }
|
||||
|
||||
inline ostream& operator<< (ostream&out, const list<hname_t>&ll)
|
||||
{
|
||||
list<hname_t>::const_iterator cur = ll.begin();
|
||||
out << *cur;
|
||||
++ cur;
|
||||
while (cur != ll.end()) {
|
||||
out << "." << *cur;
|
||||
++ cur;
|
||||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
#endif /* IVL_HName_H */
|
||||
@@ -1,181 +0,0 @@
|
||||
Basic Installation
|
||||
==================
|
||||
|
||||
These are generic installation instructions.
|
||||
|
||||
The `configure' shell script attempts to guess correct values for
|
||||
various system-dependent variables used during compilation. It uses
|
||||
those values to create a `Makefile' in each directory of the package.
|
||||
It may also create one or more `.h' files containing system-dependent
|
||||
definitions. Finally, it creates a shell script `config.status' that
|
||||
you can run in the future to recreate the current configuration, a file
|
||||
`config.cache' that saves the results of its tests to speed up
|
||||
reconfiguring, and a file `config.log' containing compiler output
|
||||
(useful mainly for debugging `configure').
|
||||
|
||||
If you need to do unusual things to compile the package, please try
|
||||
to figure out how `configure' could check whether to do them, and mail
|
||||
diffs or instructions to the address given in the `README' so they can
|
||||
be considered for the next release. If at some point `config.cache'
|
||||
contains results you don't want to keep, you may remove or edit it.
|
||||
|
||||
The file `configure.in' is used to create `configure' by a program
|
||||
called `autoconf'. You only need `configure.in' if you want to change
|
||||
it or regenerate `configure' using a newer version of `autoconf'.
|
||||
|
||||
The simplest way to compile this package is:
|
||||
|
||||
1. `cd' to the directory containing the package's source code and type
|
||||
`./configure' to configure the package for your system. If you're
|
||||
using `csh' on an old version of System V, you might need to type
|
||||
`sh ./configure' instead to prevent `csh' from trying to execute
|
||||
`configure' itself.
|
||||
|
||||
Running `configure' takes awhile. While running, it prints some
|
||||
messages telling which features it is checking for.
|
||||
|
||||
2. Type `make' to compile the package.
|
||||
|
||||
3. Optionally, type `make check' to run any self-tests that come with
|
||||
the package.
|
||||
|
||||
4. Type `make install' to install the programs and any data files and
|
||||
documentation.
|
||||
|
||||
5. You can remove the program binaries and object files from the
|
||||
source code directory by typing `make clean'. To also remove the
|
||||
files that `configure' created (so you can compile the package for
|
||||
a different kind of computer), type `make distclean'. There is
|
||||
also a `make maintainer-clean' target, but that is intended mainly
|
||||
for the package's developers. If you use it, you may have to get
|
||||
all sorts of other programs in order to regenerate files that came
|
||||
with the distribution.
|
||||
|
||||
Compilers and Options
|
||||
=====================
|
||||
|
||||
Some systems require unusual options for compilation or linking that
|
||||
the `configure' script does not know about. You can give `configure'
|
||||
initial values for variables by setting them in the environment. Using
|
||||
a Bourne-compatible shell, you can do that on the command line like
|
||||
this:
|
||||
CC=c89 CFLAGS=-O2 LIBS=-lposix ./configure
|
||||
|
||||
Or on systems that have the `env' program, you can do it like this:
|
||||
env CPPFLAGS=-I/usr/local/include LDFLAGS=-s ./configure
|
||||
|
||||
Compiling For Multiple Architectures
|
||||
====================================
|
||||
|
||||
You can compile the package for more than one kind of computer at the
|
||||
same time, by placing the object files for each architecture in their
|
||||
own directory. To do this, you must use a version of `make' that
|
||||
supports the `VPATH' variable, such as GNU `make'. `cd' to the
|
||||
directory where you want the object files and executables to go and run
|
||||
the `configure' script. `configure' automatically checks for the
|
||||
source code in the directory that `configure' is in and in `..'.
|
||||
|
||||
If you have to use a `make' that does not supports the `VPATH'
|
||||
variable, you have to compile the package for one architecture at a time
|
||||
in the source code directory. After you have installed the package for
|
||||
one architecture, use `make distclean' before reconfiguring for another
|
||||
architecture.
|
||||
|
||||
Installation Names
|
||||
==================
|
||||
|
||||
By default, `make install' will install the package's files in
|
||||
`/usr/local/bin', `/usr/local/man', etc. You can specify an
|
||||
installation prefix other than `/usr/local' by giving `configure' the
|
||||
option `--prefix=PATH'.
|
||||
|
||||
You can specify separate installation prefixes for
|
||||
architecture-specific files and architecture-independent files. If you
|
||||
give `configure' the option `--exec-prefix=PATH', the package will use
|
||||
PATH as the prefix for installing programs and libraries.
|
||||
Documentation and other data files will still use the regular prefix.
|
||||
|
||||
In addition, if you use an unusual directory layout you can give
|
||||
options like `--bindir=PATH' to specify different values for particular
|
||||
kinds of files. Run `configure --help' for a list of the directories
|
||||
you can set and what kinds of files go in them.
|
||||
|
||||
If the package supports it, you can cause programs to be installed
|
||||
with an extra prefix or suffix on their names by giving `configure' the
|
||||
option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
|
||||
|
||||
Optional Features
|
||||
=================
|
||||
|
||||
Some packages pay attention to `--enable-FEATURE' options to
|
||||
`configure', where FEATURE indicates an optional part of the package.
|
||||
They may also pay attention to `--with-PACKAGE' options, where PACKAGE
|
||||
is something like `gnu-as' or `x' (for the X Window System). The
|
||||
`README' should mention any `--enable-' and `--with-' options that the
|
||||
package recognizes.
|
||||
|
||||
For packages that use the X Window System, `configure' can usually
|
||||
find the X include and library files automatically, but if it doesn't,
|
||||
you can use the `configure' options `--x-includes=DIR' and
|
||||
`--x-libraries=DIR' to specify their locations.
|
||||
|
||||
Specifying the System Type
|
||||
==========================
|
||||
|
||||
There may be some features `configure' can not figure out
|
||||
automatically, but needs to determine by the type of host the package
|
||||
will run on. Usually `configure' can figure that out, but if it prints
|
||||
a message saying it can not guess the host type, give it the
|
||||
`--host=TYPE' option. TYPE can either be a short name for the system
|
||||
type, such as `sun4', or a canonical name with three fields:
|
||||
CPU-COMPANY-SYSTEM
|
||||
|
||||
See the file `config.sub' for the possible values of each field. If
|
||||
`config.sub' isn't included in this package, then this package doesn't
|
||||
need to know the host type.
|
||||
|
||||
If you are building compiler tools for cross-compiling, you can also
|
||||
use the `--target=TYPE' option to select the type of system they will
|
||||
produce code for and the `--build=TYPE' option to select the type of
|
||||
system on which you are compiling the package.
|
||||
|
||||
Sharing Defaults
|
||||
================
|
||||
|
||||
If you want to set default values for `configure' scripts to share,
|
||||
you can create a site shell script called `config.site' that gives
|
||||
default values for variables like `CC', `cache_file', and `prefix'.
|
||||
`configure' looks for `PREFIX/share/config.site' if it exists, then
|
||||
`PREFIX/etc/config.site' if it exists. Or, you can set the
|
||||
`CONFIG_SITE' environment variable to the location of the site script.
|
||||
A warning: not all `configure' scripts look for a site script.
|
||||
|
||||
Operation Controls
|
||||
==================
|
||||
|
||||
`configure' recognizes the following options to control how it
|
||||
operates.
|
||||
|
||||
`--cache-file=FILE'
|
||||
Use and save the results of the tests in FILE instead of
|
||||
`./config.cache'. Set FILE to `/dev/null' to disable caching, for
|
||||
debugging `configure'.
|
||||
|
||||
`--help'
|
||||
Print a summary of the options to `configure', and exit.
|
||||
|
||||
`--quiet'
|
||||
`--silent'
|
||||
`-q'
|
||||
Do not print messages saying which checks are being made.
|
||||
|
||||
`--srcdir=DIR'
|
||||
Look for the package's source code in directory DIR. Usually
|
||||
`configure' can determine that directory automatically.
|
||||
|
||||
`--version'
|
||||
Print the version of Autoconf used to generate the `configure'
|
||||
script, and exit.
|
||||
|
||||
`configure' also accepts some other, not widely useful, options.
|
||||
|
||||
-386
@@ -1,386 +0,0 @@
|
||||
#
|
||||
# This source code is free software; you can redistribute it
|
||||
# and/or modify it in source code form under the terms of the GNU
|
||||
# Library General Public License as published by the Free Software
|
||||
# Foundation; either version 2 of the License, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU Library General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU Library General Public
|
||||
# License along with this program; if not, write to the Free
|
||||
# Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
|
||||
# Boston, MA 02110-1301, USA.
|
||||
#
|
||||
SHELL = /bin/sh
|
||||
|
||||
# The interesting make targets are:
|
||||
#
|
||||
# make version
|
||||
# Force the version_tag.h file to be rebuilt. Otherwise, it will only
|
||||
# be built if it is missing.
|
||||
#
|
||||
# make all
|
||||
# make install
|
||||
#
|
||||
# The "suffix" is used as an installation suffix. It modifies certain
|
||||
# key install paths/files such that a build and install of Icarus Verilog
|
||||
# with the same $(prefix) but a different $(suffix) will not interfere.
|
||||
# The normal configuration leaves suffix empty
|
||||
suffix = @install_suffix@
|
||||
|
||||
prefix = @prefix@
|
||||
exec_prefix = @exec_prefix@
|
||||
srcdir = @srcdir@
|
||||
datarootdir = @datarootdir@
|
||||
|
||||
SUBDIRS = ivlpp vhdlpp vvp vpi libveriuser cadpli tgt-null tgt-stub tgt-vvp \
|
||||
tgt-vhdl tgt-vlog95 tgt-pcb tgt-blif tgt-sizer driver
|
||||
# Only run distclean for these directories.
|
||||
NOTUSED = tgt-fpga tgt-pal tgt-verilog
|
||||
|
||||
ifeq (@MINGW32@,yes)
|
||||
SUBDIRS += driver-vpi
|
||||
else
|
||||
NOTUSED += driver-vpi
|
||||
endif
|
||||
|
||||
# To get the version headers to build correctly we only want to look
|
||||
# for C++ files in the source directory. All other files will require
|
||||
# an explicit $(srcdir). The one exception to this is if we need to
|
||||
# rebuild the lexor_keyword.cc file. If we do, then we want to use the
|
||||
# local version instead of the one is $(srcdir).
|
||||
vpath lexor_keyword.cc .
|
||||
vpath %.cc $(srcdir)/libmisc
|
||||
vpath %.cc $(srcdir)
|
||||
|
||||
bindir = @bindir@
|
||||
libdir = @libdir@
|
||||
# This is actually the directory where we install our own header files.
|
||||
# It is a little different from the generic includedir.
|
||||
includedir = @includedir@/iverilog$(suffix)
|
||||
mandir = @mandir@
|
||||
|
||||
dllib=@DLLIB@
|
||||
|
||||
# For a cross compile these defines will need to be set accordingly.
|
||||
HOSTCC = @CC@
|
||||
HOSTCFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
|
||||
|
||||
BUILDCC = @CC_FOR_BUILD@
|
||||
BUILDEXT = @BUILD_EXEEXT@
|
||||
CXX = @CXX@
|
||||
DLLTOOL = @DLLTOOL@
|
||||
INSTALL = @INSTALL@
|
||||
INSTALL_SCRIPT = @INSTALL_SCRIPT@
|
||||
INSTALL_PROGRAM = @INSTALL_PROGRAM@
|
||||
INSTALL_DATA = @INSTALL_DATA@
|
||||
LEX = @LEX@
|
||||
YACC = @YACC@
|
||||
MAN = @MAN@
|
||||
PS2PDF = @PS2PDF@
|
||||
GIT = @GIT@
|
||||
|
||||
ifeq (@srcdir@,.)
|
||||
INCLUDE_PATH = -I. -Ilibmisc
|
||||
else
|
||||
INCLUDE_PATH = -I. -I$(srcdir) -I$(srcdir)/libmisc
|
||||
endif
|
||||
|
||||
CPPFLAGS = @DEFS@ $(INCLUDE_PATH) @CPPFLAGS@
|
||||
CFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CC@ @CFLAGS@
|
||||
CXXFLAGS = @WARNING_FLAGS@ @WARNING_FLAGS_CXX@ @CXXFLAGS@
|
||||
PICFLAGS = @PICFLAG@
|
||||
LDFLAGS = @rdynamic@ @LDFLAGS@
|
||||
CTARGETFLAGS = @CTARGETFLAGS@
|
||||
|
||||
# Source files in the libmisc directory
|
||||
M = LineInfo.o StringHeap.o
|
||||
|
||||
TT = t-dll.o t-dll-api.o t-dll-expr.o t-dll-proc.o t-dll-analog.o
|
||||
FF = cprop.o exposenodes.o nodangle.o synth.o synth2.o syn-rules.o
|
||||
|
||||
O = main.o async.o design_dump.o discipline.o dup_expr.o elaborate.o \
|
||||
elab_expr.o elaborate_analog.o elab_lval.o elab_net.o \
|
||||
elab_scope.o elab_sig.o elab_sig_analog.o elab_type.o \
|
||||
emit.o eval.o eval_attrib.o \
|
||||
eval_tree.o expr_synth.o functor.o lexor.o lexor_keyword.o link_const.o \
|
||||
load_module.o netlist.o netmisc.o nettypes.o net_analog.o net_assign.o \
|
||||
net_design.o netclass.o netdarray.o \
|
||||
netenum.o netparray.o netqueue.o netscalar.o netstruct.o netvector.o \
|
||||
net_event.o net_expr.o net_func.o \
|
||||
net_func_eval.o net_link.o net_modulo.o \
|
||||
net_nex_input.o net_nex_output.o net_proc.o net_scope.o net_tran.o \
|
||||
net_udp.o pad_to_width.o parse.o parse_misc.o pform.o pform_analog.o \
|
||||
pform_disciplines.o pform_dump.o pform_package.o pform_pclass.o \
|
||||
pform_class_type.o pform_string_type.o pform_struct_type.o pform_types.o \
|
||||
symbol_search.o sync.o sys_funcs.o verinum.o verireal.o vpi_modules.o target.o \
|
||||
Attrib.o HName.o Module.o PClass.o PDelays.o PEvent.o PExpr.o PFunction.o \
|
||||
PGate.o PGenerate.o PModport.o PNamedItem.o PPackage.o PScope.o PSpec.o \
|
||||
PTask.o PUdp.o PWire.o Statement.o AStatement.o $M $(FF) $(TT)
|
||||
|
||||
all: dep config.h _pli_types.h version_tag.h ivl@EXEEXT@ version.exe iverilog-vpi.man
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
|
||||
# In the windows world, the installer will need a dosify program to
|
||||
# dosify text files.
|
||||
ifeq (@MINGW32@,yes)
|
||||
all: dosify$(BUILDEXT)
|
||||
dosify$(BUILDEXT): $(srcdir)/dosify.c
|
||||
$(BUILDCC) $(CFLAGS) -o dosify$(BUILDEXT) $(srcdir)/dosify.c
|
||||
endif
|
||||
|
||||
# This rule rules the compiler in the trivial hello.vl program to make
|
||||
# sure the basics were compiled properly.
|
||||
check: all
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
test -r check.conf || cp $(srcdir)/check.conf .
|
||||
driver/iverilog -B. -BMvpi -BPivlpp -tcheck -ocheck.vvp $(srcdir)/examples/hello.vl
|
||||
ifeq (@WIN32@,yes)
|
||||
ifeq (@install_suffix@,)
|
||||
vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
|
||||
else
|
||||
# On Windows if we have a suffix we must run the vvp part of
|
||||
# the test with a suffix since it was built/linked that way.
|
||||
ln vvp/vvp.exe vvp/vvp$(suffix).exe
|
||||
vvp/vvp$(suffix) -M- -M./vpi ./check.vvp | grep 'Hello, World'
|
||||
rm vvp/vvp$(suffix).exe
|
||||
endif
|
||||
else
|
||||
vvp/vvp -M- -M./vpi ./check.vvp | grep 'Hello, World'
|
||||
endif
|
||||
|
||||
clean:
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
rm -f *.o parse.cc parse.h lexor.cc
|
||||
rm -f ivl.exp iverilog-vpi.man iverilog-vpi.pdf iverilog-vpi.ps
|
||||
rm -f parse.output syn-rules.output dosify$(BUILDEXT) ivl@EXEEXT@ check.vvp
|
||||
rm -f lexor_keyword.cc libivl.a libvpi.a iverilog-vpi syn-rules.cc
|
||||
rm -rf dep
|
||||
rm -f version.exe
|
||||
|
||||
distclean: clean
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
$(foreach dir,$(NOTUSED),$(MAKE) -C $(dir) $@ && ) true
|
||||
rm -f Makefile config.status config.log config.cache
|
||||
rm -f stamp-config-h config.h
|
||||
rm -f stamp-_pli_types-h _pli_types.h
|
||||
ifneq (@srcdir@,.)
|
||||
rm -f version_tag.h check.conf
|
||||
rmdir $(SUBDIRS) $(NOTUSED)
|
||||
endif
|
||||
rm -rf autom4te.cache
|
||||
|
||||
cppcheck: $(O:.o=.cc) $(srcdir)/dosify.c $(srcdir)/version.c
|
||||
cppcheck --enable=all --std=posix --std=c99 --std=c++03 -f \
|
||||
--suppressions-list=$(srcdir)/cppcheck.sup \
|
||||
-UYYPARSE_PARAM -UYYPRINT -Ushort -Usize_t -Uyyoverflow \
|
||||
-UYYTYPE_INT8 -UYYTYPE_INT16 -UYYTYPE_UINT8 -UYYTYPE_UINT16 \
|
||||
--relative-paths=$(srcdir) $(INCLUDE_PATH) $^
|
||||
|
||||
cppcheck-all:
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) cppcheck && ) true
|
||||
$(foreach dir,$(NOTUSED),$(MAKE) -C $(dir) cppcheck && ) true
|
||||
$(MAKE) cppcheck
|
||||
|
||||
Makefile: $(srcdir)/Makefile.in config.status
|
||||
./config.status --file=$@
|
||||
|
||||
dep:
|
||||
mkdir dep
|
||||
|
||||
stamp-config-h: $(srcdir)/config.h.in config.status
|
||||
@rm -f $@
|
||||
./config.status config.h
|
||||
config.h: stamp-config-h
|
||||
|
||||
stamp-_pli_types-h: $(srcdir)/_pli_types.h.in config.status
|
||||
@rm -f $@
|
||||
./config.status _pli_types.h
|
||||
_pli_types.h: stamp-_pli_types-h
|
||||
|
||||
$(srcdir)/configure: $(srcdir)/configure.in $(srcdir)/aclocal.m4
|
||||
cd $(srcdir) && autoconf
|
||||
|
||||
config.status: $(srcdir)/configure
|
||||
./config.status --recheck
|
||||
./config.status
|
||||
|
||||
ifeq (@WIN32@,yes)
|
||||
# Under Windows (mingw) I need to make the ivl.exe in two steps.
|
||||
# The first step makes an ivl.exe that dlltool can use to make an
|
||||
# export and import library, and the last link makes a, ivl.exe
|
||||
# that really exports the things that the import library imports.
|
||||
ivl@EXEEXT@: $O $(srcdir)/ivl.def
|
||||
$(CXX) -o ivl@EXEEXT@ $O $(dllib) @EXTRALIBS@
|
||||
$(DLLTOOL) --dllname ivl@EXEEXT@ --def $(srcdir)/ivl.def \
|
||||
--output-lib libivl.a --output-exp ivl.exp
|
||||
$(CXX) $(LDFLAGS) -o ivl@EXEEXT@ ivl.exp $O $(dllib) @EXTRALIBS@
|
||||
else
|
||||
ivl@EXEEXT@: $O
|
||||
$(CXX) $(LDFLAGS) -o ivl@EXEEXT@ $O $(dllib)
|
||||
endif
|
||||
|
||||
ifeq (@MINGW32@,no)
|
||||
all: iverilog-vpi
|
||||
|
||||
iverilog-vpi: $(srcdir)/iverilog-vpi.sh Makefile
|
||||
sed -e 's;@SHARED@;@shared@;' -e 's;@PIC@;@PICFLAG@;' \
|
||||
-e 's;@SUFFIX@;$(suffix);' \
|
||||
-e 's;@IVCC@;$(CC);' \
|
||||
-e 's;@IVCXX@;$(CXX);' \
|
||||
-e 's;@IVCFLAGS@;$(CFLAGS);' \
|
||||
-e 's;@IVCXXFLAGS@;$(CXXFLAGS);' \
|
||||
-e 's;@IVCTARGETFLAGS@;$(CTARGETFLAGS);' \
|
||||
-e 's;@INCLUDEDIR@;$(includedir);' \
|
||||
-e 's;@LIBDIR@;@libdir@;' $< > $@
|
||||
chmod +x $@
|
||||
endif
|
||||
|
||||
version.exe: $(srcdir)/version.c $(srcdir)/version_base.h version_tag.h
|
||||
$(BUILDCC) $(CFLAGS) -o version.exe -I. -I$(srcdir) $(srcdir)/version.c
|
||||
|
||||
%.o: %.cc config.h
|
||||
$(CXX) $(CPPFLAGS) $(CXXFLAGS) @DEPENDENCY_FLAG@ -c $< -o $*.o
|
||||
mv $*.d dep/$*.d
|
||||
|
||||
# Here are some explicit dependencies needed to get things going.
|
||||
main.o: main.cc version_tag.h
|
||||
|
||||
lexor.o: lexor.cc parse.h
|
||||
|
||||
parse.o: parse.cc
|
||||
|
||||
# Use pattern rules to avoid parallel build issues (see pr3462585)
|
||||
parse%cc parse%h: $(srcdir)/parse%y
|
||||
$(YACC) --verbose -t -p VL --defines=parse.h -o parse.cc $<
|
||||
|
||||
syn-rules.cc: $(srcdir)/syn-rules.y
|
||||
$(YACC) --verbose -t -p syn_ -o $@ $<
|
||||
|
||||
lexor.cc: $(srcdir)/lexor.lex
|
||||
$(LEX) -s -t $< > $@
|
||||
|
||||
lexor_keyword.o: lexor_keyword.cc parse.h
|
||||
|
||||
lexor_keyword.cc: $(srcdir)/lexor_keyword.gperf
|
||||
gperf -o -i 7 -C -k 1-4,6,9,$$ -H keyword_hash -N check_identifier -t $(srcdir)/lexor_keyword.gperf > lexor_keyword.cc || (rm -f lexor_keyword.cc ; false)
|
||||
|
||||
iverilog-vpi.man: $(srcdir)/iverilog-vpi.man.in version.exe
|
||||
./version.exe `head -1 $(srcdir)/iverilog-vpi.man.in`'\n' > $@
|
||||
tail -n +2 $(srcdir)/iverilog-vpi.man.in >> $@
|
||||
|
||||
iverilog-vpi.ps: iverilog-vpi.man
|
||||
$(MAN) -t ./iverilog-vpi.man > iverilog-vpi.ps
|
||||
|
||||
iverilog-vpi.pdf: iverilog-vpi.ps
|
||||
$(PS2PDF) iverilog-vpi.ps iverilog-vpi.pdf
|
||||
|
||||
# For VERSION_TAG in driver/main.c, first try git-describe, then look for a
|
||||
# version_tag.h file in the source tree (included in snapshots and releases),
|
||||
# and finally use nothing.
|
||||
|
||||
# "true" and "false" in the next few lines are Unix shell command names
|
||||
ifeq ($(GIT),none)
|
||||
GIT_PRESENT = false
|
||||
else
|
||||
GIT_PRESENT = true
|
||||
endif
|
||||
version_tag.h version:
|
||||
@if $(GIT_PRESENT) && test -d $(srcdir)/.git; then \
|
||||
echo "Using git-describe for VERSION_TAG"; \
|
||||
tmp=`(cd $(srcdir) && $(GIT) describe --always --dirty) \
|
||||
| sed -e 's;\(.*\);#define VERSION_TAG "\1";'`; \
|
||||
echo "$$tmp" | diff - version_tag.h > /dev/null 2>&1 || echo "$$tmp" > version_tag.h || exit 1; \
|
||||
elif test -r $(srcdir)/version_tag.h; then \
|
||||
echo "Using $(srcdir)/version_tag.h for VERSION_TAG"; \
|
||||
diff $(srcdir)/version_tag.h version_tag.h > /dev/null 2>&1 || cp $(srcdir)/version_tag.h version_tag.h; \
|
||||
else \
|
||||
echo "Using empty VERSION_TAG"; \
|
||||
echo '#define VERSION_TAG ""' > version_tag.h; \
|
||||
fi
|
||||
|
||||
ifeq (@MINGW32@,yes)
|
||||
ifeq ($(MAN),none)
|
||||
INSTALL_DOC = installman
|
||||
else
|
||||
ifeq ($(PS2PDF),none)
|
||||
INSTALL_DOC = installman
|
||||
else
|
||||
INSTALL_DOC = installpdf installman
|
||||
all: dep iverilog-vpi.pdf
|
||||
endif
|
||||
endif
|
||||
INSTALL_DOCDIR = $(mandir)/man1
|
||||
else
|
||||
INSTALL_DOC = installman
|
||||
INSTALL_DOCDIR = $(mandir)/man1
|
||||
endif
|
||||
|
||||
ifeq (@MINGW32@,yes)
|
||||
WIN32_INSTALL =
|
||||
else
|
||||
WIN32_INSTALL = installwin32
|
||||
endif
|
||||
|
||||
install: all installdirs installfiles
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
|
||||
F = ./ivl@EXEEXT@ \
|
||||
$(srcdir)/constants.vams \
|
||||
$(srcdir)/disciplines.vams \
|
||||
$(srcdir)/ivl_target.h \
|
||||
./_pli_types.h \
|
||||
$(srcdir)/sv_vpi_user.h \
|
||||
$(srcdir)/vpi_user.h \
|
||||
$(srcdir)/acc_user.h \
|
||||
$(srcdir)/veriuser.h \
|
||||
$(INSTALL_DOC) \
|
||||
$(WIN32_INSTALL)
|
||||
|
||||
installwin32: ./iverilog-vpi installdirs
|
||||
$(INSTALL_SCRIPT) ./iverilog-vpi "$(DESTDIR)$(bindir)/iverilog-vpi$(suffix)"
|
||||
|
||||
installman: iverilog-vpi.man installdirs
|
||||
$(INSTALL_DATA) iverilog-vpi.man "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1"
|
||||
|
||||
installpdf: iverilog-vpi.pdf installdirs
|
||||
$(INSTALL_DATA) iverilog-vpi.pdf "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"
|
||||
|
||||
installfiles: $(F) | installdirs
|
||||
$(INSTALL_PROGRAM) ./ivl@EXEEXT@ "$(DESTDIR)$(libdir)/ivl$(suffix)/ivl@EXEEXT@"
|
||||
$(INSTALL_DATA) $(srcdir)/constants.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/constants.vams"
|
||||
$(INSTALL_DATA) $(srcdir)/disciplines.vams "$(DESTDIR)$(libdir)/ivl$(suffix)/include/disciplines.vams"
|
||||
$(INSTALL_DATA) $(srcdir)/ivl_target.h "$(DESTDIR)$(includedir)/ivl_target.h"
|
||||
$(INSTALL_DATA) ./_pli_types.h "$(DESTDIR)$(includedir)/_pli_types.h"
|
||||
$(INSTALL_DATA) $(srcdir)/sv_vpi_user.h "$(DESTDIR)$(includedir)/sv_vpi_user.h"
|
||||
$(INSTALL_DATA) $(srcdir)/vpi_user.h "$(DESTDIR)$(includedir)/vpi_user.h"
|
||||
$(INSTALL_DATA) $(srcdir)/acc_user.h "$(DESTDIR)$(includedir)/acc_user.h"
|
||||
$(INSTALL_DATA) $(srcdir)/veriuser.h "$(DESTDIR)$(includedir)/veriuser.h"
|
||||
|
||||
installdirs: $(srcdir)/mkinstalldirs
|
||||
$(srcdir)/mkinstalldirs "$(DESTDIR)$(bindir)" \
|
||||
"$(DESTDIR)$(includedir)" \
|
||||
"$(DESTDIR)$(libdir)/ivl$(suffix)" \
|
||||
"$(DESTDIR)$(libdir)/ivl$(suffix)/include" \
|
||||
"$(DESTDIR)$(mandir)" \
|
||||
"$(DESTDIR)$(mandir)/man1"
|
||||
|
||||
uninstall:
|
||||
$(foreach dir,$(SUBDIRS),$(MAKE) -C $(dir) $@ && ) true
|
||||
for f in ivl@EXEEXT@ include/constants.vams include/disciplines.vams; \
|
||||
do rm -f "$(DESTDIR)$(libdir)/ivl$(suffix)/$$f"; done
|
||||
-rmdir "$(DESTDIR)$(libdir)/ivl$(suffix)/include"
|
||||
-rmdir "$(DESTDIR)$(libdir)/ivl$(suffix)"
|
||||
for f in verilog$(suffix) iverilog-vpi$(suffix) gverilog$(suffix)@EXEEXT@; \
|
||||
do rm -f "$(DESTDIR)$(bindir)/$$f"; done
|
||||
for f in ivl_target.h vpi_user.h _pli_types.h sv_vpi_user.h acc_user.h veriuser.h; \
|
||||
do rm -f "$(DESTDIR)$(includedir)/$$f"; done
|
||||
-test X$(suffix) = X || rmdir "$(DESTDIR)$(includedir)"
|
||||
rm -f "$(DESTDIR)$(mandir)/man1/iverilog-vpi$(suffix).1" "$(DESTDIR)$(prefix)/iverilog-vpi$(suffix).pdf"
|
||||
|
||||
|
||||
-include $(patsubst %.o, dep/%.d, $O)
|
||||
@@ -1,134 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1998-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "Module.h"
|
||||
# include "PGate.h"
|
||||
# include "PWire.h"
|
||||
# include <cassert>
|
||||
|
||||
list<Module::named_expr_t> Module::user_defparms;
|
||||
|
||||
/* n is a permallocated string. */
|
||||
Module::Module(LexicalScope*parent, perm_string n)
|
||||
: PScopeExtra(n, parent)
|
||||
{
|
||||
library_flag = false;
|
||||
is_cell = false;
|
||||
is_interface = false;
|
||||
program_block = false;
|
||||
uc_drive = UCD_NONE;
|
||||
}
|
||||
|
||||
Module::~Module()
|
||||
{
|
||||
}
|
||||
|
||||
void Module::add_gate(PGate*gate)
|
||||
{
|
||||
gates_.push_back(gate);
|
||||
}
|
||||
|
||||
unsigned Module::port_count() const
|
||||
{
|
||||
return ports.size();
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the array of PEIdent object that are at this port of the
|
||||
* module. If the port is internally unconnected, return an empty
|
||||
* array.
|
||||
*/
|
||||
const vector<PEIdent*>& Module::get_port(unsigned idx) const
|
||||
{
|
||||
assert(idx < ports.size());
|
||||
static const vector<PEIdent*> zero;
|
||||
|
||||
if (ports[idx])
|
||||
return ports[idx]->expr;
|
||||
else
|
||||
return zero;
|
||||
}
|
||||
|
||||
unsigned Module::find_port(const char*name) const
|
||||
{
|
||||
assert(name != 0);
|
||||
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
|
||||
if (ports[idx] == 0) {
|
||||
/* It is possible to have undeclared ports. These
|
||||
are ports that are skipped in the declaration,
|
||||
for example like so: module foo(x ,, y); The
|
||||
port between x and y is unnamed and thus
|
||||
inaccessible to binding by name. */
|
||||
continue;
|
||||
}
|
||||
assert(ports[idx]);
|
||||
if (ports[idx]->name == name)
|
||||
return idx;
|
||||
}
|
||||
|
||||
return ports.size();
|
||||
}
|
||||
|
||||
perm_string Module::get_port_name(unsigned idx) const
|
||||
{
|
||||
|
||||
assert(idx < ports.size());
|
||||
if (ports[idx] == 0 || ports[idx]->name.str() == 0) {
|
||||
/* It is possible to have undeclared ports. These
|
||||
are ports that are skipped in the declaration,
|
||||
for example like so: module foo(x ,, y); The
|
||||
port between x and y is unnamed and thus
|
||||
inaccessible to binding by name. Port references
|
||||
that aren't simple or escaped identifiers are
|
||||
also inaccessible to binding by name. */
|
||||
return perm_string::literal("unnamed");
|
||||
}
|
||||
return ports[idx]->name;
|
||||
}
|
||||
|
||||
|
||||
|
||||
PGate* Module::get_gate(perm_string name)
|
||||
{
|
||||
for (list<PGate*>::iterator cur = gates_.begin()
|
||||
; cur != gates_.end() ; ++ cur ) {
|
||||
|
||||
if ((*cur)->get_name() == name)
|
||||
return *cur;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const list<PGate*>& Module::get_gates() const
|
||||
{
|
||||
return gates_;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType Module::symbol_type() const
|
||||
{
|
||||
if (program_block)
|
||||
return PROGRAM;
|
||||
if (is_interface)
|
||||
return INTERFACE;
|
||||
|
||||
return MODULE;
|
||||
}
|
||||
@@ -1,174 +0,0 @@
|
||||
#ifndef IVL_Module_H
|
||||
#define IVL_Module_H
|
||||
/*
|
||||
* Copyright (c) 1998-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
|
||||
# include <list>
|
||||
# include <map>
|
||||
# include <vector>
|
||||
# include <utility>
|
||||
# include "StringHeap.h"
|
||||
# include "HName.h"
|
||||
# include "named.h"
|
||||
# include "PScope.h"
|
||||
# include "PNamedItem.h"
|
||||
# include "netlist.h"
|
||||
# include "pform_types.h"
|
||||
class PExpr;
|
||||
class PEIdent;
|
||||
class PGate;
|
||||
class PGenerate;
|
||||
class PModport;
|
||||
class PSpecPath;
|
||||
class PTask;
|
||||
class PFunction;
|
||||
class PWire;
|
||||
class PProcess;
|
||||
class Design;
|
||||
class NetScope;
|
||||
|
||||
/*
|
||||
* A module is a named container and scope. A module holds a bunch of
|
||||
* semantic quantities such as wires and gates. The module is
|
||||
* therefore the handle for grasping the described circuit.
|
||||
*
|
||||
* SystemVerilog introduces program blocks and interfaces. These have
|
||||
* much in common with modules, so the Module class is used to represent
|
||||
* these containers as well.
|
||||
*/
|
||||
|
||||
class Module : public PScopeExtra, public PNamedItem {
|
||||
|
||||
/* The module ports are in general a vector of port_t
|
||||
objects. Each port has a name and an ordered list of
|
||||
wires. The name is the means that the outside uses to
|
||||
access the port, the wires are the internal connections to
|
||||
the port. */
|
||||
public:
|
||||
struct port_t {
|
||||
perm_string name;
|
||||
vector<PEIdent*> expr;
|
||||
};
|
||||
|
||||
public:
|
||||
/* The name passed here is the module name, not the instance
|
||||
name. This name must be a permallocated string. */
|
||||
explicit Module(LexicalScope*parent, perm_string name);
|
||||
~Module();
|
||||
|
||||
/* Initially false. This is set to true if the module has been
|
||||
declared as a library module. This makes the module
|
||||
ineligible for being chosen as an implicit root. It has no
|
||||
other effect. */
|
||||
bool library_flag;
|
||||
|
||||
bool is_cell;
|
||||
|
||||
/* This is true if the module represents a program block
|
||||
instead of a module/cell. Program blocks have content
|
||||
restrictions and slightly modify scheduling semantics. */
|
||||
bool program_block;
|
||||
|
||||
/* This is true if the module represents a interface
|
||||
instead of a module/cell. Interfaces have different
|
||||
content restrictions and some extra allowed items. */
|
||||
bool is_interface;
|
||||
|
||||
enum UCDriveType { UCD_NONE, UCD_PULL0, UCD_PULL1 };
|
||||
UCDriveType uc_drive;
|
||||
|
||||
/* specparams are simpler than other parameters, in that they
|
||||
can have a range, but not an explicit type. The restrictions
|
||||
are enforced by the parser. */
|
||||
map<perm_string,param_expr_t*>specparams;
|
||||
|
||||
/* The module also has defparam assignments which don't create
|
||||
new parameters within the module, but may be used to set
|
||||
values within this module (when instantiated) or in other
|
||||
instantiated modules. */
|
||||
typedef pair<pform_name_t,PExpr*> named_expr_t;
|
||||
list<named_expr_t>defparms;
|
||||
static list<named_expr_t>user_defparms;
|
||||
|
||||
/* Parameters may be overridden at instantiation time;
|
||||
the overrides do not contain explicit parameter names,
|
||||
but rather refer to parameters in the order they
|
||||
appear in the instantiated module. Therefore a
|
||||
list of names in module-order is needed to pass from
|
||||
a parameter-index to its name. */
|
||||
list<perm_string> param_names;
|
||||
|
||||
/* This is an array of port descriptors, which is in turn a
|
||||
named array of PEident pointers. */
|
||||
vector<port_t*> ports;
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
/* The module has a list of generate schemes that appear in
|
||||
the module definition. These are used at elaboration time. */
|
||||
list<PGenerate*> generate_schemes;
|
||||
|
||||
/* Nested modules are placed here, and are not elaborated
|
||||
unless they are instantiated, implicitly or explicitly. */
|
||||
std::map<perm_string,Module*> nested_modules;
|
||||
|
||||
/* An interface can contain one or more named modport lists.
|
||||
The parser will ensure these don't appear in modules or
|
||||
program blocks. */
|
||||
map<perm_string,PModport*> modports;
|
||||
|
||||
list<PSpecPath*> specify_paths;
|
||||
|
||||
// The mod_name() is the name of the module type.
|
||||
perm_string mod_name() const { return pscope_name(); }
|
||||
|
||||
void add_gate(PGate*gate);
|
||||
|
||||
unsigned port_count() const;
|
||||
const vector<PEIdent*>& get_port(unsigned idx) const;
|
||||
unsigned find_port(const char*name) const;
|
||||
|
||||
// Return port name ("" for undeclared port)
|
||||
perm_string get_port_name(unsigned idx) const;
|
||||
|
||||
PGate* get_gate(perm_string name);
|
||||
|
||||
const list<PGate*>& get_gates() const;
|
||||
|
||||
void dump(ostream&out) const;
|
||||
bool elaborate(Design*, NetScope*scope) const;
|
||||
|
||||
typedef map<perm_string,PExpr*> replace_t;
|
||||
bool elaborate_scope(Design*, NetScope*scope, const replace_t&rep);
|
||||
|
||||
bool elaborate_sig(Design*, NetScope*scope) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
void dump_specparams_(ostream&out, unsigned indent) const;
|
||||
list<PGate*> gates_;
|
||||
|
||||
private: // Not implemented
|
||||
Module(const Module&);
|
||||
Module& operator= (const Module&);
|
||||
};
|
||||
|
||||
#endif /* IVL_Module_H */
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2012-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PClass.h"
|
||||
|
||||
PClass::PClass(perm_string name, LexicalScope*parent)
|
||||
: PScopeExtra(name, parent), type(0)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
PClass::~PClass()
|
||||
{
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PClass::symbol_type() const
|
||||
{
|
||||
return CLASS;
|
||||
}
|
||||
@@ -1,49 +0,0 @@
|
||||
#ifndef IVL_PClass_H
|
||||
#define IVL_PClass_H
|
||||
/*
|
||||
* Copyright (c) 2012-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PScope.h"
|
||||
# include "PNamedItem.h"
|
||||
# include "StringHeap.h"
|
||||
# include <iostream>
|
||||
|
||||
class PChainConstructor;
|
||||
|
||||
/*
|
||||
* SystemVerilog supports class declarations with their own lexical
|
||||
* scope, etc. The parser arranges for these to be created and
|
||||
* collected.
|
||||
*/
|
||||
|
||||
class PClass : public PScopeExtra, public PNamedItem {
|
||||
|
||||
public:
|
||||
explicit PClass (perm_string name, LexicalScope*parent);
|
||||
~PClass();
|
||||
|
||||
void dump(std::ostream&out, unsigned indent) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
public:
|
||||
class_type_t*type;
|
||||
};
|
||||
|
||||
#endif /* IVL_PClass_H */
|
||||
-183
@@ -1,183 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1999-2017 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include <iostream>
|
||||
|
||||
# include "PDelays.h"
|
||||
# include "PExpr.h"
|
||||
# include "verinum.h"
|
||||
# include "netmisc.h"
|
||||
|
||||
PDelays::PDelays()
|
||||
{
|
||||
delete_flag_ = true;
|
||||
for (unsigned idx = 0 ; idx < 3 ; idx += 1)
|
||||
delay_[idx] = 0;
|
||||
}
|
||||
|
||||
PDelays::~PDelays()
|
||||
{
|
||||
if (delete_flag_) {
|
||||
for (unsigned idx = 0 ; idx < 3 ; idx += 1)
|
||||
delete delay_[idx];
|
||||
}
|
||||
}
|
||||
|
||||
void PDelays::set_delay(PExpr*del)
|
||||
{
|
||||
assert(del);
|
||||
assert(delay_[0] == 0);
|
||||
delay_[0] = del;
|
||||
delete_flag_ = true;
|
||||
}
|
||||
|
||||
|
||||
void PDelays::set_delays(const list<PExpr*>*del, bool df)
|
||||
{
|
||||
assert(del);
|
||||
assert(del->size() <= 3);
|
||||
|
||||
list<PExpr*>::const_iterator cur = del->begin();
|
||||
for (unsigned idx = 0 ; cur != del->end() ; idx += 1, ++cur)
|
||||
delay_[idx] = *cur;
|
||||
|
||||
delete_flag_ = df;
|
||||
}
|
||||
|
||||
unsigned PDelays::delay_count() const
|
||||
{
|
||||
unsigned dly_cnt = 0;
|
||||
for (unsigned idx = 0 ; idx < 3 ; idx += 1)
|
||||
if (delay_[idx]) dly_cnt += 1;
|
||||
|
||||
return dly_cnt;
|
||||
}
|
||||
|
||||
static NetExpr*calculate_val(Design*des, NetScope*scope, PExpr*expr)
|
||||
{
|
||||
NetExpr*dex = elab_and_eval(des, scope, expr, -1);
|
||||
|
||||
check_for_inconsistent_delays(scope);
|
||||
|
||||
/* If the delay expression is a real constant or vector
|
||||
constant, then evaluate it, scale it to the local time
|
||||
units, and return an adjusted value. */
|
||||
|
||||
if (NetECReal*tmp = dynamic_cast<NetECReal*>(dex)) {
|
||||
uint64_t delay = get_scaled_time_from_real(des, scope, tmp);
|
||||
|
||||
delete tmp;
|
||||
NetEConst*tmp2 = new NetEConst(verinum(delay, 64));
|
||||
tmp2->set_line(*expr);
|
||||
return tmp2;
|
||||
}
|
||||
|
||||
|
||||
if (NetEConst*tmp = dynamic_cast<NetEConst*>(dex)) {
|
||||
verinum fn = tmp->value();
|
||||
uint64_t delay = des->scale_to_precision(fn.as_ulong64(), scope);
|
||||
|
||||
delete tmp;
|
||||
NetEConst*tmp2 = new NetEConst(verinum(delay, 64));
|
||||
tmp2->set_line(*expr);
|
||||
return tmp2;
|
||||
}
|
||||
|
||||
/* Oops, cannot evaluate down to a constant. */
|
||||
return dex;
|
||||
}
|
||||
|
||||
static NetExpr* make_delay_nets(Design*des, NetScope*scope, NetExpr*expr)
|
||||
{
|
||||
if (expr == 0)
|
||||
return 0;
|
||||
|
||||
if (dynamic_cast<NetESignal*> (expr))
|
||||
return expr;
|
||||
|
||||
if (dynamic_cast<NetEConst*> (expr))
|
||||
return expr;
|
||||
|
||||
NetNet*sig = expr->synthesize(des, scope, expr);
|
||||
if (sig == 0) {
|
||||
cerr << expr->get_fileline() << ": error: Expression " << *expr
|
||||
<< " is not suitable as a delay expression." << endl;
|
||||
des->errors += 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
expr = new NetESignal(sig);
|
||||
return expr;
|
||||
}
|
||||
|
||||
static NetExpr* calc_decay_time(NetExpr *rise, NetExpr *fall)
|
||||
{
|
||||
NetEConst *c_rise = dynamic_cast<NetEConst*>(rise);
|
||||
NetEConst *c_fall = dynamic_cast<NetEConst*>(fall);
|
||||
if (c_rise && c_fall) {
|
||||
if (c_rise->value() < c_fall->value()) return rise;
|
||||
else return fall;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void PDelays::eval_delays(Design*des, NetScope*scope,
|
||||
NetExpr*&rise_time,
|
||||
NetExpr*&fall_time,
|
||||
NetExpr*&decay_time,
|
||||
bool as_nets_flag) const
|
||||
{
|
||||
assert(scope);
|
||||
|
||||
|
||||
if (delay_[0]) {
|
||||
rise_time = calculate_val(des, scope, delay_[0]);
|
||||
if (as_nets_flag)
|
||||
rise_time = make_delay_nets(des, scope, rise_time);
|
||||
|
||||
if (delay_[1]) {
|
||||
fall_time = calculate_val(des, scope, delay_[1]);
|
||||
if (as_nets_flag)
|
||||
fall_time = make_delay_nets(des, scope, fall_time);
|
||||
|
||||
if (delay_[2]) {
|
||||
decay_time = calculate_val(des, scope, delay_[2]);
|
||||
if (as_nets_flag)
|
||||
decay_time = make_delay_nets(des, scope,
|
||||
decay_time);
|
||||
|
||||
} else {
|
||||
// If this is zero then we need to do the min()
|
||||
// at run time.
|
||||
decay_time = calc_decay_time(rise_time, fall_time);
|
||||
}
|
||||
} else {
|
||||
assert(delay_[2] == 0);
|
||||
fall_time = rise_time;
|
||||
decay_time = rise_time;
|
||||
}
|
||||
} else {
|
||||
rise_time = 0;
|
||||
fall_time = 0;
|
||||
decay_time = 0;
|
||||
}
|
||||
}
|
||||
@@ -1,75 +0,0 @@
|
||||
#ifndef IVL_PDelays_H
|
||||
#define IVL_PDelays_H
|
||||
/*
|
||||
* Copyright (c) 1999-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "svector.h"
|
||||
# include <string>
|
||||
# include <list>
|
||||
# include <iostream>
|
||||
|
||||
#ifdef __GNUC__
|
||||
#if __GNUC__ > 2
|
||||
using namespace std;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
class Design;
|
||||
class NetScope;
|
||||
class NetExpr;
|
||||
class PExpr;
|
||||
|
||||
/*
|
||||
* Various PForm objects can carry delays. These delays include rise,
|
||||
* fall and decay times. This class arranges to carry the triplet.
|
||||
*/
|
||||
class PDelays {
|
||||
|
||||
public:
|
||||
PDelays();
|
||||
~PDelays();
|
||||
|
||||
/* Set the delay expressions. If the delete_flag is true, then
|
||||
this object takes ownership of the expressions, and will
|
||||
delete it in the destructor. */
|
||||
void set_delay(PExpr*);
|
||||
void set_delays(const list<PExpr*>*del, bool delete_flag=true);
|
||||
|
||||
unsigned delay_count() const;
|
||||
|
||||
void eval_delays(Design*des, NetScope*scope,
|
||||
NetExpr*&rise_time,
|
||||
NetExpr*&fall_time,
|
||||
NetExpr*&decay_time,
|
||||
bool as_nets_flag =false) const;
|
||||
|
||||
void dump_delays(ostream&out) const;
|
||||
|
||||
private:
|
||||
PExpr* delay_[3];
|
||||
bool delete_flag_;
|
||||
|
||||
private: // not implemented
|
||||
PDelays(const PDelays&);
|
||||
PDelays& operator= (const PDelays&);
|
||||
};
|
||||
|
||||
ostream& operator << (ostream&o, const PDelays&);
|
||||
|
||||
#endif /* IVL_PDelays_H */
|
||||
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2004-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "PEvent.h"
|
||||
|
||||
PEvent::PEvent(perm_string n)
|
||||
: name_(n)
|
||||
{
|
||||
}
|
||||
|
||||
PEvent::~PEvent()
|
||||
{
|
||||
}
|
||||
|
||||
perm_string PEvent::name() const
|
||||
{
|
||||
return name_;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PEvent::symbol_type() const
|
||||
{
|
||||
return EVENT;
|
||||
}
|
||||
@@ -1,56 +0,0 @@
|
||||
#ifndef IVL_PEvent_H
|
||||
#define IVL_PEvent_H
|
||||
/*
|
||||
* Copyright (c) 2000-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PNamedItem.h"
|
||||
# include "StringHeap.h"
|
||||
# include <string>
|
||||
|
||||
class Design;
|
||||
class NetScope;
|
||||
|
||||
/*
|
||||
* The PEvent class represents event objects. These are things that
|
||||
* are declared in Verilog as ``event foo;'' The name passed to the
|
||||
* constructor is the "foo" part of the declaration.
|
||||
*/
|
||||
class PEvent : public PNamedItem {
|
||||
|
||||
public:
|
||||
// The name is a perm-allocated string. It is the simple name
|
||||
// of the event, without any scope.
|
||||
explicit PEvent(perm_string name);
|
||||
~PEvent();
|
||||
|
||||
perm_string name() const;
|
||||
|
||||
void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
|
||||
private: // not implemented
|
||||
PEvent(const PEvent&);
|
||||
PEvent& operator= (const PEvent&);
|
||||
};
|
||||
|
||||
#endif /* IVL_PEvent_H */
|
||||
@@ -1,587 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1998-2020 Stephen Williams <[email protected]>
|
||||
* Copyright CERN 2013 / Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include <iostream>
|
||||
|
||||
# include "compiler.h"
|
||||
# include "PExpr.h"
|
||||
# include "PWire.h"
|
||||
# include "Module.h"
|
||||
# include "netmisc.h"
|
||||
# include "util.h"
|
||||
# include <typeinfo>
|
||||
|
||||
PExpr::PExpr()
|
||||
{
|
||||
expr_type_ = IVL_VT_NO_TYPE;
|
||||
expr_width_ = 0;
|
||||
min_width_ = 0;
|
||||
signed_flag_ = false;
|
||||
}
|
||||
|
||||
PExpr::~PExpr()
|
||||
{
|
||||
}
|
||||
|
||||
void PExpr::declare_implicit_nets(LexicalScope*, NetNet::Type)
|
||||
{
|
||||
}
|
||||
|
||||
bool PExpr::has_aa_term(Design*, NetScope*) const
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
bool PExpr::is_the_same(const PExpr*that) const
|
||||
{
|
||||
return typeid(this) == typeid(that);
|
||||
}
|
||||
|
||||
NetNet* PExpr::elaborate_lnet(Design*, NetScope*) const
|
||||
{
|
||||
cerr << get_fileline() << ": error: "
|
||||
<< "expression not valid in assign l-value: "
|
||||
<< *this << endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
NetNet* PExpr::elaborate_bi_net(Design*, NetScope*) const
|
||||
{
|
||||
cerr << get_fileline() << ": error: "
|
||||
<< "expression not valid as argument to inout port: "
|
||||
<< *this << endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool PExpr::is_collapsible_net(Design*, NetScope*) const
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
const char* PExpr::width_mode_name(width_mode_t mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case PExpr::SIZED:
|
||||
return "sized";
|
||||
case PExpr::UNSIZED:
|
||||
return "unsized";
|
||||
case PExpr::EXPAND:
|
||||
return "expand";
|
||||
case PExpr::LOSSLESS:
|
||||
return "lossless";
|
||||
case PExpr::UPSIZE:
|
||||
return "upsize";
|
||||
default:
|
||||
return "??";
|
||||
}
|
||||
}
|
||||
|
||||
PEAssignPattern::PEAssignPattern()
|
||||
{
|
||||
}
|
||||
|
||||
PEAssignPattern::PEAssignPattern(const list<PExpr*>&p)
|
||||
: parms_(p.size())
|
||||
{
|
||||
size_t idx = 0;
|
||||
for (list<PExpr*>::const_iterator cur = p.begin()
|
||||
; cur != p.end() ; ++cur) {
|
||||
parms_[idx] = *cur;
|
||||
idx += 1;
|
||||
}
|
||||
}
|
||||
|
||||
PEAssignPattern::~PEAssignPattern()
|
||||
{
|
||||
}
|
||||
|
||||
PEBinary::PEBinary(char op, PExpr*l, PExpr*r)
|
||||
: op_(op), left_(l), right_(r)
|
||||
{
|
||||
}
|
||||
|
||||
PEBinary::~PEBinary()
|
||||
{
|
||||
}
|
||||
|
||||
void PEBinary::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
if (left_) left_->declare_implicit_nets(scope, type);
|
||||
if (right_) right_->declare_implicit_nets(scope, type);
|
||||
}
|
||||
|
||||
bool PEBinary::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
assert(left_ && right_);
|
||||
return left_->has_aa_term(des, scope) || right_->has_aa_term(des, scope);
|
||||
}
|
||||
|
||||
PECastSize::PECastSize(PExpr*si, PExpr*b)
|
||||
: size_(si), base_(b)
|
||||
{
|
||||
}
|
||||
|
||||
PECastSize::~PECastSize()
|
||||
{
|
||||
}
|
||||
|
||||
PECastType::PECastType(data_type_t*t, PExpr*b)
|
||||
: target_(t), base_(b)
|
||||
{
|
||||
}
|
||||
|
||||
PECastType::~PECastType()
|
||||
{
|
||||
}
|
||||
|
||||
PEBComp::PEBComp(char op, PExpr*l, PExpr*r)
|
||||
: PEBinary(op, l, r)
|
||||
{
|
||||
l_width_ = 0;
|
||||
r_width_ = 0;
|
||||
}
|
||||
|
||||
PEBComp::~PEBComp()
|
||||
{
|
||||
}
|
||||
|
||||
PEBLogic::PEBLogic(char op, PExpr*l, PExpr*r)
|
||||
: PEBinary(op, l, r)
|
||||
{
|
||||
assert(op == 'a' || op == 'o' || op == 'q' || op == 'Q');
|
||||
}
|
||||
|
||||
PEBLogic::~PEBLogic()
|
||||
{
|
||||
}
|
||||
|
||||
PEBLeftWidth::PEBLeftWidth(char op, PExpr*l, PExpr*r)
|
||||
: PEBinary(op, l, r)
|
||||
{
|
||||
}
|
||||
|
||||
PEBLeftWidth::~PEBLeftWidth()
|
||||
{
|
||||
}
|
||||
|
||||
PEBPower::PEBPower(char op, PExpr*l, PExpr*r)
|
||||
: PEBLeftWidth(op, l, r)
|
||||
{
|
||||
}
|
||||
|
||||
PEBPower::~PEBPower()
|
||||
{
|
||||
}
|
||||
|
||||
PEBShift::PEBShift(char op, PExpr*l, PExpr*r)
|
||||
: PEBLeftWidth(op, l, r)
|
||||
{
|
||||
}
|
||||
|
||||
PEBShift::~PEBShift()
|
||||
{
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(const pform_name_t&n, const vector<PExpr *> &parms)
|
||||
: package_(0), path_(n), parms_(parms), is_overridden_(false)
|
||||
{
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(PPackage*pkg, const pform_name_t&n, const vector<PExpr *> &parms)
|
||||
: package_(pkg), path_(n), parms_(parms), is_overridden_(false)
|
||||
{
|
||||
}
|
||||
|
||||
static pform_name_t pn_from_ps(perm_string n)
|
||||
{
|
||||
name_component_t tmp_name (n);
|
||||
pform_name_t tmp;
|
||||
tmp.push_back(tmp_name);
|
||||
return tmp;
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(PPackage*pkg, perm_string n, const list<PExpr *> &parms)
|
||||
: package_(pkg), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
|
||||
{
|
||||
int tmp_idx = 0;
|
||||
assert(parms_.size() == parms.size());
|
||||
for (list<PExpr*>::const_iterator idx = parms.begin()
|
||||
; idx != parms.end() ; ++idx)
|
||||
parms_[tmp_idx++] = *idx;
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(perm_string n, const vector<PExpr*>&parms)
|
||||
: package_(0), path_(pn_from_ps(n)), parms_(parms), is_overridden_(false)
|
||||
{
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(perm_string n)
|
||||
: package_(0), path_(pn_from_ps(n)), is_overridden_(false)
|
||||
{
|
||||
}
|
||||
|
||||
// NOTE: Anachronism. Try to work all use of svector out.
|
||||
PECallFunction::PECallFunction(const pform_name_t&n, const list<PExpr *> &parms)
|
||||
: package_(0), path_(n), parms_(parms.size()), is_overridden_(false)
|
||||
{
|
||||
int tmp_idx = 0;
|
||||
assert(parms_.size() == parms.size());
|
||||
for (list<PExpr*>::const_iterator idx = parms.begin()
|
||||
; idx != parms.end() ; ++idx)
|
||||
parms_[tmp_idx++] = *idx;
|
||||
}
|
||||
|
||||
PECallFunction::PECallFunction(perm_string n, const list<PExpr*>&parms)
|
||||
: package_(0), path_(pn_from_ps(n)), parms_(parms.size()), is_overridden_(false)
|
||||
{
|
||||
int tmp_idx = 0;
|
||||
assert(parms_.size() == parms.size());
|
||||
for (list<PExpr*>::const_iterator idx = parms.begin()
|
||||
; idx != parms.end() ; ++idx)
|
||||
parms_[tmp_idx++] = *idx;
|
||||
}
|
||||
|
||||
PECallFunction::~PECallFunction()
|
||||
{
|
||||
}
|
||||
|
||||
void PECallFunction::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx]->declare_implicit_nets(scope, type);
|
||||
}
|
||||
}
|
||||
|
||||
bool PECallFunction::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
bool flag = false;
|
||||
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
flag = parms_[idx]->has_aa_term(des, scope) || flag;
|
||||
}
|
||||
return flag;
|
||||
}
|
||||
|
||||
PEConcat::PEConcat(const list<PExpr*>&p, PExpr*r)
|
||||
: parms_(p.size()), width_modes_(SIZED, p.size()), repeat_(r)
|
||||
{
|
||||
int tmp_idx = 0;
|
||||
assert(parms_.size() == p.size());
|
||||
for (list<PExpr*>::const_iterator idx = p.begin()
|
||||
; idx != p.end() ; ++idx)
|
||||
parms_[tmp_idx++] = *idx;
|
||||
|
||||
tested_scope_ = 0;
|
||||
repeat_count_ = 1;
|
||||
}
|
||||
|
||||
PEConcat::~PEConcat()
|
||||
{
|
||||
delete repeat_;
|
||||
}
|
||||
|
||||
void PEConcat::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx]->declare_implicit_nets(scope, type);
|
||||
}
|
||||
}
|
||||
|
||||
bool PEConcat::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
bool flag = false;
|
||||
for (unsigned idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
flag = parms_[idx]->has_aa_term(des, scope) || flag;
|
||||
}
|
||||
if (repeat_)
|
||||
flag = repeat_->has_aa_term(des, scope) || flag;
|
||||
|
||||
return flag;
|
||||
}
|
||||
|
||||
PEEvent::PEEvent(PEEvent::edge_t t, PExpr*e)
|
||||
: type_(t), expr_(e)
|
||||
{
|
||||
}
|
||||
|
||||
PEEvent::~PEEvent()
|
||||
{
|
||||
}
|
||||
|
||||
PEEvent::edge_t PEEvent::type() const
|
||||
{
|
||||
return type_;
|
||||
}
|
||||
|
||||
bool PEEvent::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
assert(expr_);
|
||||
return expr_->has_aa_term(des, scope);
|
||||
}
|
||||
|
||||
PExpr* PEEvent::expr() const
|
||||
{
|
||||
return expr_;
|
||||
}
|
||||
|
||||
PENull::PENull(void)
|
||||
{
|
||||
}
|
||||
|
||||
PENull::~PENull()
|
||||
{
|
||||
}
|
||||
|
||||
PEFNumber::PEFNumber(verireal*v)
|
||||
: value_(v)
|
||||
{
|
||||
}
|
||||
|
||||
PEFNumber::~PEFNumber()
|
||||
{
|
||||
delete value_;
|
||||
}
|
||||
|
||||
const verireal& PEFNumber::value() const
|
||||
{
|
||||
return *value_;
|
||||
}
|
||||
|
||||
PEIdent::PEIdent(const pform_name_t&that)
|
||||
: package_(0), path_(that), no_implicit_sig_(false)
|
||||
{
|
||||
}
|
||||
|
||||
PEIdent::PEIdent(perm_string s, bool no_implicit_sig)
|
||||
: package_(0), no_implicit_sig_(no_implicit_sig)
|
||||
{
|
||||
path_.push_back(name_component_t(s));
|
||||
}
|
||||
|
||||
PEIdent::PEIdent(PPackage*pkg, const pform_name_t&that)
|
||||
: package_(pkg), path_(that), no_implicit_sig_(true)
|
||||
{
|
||||
}
|
||||
|
||||
PEIdent::~PEIdent()
|
||||
{
|
||||
}
|
||||
|
||||
void PEIdent::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
/* We create an implicit wire if:
|
||||
- this is a simple identifier
|
||||
- an identifier of that name has not already been declared in
|
||||
any enclosing scope.
|
||||
- this is not an implicit named port connection */
|
||||
if (no_implicit_sig_)
|
||||
return;
|
||||
if ((path_.size() == 1) && (path_.front().index.size() == 0)) {
|
||||
perm_string name = path_.front().name;
|
||||
LexicalScope*ss = scope;
|
||||
while (ss) {
|
||||
if (ss->wires.find(name) != ss->wires.end())
|
||||
return;
|
||||
if (ss->localparams.find(name) != ss->localparams.end())
|
||||
return;
|
||||
if (ss->parameters.find(name) != ss->parameters.end())
|
||||
return;
|
||||
if (ss->genvars.find(name) != ss->genvars.end())
|
||||
return;
|
||||
if (ss->events.find(name) != ss->events.end())
|
||||
return;
|
||||
/* Strictly speaking, we should also check for name clashes
|
||||
with tasks, functions, named blocks, module instances,
|
||||
and generate blocks. However, this information is not
|
||||
readily available. As these names would not be legal in
|
||||
this context, we can declare implicit nets here and rely
|
||||
on later checks for name clashes to report the error. */
|
||||
|
||||
ss = ss->parent_scope();
|
||||
}
|
||||
PWire*net = new PWire(name, type, NetNet::NOT_A_PORT, IVL_VT_LOGIC);
|
||||
net->set_file(get_file());
|
||||
net->set_lineno(get_lineno());
|
||||
net->set_range_scalar(SR_NET);
|
||||
scope->wires[name] = net;
|
||||
if (warn_implicit) {
|
||||
cerr << get_fileline() << ": warning: implicit "
|
||||
"definition of wire '" << name << "'." << endl;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool PEIdent::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
NetNet* net = 0;
|
||||
const NetExpr*par = 0;
|
||||
NetEvent* eve = 0;
|
||||
|
||||
const NetExpr*ex1, *ex2;
|
||||
|
||||
scope = symbol_search(this, des, scope, path_, net, par, eve, ex1, ex2);
|
||||
|
||||
if (scope)
|
||||
return scope->is_auto();
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
PENewArray::PENewArray(PExpr*size_expr, PExpr*init_expr)
|
||||
: size_(size_expr), init_(init_expr)
|
||||
{
|
||||
}
|
||||
|
||||
PENewArray::~PENewArray()
|
||||
{
|
||||
delete size_;
|
||||
}
|
||||
|
||||
PENewClass::PENewClass(void)
|
||||
{
|
||||
}
|
||||
|
||||
PENewClass::PENewClass(const list<PExpr*>&p)
|
||||
: parms_(p.size())
|
||||
{
|
||||
size_t tmp_idx = 0;
|
||||
for (list<PExpr*>::const_iterator cur = p.begin()
|
||||
; cur != p.end() ; ++ cur) {
|
||||
parms_[tmp_idx++] = *cur;
|
||||
}
|
||||
}
|
||||
|
||||
PENewClass::~PENewClass()
|
||||
{
|
||||
}
|
||||
|
||||
PENewCopy::PENewCopy(PExpr*src)
|
||||
: src_(src)
|
||||
{
|
||||
}
|
||||
|
||||
PENewCopy::~PENewCopy()
|
||||
{
|
||||
}
|
||||
|
||||
PENumber::PENumber(verinum*vp)
|
||||
: value_(vp)
|
||||
{
|
||||
assert(vp);
|
||||
}
|
||||
|
||||
PENumber::~PENumber()
|
||||
{
|
||||
delete value_;
|
||||
}
|
||||
|
||||
const verinum& PENumber::value() const
|
||||
{
|
||||
return *value_;
|
||||
}
|
||||
|
||||
bool PENumber::is_the_same(const PExpr*that) const
|
||||
{
|
||||
const PENumber*obj = dynamic_cast<const PENumber*>(that);
|
||||
if (obj == 0)
|
||||
return false;
|
||||
|
||||
return *value_ == *obj->value_;
|
||||
}
|
||||
|
||||
PEString::PEString(char*s)
|
||||
: text_(s)
|
||||
{
|
||||
}
|
||||
|
||||
PEString::~PEString()
|
||||
{
|
||||
delete[]text_;
|
||||
}
|
||||
|
||||
string PEString::value() const
|
||||
{
|
||||
return text_;
|
||||
}
|
||||
|
||||
PETernary::PETernary(PExpr*e, PExpr*t, PExpr*f)
|
||||
: expr_(e), tru_(t), fal_(f)
|
||||
{
|
||||
}
|
||||
|
||||
PETernary::~PETernary()
|
||||
{
|
||||
}
|
||||
|
||||
void PETernary::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
assert(expr_ && tru_ && fal_);
|
||||
expr_->declare_implicit_nets(scope, type);
|
||||
tru_->declare_implicit_nets(scope, type);
|
||||
fal_->declare_implicit_nets(scope, type);
|
||||
}
|
||||
|
||||
bool PETernary::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
assert(expr_ && tru_ && fal_);
|
||||
return expr_->has_aa_term(des, scope)
|
||||
|| tru_->has_aa_term(des, scope)
|
||||
|| fal_->has_aa_term(des, scope);
|
||||
}
|
||||
|
||||
PETypename::PETypename(data_type_t*dt)
|
||||
: data_type_(dt)
|
||||
{
|
||||
}
|
||||
|
||||
PETypename::~PETypename()
|
||||
{
|
||||
}
|
||||
|
||||
PEUnary::PEUnary(char op, PExpr*ex)
|
||||
: op_(op), expr_(ex)
|
||||
{
|
||||
}
|
||||
|
||||
PEUnary::~PEUnary()
|
||||
{
|
||||
}
|
||||
|
||||
void PEUnary::declare_implicit_nets(LexicalScope*scope, NetNet::Type type)
|
||||
{
|
||||
assert(expr_);
|
||||
expr_->declare_implicit_nets(scope, type);
|
||||
}
|
||||
|
||||
bool PEUnary::has_aa_term(Design*des, NetScope*scope) const
|
||||
{
|
||||
assert(expr_);
|
||||
return expr_->has_aa_term(des, scope);
|
||||
}
|
||||
|
||||
PEVoid::PEVoid()
|
||||
{
|
||||
}
|
||||
|
||||
PEVoid::~PEVoid()
|
||||
{
|
||||
}
|
||||
@@ -1,91 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1999-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
# include "PTask.h"
|
||||
# include "Statement.h"
|
||||
# include <cassert>
|
||||
# include "ivl_assert.h"
|
||||
|
||||
PFunction::PFunction(perm_string name, LexicalScope*parent, bool is_auto__)
|
||||
: PTaskFunc(name, parent), statement_(0)
|
||||
{
|
||||
is_auto_ = is_auto__;
|
||||
return_type_ = 0;
|
||||
}
|
||||
|
||||
PFunction::~PFunction()
|
||||
{
|
||||
}
|
||||
|
||||
void PFunction::set_statement(Statement*s)
|
||||
{
|
||||
assert(s != 0);
|
||||
assert(statement_ == 0);
|
||||
statement_ = s;
|
||||
}
|
||||
|
||||
void PFunction::push_statement_front(Statement*stmt)
|
||||
{
|
||||
// This should not be possible.
|
||||
ivl_assert(*this, statement_);
|
||||
|
||||
// Get the PBlock of the statement. If it is not a PBlock,
|
||||
// then create one to wrap the existing statement and the new
|
||||
// statement that we're pushing.
|
||||
PBlock*blk = dynamic_cast<PBlock*> (statement_);
|
||||
if (blk == 0) {
|
||||
PBlock*tmp = new PBlock(PBlock::BL_SEQ);
|
||||
tmp->set_line(*this);
|
||||
vector<Statement*>tmp_list(1);
|
||||
tmp_list[0] = statement_;
|
||||
tmp->set_statement(tmp_list);
|
||||
|
||||
statement_ = tmp;
|
||||
blk = tmp;
|
||||
}
|
||||
|
||||
// Now do the push.
|
||||
blk->push_statement_front(stmt);
|
||||
}
|
||||
|
||||
void PFunction::set_return(data_type_t*t)
|
||||
{
|
||||
return_type_ = t;
|
||||
}
|
||||
|
||||
PChainConstructor* PFunction::extract_chain_constructor()
|
||||
{
|
||||
PChainConstructor*res = 0;
|
||||
|
||||
if ((res = dynamic_cast<PChainConstructor*> (statement_))) {
|
||||
statement_ = new PBlock(PBlock::BL_SEQ);
|
||||
statement_->set_line(*this);
|
||||
|
||||
} else if (PBlock*blk = dynamic_cast<PBlock*>(statement_)) {
|
||||
res = blk->extract_chain_constructor();
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PFunction::symbol_type() const
|
||||
{
|
||||
return FUNCTION;
|
||||
}
|
||||
@@ -1,316 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1999-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "PGate.h"
|
||||
# include "PExpr.h"
|
||||
# include "verinum.h"
|
||||
# include <cassert>
|
||||
|
||||
void PGate::set_pins_(list<PExpr*>*pins)
|
||||
{
|
||||
assert(pins);
|
||||
assert(pins->size() == pins_.size());
|
||||
|
||||
for (size_t idx = 0 ; idx < pins_.size() ; idx += 1) {
|
||||
pins_[idx] = pins->front();
|
||||
pins->pop_front();
|
||||
}
|
||||
|
||||
assert(pins->empty());
|
||||
delete pins;
|
||||
}
|
||||
|
||||
PGate::PGate(perm_string name, list<PExpr*>*pins, const list<PExpr*>*del)
|
||||
: name_(name), pins_(pins? pins->size() : 0)
|
||||
{
|
||||
if (pins) set_pins_(pins);
|
||||
if (del) delay_.set_delays(del);
|
||||
str0_ = IVL_DR_STRONG;
|
||||
str1_ = IVL_DR_STRONG;
|
||||
}
|
||||
|
||||
PGate::PGate(perm_string name, list<PExpr*>*pins, PExpr*del)
|
||||
: name_(name), pins_(pins? pins->size() : 0)
|
||||
{
|
||||
if (pins) set_pins_(pins);
|
||||
if (del) delay_.set_delay(del);
|
||||
str0_ = IVL_DR_STRONG;
|
||||
str1_ = IVL_DR_STRONG;
|
||||
}
|
||||
|
||||
PGate::PGate(perm_string name, list<PExpr*>*pins)
|
||||
: name_(name), pins_(pins? pins->size() : 0)
|
||||
{
|
||||
if (pins) set_pins_(pins);
|
||||
str0_ = IVL_DR_STRONG;
|
||||
str1_ = IVL_DR_STRONG;
|
||||
}
|
||||
|
||||
PGate::~PGate()
|
||||
{
|
||||
}
|
||||
|
||||
ivl_drive_t PGate::strength0() const
|
||||
{
|
||||
return str0_;
|
||||
}
|
||||
|
||||
void PGate::strength0(ivl_drive_t s)
|
||||
{
|
||||
str0_ = s;
|
||||
}
|
||||
|
||||
ivl_drive_t PGate::strength1() const
|
||||
{
|
||||
return str1_;
|
||||
}
|
||||
|
||||
void PGate::strength1(ivl_drive_t s)
|
||||
{
|
||||
str1_ = s;
|
||||
}
|
||||
|
||||
void PGate::elaborate_scope(Design*, NetScope*) const
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* This method is used during elaboration to calculate the
|
||||
* rise/fall/decay times for the gate. These values were set in pform
|
||||
* by the constructor, so here I evaluate the expression in the given
|
||||
* design context and save the calculated delays into the output
|
||||
* parameters. This method understands how to handle the different
|
||||
* numbers of expressions.
|
||||
*/
|
||||
|
||||
void PGate::eval_delays(Design*des, NetScope*scope,
|
||||
NetExpr*&rise_expr,
|
||||
NetExpr*&fall_expr,
|
||||
NetExpr*&decay_expr,
|
||||
bool as_net_flag) const
|
||||
{
|
||||
delay_.eval_delays(des, scope,
|
||||
rise_expr, fall_expr, decay_expr,
|
||||
as_net_flag);
|
||||
}
|
||||
|
||||
unsigned PGate::delay_count() const
|
||||
{
|
||||
return delay_.delay_count();
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PGate::symbol_type() const
|
||||
{
|
||||
return INSTANCE;
|
||||
}
|
||||
|
||||
PGAssign::PGAssign(list<PExpr*>*pins)
|
||||
: PGate(perm_string(), pins)
|
||||
{
|
||||
assert(pin_count() == 2);
|
||||
}
|
||||
|
||||
PGAssign::PGAssign(list<PExpr*>*pins, list<PExpr*>*dels)
|
||||
: PGate(perm_string(), pins, dels)
|
||||
{
|
||||
assert(pin_count() == 2);
|
||||
}
|
||||
|
||||
PGAssign::~PGAssign()
|
||||
{
|
||||
}
|
||||
|
||||
PGBuiltin::PGBuiltin(Type t, perm_string name,
|
||||
list<PExpr*>*pins,
|
||||
list<PExpr*>*del)
|
||||
: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PGBuiltin::PGBuiltin(Type t, perm_string name,
|
||||
list<PExpr*>*pins,
|
||||
PExpr*del)
|
||||
: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
PGBuiltin::~PGBuiltin()
|
||||
{
|
||||
}
|
||||
|
||||
void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
|
||||
{
|
||||
assert(msb_ == 0);
|
||||
assert(lsb_ == 0);
|
||||
|
||||
msb_ = msb;
|
||||
lsb_ = lsb;
|
||||
}
|
||||
|
||||
const char* PGBuiltin::gate_name() const
|
||||
{
|
||||
switch(type_) {
|
||||
case AND:
|
||||
return "AND";
|
||||
break;
|
||||
case NAND:
|
||||
return "NAND";
|
||||
break;
|
||||
|
||||
case OR:
|
||||
return "OR";
|
||||
break;
|
||||
case NOR:
|
||||
return "NOR";
|
||||
break;
|
||||
|
||||
case XOR:
|
||||
return "XOR";
|
||||
break;
|
||||
case XNOR:
|
||||
return "XNOR";
|
||||
break;
|
||||
|
||||
case BUF:
|
||||
return "BUF";
|
||||
break;
|
||||
case NOT:
|
||||
return "NOT";
|
||||
break;
|
||||
|
||||
case BUFIF0:
|
||||
return "BUFIF0";
|
||||
break;
|
||||
case NOTIF0:
|
||||
return "NOTIF0";
|
||||
break;
|
||||
|
||||
case BUFIF1:
|
||||
return "BUFIF1";
|
||||
break;
|
||||
case NOTIF1:
|
||||
return "NOTIF1";
|
||||
break;
|
||||
|
||||
case NMOS:
|
||||
return "NMOS";
|
||||
break;
|
||||
case RNMOS:
|
||||
return "RNMOS";
|
||||
break;
|
||||
|
||||
case PMOS:
|
||||
return "PMOS";
|
||||
break;
|
||||
case RPMOS:
|
||||
return "RPMOS";
|
||||
break;
|
||||
|
||||
case TRAN:
|
||||
return "TRAN";
|
||||
break;
|
||||
case RTRAN:
|
||||
return "RTRAN";
|
||||
break;
|
||||
|
||||
case TRANIF0:
|
||||
return "TRANIF0";
|
||||
break;
|
||||
case RTRANIF0:
|
||||
return "RTRANIF0";
|
||||
break;
|
||||
|
||||
case TRANIF1:
|
||||
return "TRANIF1";
|
||||
break;
|
||||
case RTRANIF1:
|
||||
return "RTRANIF1";
|
||||
break;
|
||||
|
||||
case CMOS:
|
||||
return "CMOS";
|
||||
break;
|
||||
case RCMOS:
|
||||
return "RCMOS";
|
||||
break;
|
||||
|
||||
case PULLUP:
|
||||
return "PULLUP";
|
||||
break;
|
||||
case PULLDOWN:
|
||||
return "PULLDOWN";
|
||||
break;
|
||||
}
|
||||
|
||||
return "<unknown>";
|
||||
}
|
||||
|
||||
PGModule::PGModule(perm_string type, perm_string name, list<PExpr*>*pins)
|
||||
: PGate(name, pins), bound_type_(0), type_(type), overrides_(0), pins_(0),
|
||||
npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PGModule::PGModule(perm_string type, perm_string name,
|
||||
named<PExpr*>*pins, unsigned npins)
|
||||
: PGate(name, 0), bound_type_(0), type_(type), overrides_(0), pins_(pins),
|
||||
npins_(npins), parms_(0), nparms_(0), msb_(0), lsb_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PGModule::PGModule(Module*type, perm_string name)
|
||||
: PGate(name, 0), bound_type_(type), overrides_(0), pins_(0),
|
||||
npins_(0), parms_(0), nparms_(0), msb_(0), lsb_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PGModule::~PGModule()
|
||||
{
|
||||
}
|
||||
|
||||
void PGModule::set_parameters(list<PExpr*>*o)
|
||||
{
|
||||
assert(overrides_ == 0);
|
||||
overrides_ = o;
|
||||
}
|
||||
|
||||
void PGModule::set_parameters(named<PExpr*>*pa, unsigned npa)
|
||||
{
|
||||
assert(parms_ == 0);
|
||||
assert(overrides_ == 0);
|
||||
parms_ = pa;
|
||||
nparms_ = npa;
|
||||
}
|
||||
|
||||
void PGModule::set_range(PExpr*msb, PExpr*lsb)
|
||||
{
|
||||
assert(msb_ == 0);
|
||||
assert(lsb_ == 0);
|
||||
|
||||
msb_ = msb;
|
||||
lsb_ = lsb;
|
||||
}
|
||||
|
||||
perm_string PGModule::get_type() const
|
||||
{
|
||||
return type_;
|
||||
}
|
||||
@@ -1,267 +0,0 @@
|
||||
#ifndef IVL_PGate_H
|
||||
#define IVL_PGate_H
|
||||
/*
|
||||
* Copyright (c) 1998-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "svector.h"
|
||||
# include "StringHeap.h"
|
||||
# include "named.h"
|
||||
# include "PNamedItem.h"
|
||||
# include "PDelays.h"
|
||||
# include "netlist.h"
|
||||
# include <map>
|
||||
# include <list>
|
||||
# include <vector>
|
||||
# include <string>
|
||||
class PExpr;
|
||||
class PUdp;
|
||||
class Module;
|
||||
|
||||
/*
|
||||
* A PGate represents a Verilog gate. The gate has a name and other
|
||||
* properties, and a set of pins that connect to wires. It is known at
|
||||
* the time a gate is constructed how many pins the gate has.
|
||||
*
|
||||
* This pins of a gate are connected to expressions. The elaboration
|
||||
* step will need to convert expressions to a network of gates in
|
||||
* order to elaborate expression inputs, but that can easily be done.
|
||||
*
|
||||
* The PGate base class also carries the strength0 and strength1
|
||||
* strengths for those gates where the driver[s] can be described by a
|
||||
* single strength pair. There is a strength of the 0 drive, and a
|
||||
* strength of the 1 drive.
|
||||
*/
|
||||
class PGate : public PNamedItem {
|
||||
|
||||
public:
|
||||
explicit PGate(perm_string name, list<PExpr*>*pins,
|
||||
const list<PExpr*>*del);
|
||||
|
||||
explicit PGate(perm_string name, list<PExpr*>*pins,
|
||||
PExpr*del);
|
||||
|
||||
explicit PGate(perm_string name, list<PExpr*>*pins);
|
||||
|
||||
virtual ~PGate();
|
||||
|
||||
perm_string get_name() const { return name_; }
|
||||
|
||||
// This evaluates the delays as far as possible, but returns
|
||||
// an expression, and do not signal errors.
|
||||
void eval_delays(Design*des, NetScope*scope,
|
||||
NetExpr*&rise_time,
|
||||
NetExpr*&fall_time,
|
||||
NetExpr*&decay_time,
|
||||
bool as_net_flag =false) const;
|
||||
|
||||
unsigned delay_count() const;
|
||||
|
||||
unsigned pin_count() const { return pins_.size(); }
|
||||
PExpr*pin(unsigned idx) const { return pins_[idx]; }
|
||||
|
||||
ivl_drive_t strength0() const;
|
||||
ivl_drive_t strength1() const;
|
||||
|
||||
void strength0(ivl_drive_t);
|
||||
void strength1(ivl_drive_t);
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind =4) const;
|
||||
virtual void elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*sc) const;
|
||||
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
protected:
|
||||
const vector<PExpr*>& get_pins() const { return pins_; }
|
||||
|
||||
void dump_pins(ostream&out) const;
|
||||
void dump_delays(ostream&out) const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
PDelays delay_;
|
||||
vector<PExpr*>pins_;
|
||||
|
||||
ivl_drive_t str0_, str1_;
|
||||
|
||||
void set_pins_(list<PExpr*>*pins);
|
||||
|
||||
private: // not implemented
|
||||
PGate(const PGate&);
|
||||
PGate& operator= (const PGate&);
|
||||
};
|
||||
|
||||
/* A continuous assignment has a single output and a single input. The
|
||||
input is passed directly to the output. This is different from a
|
||||
BUF because elaboration may need to turn this into a vector of
|
||||
gates. */
|
||||
class PGAssign : public PGate {
|
||||
|
||||
public:
|
||||
explicit PGAssign(list<PExpr*>*pins);
|
||||
explicit PGAssign(list<PExpr*>*pins, list<PExpr*>*dels);
|
||||
~PGAssign();
|
||||
|
||||
void dump(ostream&out, unsigned ind =4) const;
|
||||
virtual void elaborate(Design*des, NetScope*scope) const;
|
||||
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
void elaborate_unpacked_array_(Design*des, NetScope*scope, NetNet*lval) const;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* The Builtin class is specifically a gate with one of the builtin
|
||||
* types. The parser recognizes these types during parse. These types
|
||||
* have special properties that allow them to be treated specially.
|
||||
*
|
||||
* A PGBuiltin can be grouped into an array of devices. If this is
|
||||
* done, the msb_ and lsb_ are set to the indices of the array
|
||||
* range. Elaboration causes a gate to be created for each element of
|
||||
* the array, and a name will be generated for each gate.
|
||||
*/
|
||||
class PGBuiltin : public PGate {
|
||||
|
||||
public:
|
||||
enum Type { AND, NAND, OR, NOR, XOR, XNOR, BUF, BUFIF0, BUFIF1,
|
||||
NOT, NOTIF0, NOTIF1, PULLDOWN, PULLUP, NMOS, RNMOS,
|
||||
PMOS, RPMOS, CMOS, RCMOS, TRAN, RTRAN, TRANIF0,
|
||||
TRANIF1, RTRANIF0, RTRANIF1 };
|
||||
|
||||
public:
|
||||
explicit PGBuiltin(Type t, perm_string name,
|
||||
list<PExpr*>*pins,
|
||||
list<PExpr*>*del);
|
||||
explicit PGBuiltin(Type t, perm_string name,
|
||||
list<PExpr*>*pins,
|
||||
PExpr*del);
|
||||
~PGBuiltin();
|
||||
|
||||
Type type() const { return type_; }
|
||||
const char * gate_name() const;
|
||||
void set_range(PExpr*msb, PExpr*lsb);
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind =4) const;
|
||||
virtual void elaborate(Design*, NetScope*scope) const;
|
||||
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
unsigned calculate_array_count_(Design*, NetScope*,
|
||||
long&high, long&low) const;
|
||||
|
||||
void calculate_gate_and_lval_count_(unsigned&gate_count,
|
||||
unsigned&lval_count) const;
|
||||
|
||||
NetNode* create_gate_for_output_(Design*, NetScope*,
|
||||
perm_string gate_name,
|
||||
unsigned instance_width) const;
|
||||
|
||||
bool check_delay_count(Design*des) const;
|
||||
|
||||
Type type_;
|
||||
PExpr*msb_;
|
||||
PExpr*lsb_;
|
||||
};
|
||||
|
||||
/*
|
||||
* This kind of gate is an instantiation of a module. The stored type
|
||||
* is the name of a module definition somewhere in the pform. This
|
||||
* type also handles UDP devices, because it is generally not known at
|
||||
* parse time whether a name belongs to a module or a UDP.
|
||||
*/
|
||||
class PGModule : public PGate {
|
||||
|
||||
public:
|
||||
// The name is the *instance* name of the gate.
|
||||
|
||||
// If the binding of ports is by position, this constructor
|
||||
// builds everything all at once.
|
||||
explicit PGModule(perm_string type, perm_string name,
|
||||
list<PExpr*>*pins);
|
||||
|
||||
// If the binding of ports is by name, this constructor takes
|
||||
// the bindings and stores them for later elaboration.
|
||||
explicit PGModule(perm_string type, perm_string name,
|
||||
named<PExpr*>*pins, unsigned npins);
|
||||
|
||||
// If the module type is known by design, then use this
|
||||
// constructor.
|
||||
explicit PGModule(Module*type, perm_string name);
|
||||
|
||||
~PGModule();
|
||||
|
||||
// Parameter overrides can come as an ordered list, or a set
|
||||
// of named expressions.
|
||||
void set_parameters(list<PExpr*>*o);
|
||||
void set_parameters(named<PExpr*>*pa, unsigned npa);
|
||||
|
||||
// Modules can be instantiated in ranges. The parser uses this
|
||||
// method to pass the range to the pform.
|
||||
void set_range(PExpr*msb, PExpr*lsb);
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind =4) const;
|
||||
virtual void elaborate(Design*, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*sc) const;
|
||||
virtual bool elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
// This returns the module name of this module. It is a
|
||||
// permallocated string.
|
||||
perm_string get_type() const;
|
||||
|
||||
private:
|
||||
Module*bound_type_;
|
||||
perm_string type_;
|
||||
list<PExpr*>*overrides_;
|
||||
named<PExpr*>*pins_;
|
||||
unsigned npins_;
|
||||
|
||||
// These members support parameter override by name
|
||||
named<PExpr*>*parms_;
|
||||
unsigned nparms_;
|
||||
|
||||
// Arrays of modules are give if these are set.
|
||||
PExpr*msb_;
|
||||
PExpr*lsb_;
|
||||
|
||||
friend class delayed_elaborate_scope_mod_instances;
|
||||
void elaborate_mod_(Design*, Module*mod, NetScope*scope) const;
|
||||
void elaborate_udp_(Design*, PUdp *udp, NetScope*scope) const;
|
||||
unsigned calculate_instance_count_(Design*, NetScope*,
|
||||
long&high, long&low,
|
||||
perm_string name) const;
|
||||
void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
|
||||
void elaborate_scope_mod_instances_(Design*des, Module*mod, NetScope*sc) const;
|
||||
bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
|
||||
// Not currently used.
|
||||
#if 0
|
||||
bool elaborate_sig_udp_(Design*des, NetScope*scope, PUdp*udp) const;
|
||||
#endif
|
||||
|
||||
NetNet*resize_net_to_port_(Design*des, NetScope*scope,
|
||||
NetNet*sig, unsigned port_wid,
|
||||
NetNet::PortType dir, bool as_signed) const;
|
||||
};
|
||||
|
||||
#endif /* IVL_PGate_H */
|
||||
-120
@@ -1,120 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2020 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PGenerate.h"
|
||||
# include "PWire.h"
|
||||
# include "ivl_assert.h"
|
||||
|
||||
PGenerate::PGenerate(LexicalScope*parent, unsigned id)
|
||||
: LexicalScope(parent), id_number(id)
|
||||
{
|
||||
direct_nested_ = false;
|
||||
scheme_type = GS_NONE;
|
||||
local_index = false;
|
||||
loop_init = 0;
|
||||
loop_test = 0;
|
||||
loop_step = 0;
|
||||
}
|
||||
|
||||
PGenerate::~PGenerate()
|
||||
{
|
||||
}
|
||||
|
||||
void PGenerate::add_gate(PGate*gate)
|
||||
{
|
||||
gates.push_back(gate);
|
||||
}
|
||||
|
||||
void PGenerate::probe_for_direct_nesting_(void)
|
||||
{
|
||||
direct_nested_ = false;
|
||||
|
||||
ivl_assert(*this, scheme_type==GS_CASE_ITEM || scheme_type==GS_CONDIT || scheme_type==GS_ELSE);
|
||||
|
||||
// If this scheme has received an explicit name, then it
|
||||
// cannot be direct nested.
|
||||
if (scope_name[0] != '$') return;
|
||||
|
||||
if (! tasks.empty()) return;
|
||||
if (! funcs.empty()) return;
|
||||
if (! gates.empty()) return;
|
||||
if (! parameters.empty()) return;
|
||||
if (! localparams.empty()) return;
|
||||
if (! events.empty()) return;
|
||||
if (! wires.empty()) return;
|
||||
if (! genvars.empty()) return;
|
||||
if (! behaviors.empty()) return;
|
||||
if (! analog_behaviors.empty()) return;
|
||||
|
||||
if (generate_schemes.empty()) return;
|
||||
|
||||
switch (generate_schemes.size()) {
|
||||
case 1: {
|
||||
PGenerate*child = generate_schemes.front();
|
||||
if (child->scheme_type == GS_CONDIT)
|
||||
direct_nested_ = true;
|
||||
if (child->scheme_type == GS_CASE)
|
||||
direct_nested_ = true;
|
||||
break;
|
||||
}
|
||||
|
||||
case 2: {
|
||||
PGenerate*child1 = generate_schemes.front();
|
||||
PGenerate*child2 = generate_schemes.back();
|
||||
if (child1->scheme_type==GS_CONDIT && child2->scheme_type==GS_ELSE)
|
||||
direct_nested_ = true;
|
||||
if (child2->scheme_type==GS_CONDIT && child1->scheme_type==GS_ELSE)
|
||||
direct_nested_ = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ostream& operator << (ostream&out, PGenerate::scheme_t type)
|
||||
{
|
||||
switch (type) {
|
||||
case PGenerate::GS_NONE:
|
||||
out << "GS_NONE";
|
||||
break;
|
||||
case PGenerate::GS_LOOP:
|
||||
out << "GS_LOOP";
|
||||
break;
|
||||
case PGenerate::GS_CONDIT:
|
||||
out << "GS_CONDIT";
|
||||
break;
|
||||
case PGenerate::GS_ELSE:
|
||||
out << "GS_ELSE";
|
||||
break;
|
||||
case PGenerate::GS_CASE:
|
||||
out << "GS_CASE";
|
||||
break;
|
||||
case PGenerate::GS_CASE_ITEM:
|
||||
out << "GS_CASE_ITEM";
|
||||
break;
|
||||
case PGenerate::GS_NBLOCK:
|
||||
out << "GS_NBLOCK";
|
||||
break;
|
||||
}
|
||||
return out;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PGenerate::symbol_type() const
|
||||
{
|
||||
return GENBLOCK;
|
||||
}
|
||||
-147
@@ -1,147 +0,0 @@
|
||||
#ifndef IVL_PGenerate_H
|
||||
#define IVL_PGenerate_H
|
||||
/*
|
||||
* Copyright (c) 2006-2020 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PNamedItem.h"
|
||||
# include "StringHeap.h"
|
||||
# include "HName.h"
|
||||
# include "PScope.h"
|
||||
# include <list>
|
||||
# include <map>
|
||||
# include <valarray>
|
||||
# include "pform_types.h"
|
||||
|
||||
class Design;
|
||||
class NetScope;
|
||||
class PExpr;
|
||||
class PFunction;
|
||||
class PProcess;
|
||||
class PTask;
|
||||
class PGate;
|
||||
class PWire;
|
||||
|
||||
/*
|
||||
* This represents a generate scheme. The interpretation of the
|
||||
* members depends on the scheme_type.
|
||||
*
|
||||
* GS_LOOP
|
||||
*
|
||||
* GS_CASE
|
||||
* loop_test is the expression to be compared.
|
||||
* generates contains only GS_CASE_ITEM schemes.
|
||||
* GS_CASE_ITEM
|
||||
* The parent points to the GS_CASE that contains this item.
|
||||
* the loop_test is compared with the parent->loop_test expression.
|
||||
*/
|
||||
class PGenerate : public PNamedItem, public LexicalScope {
|
||||
|
||||
public:
|
||||
explicit PGenerate(LexicalScope*parent, unsigned id_number);
|
||||
~PGenerate();
|
||||
|
||||
// Generate schemes have an ID number, for when the scope is
|
||||
// implicit.
|
||||
const unsigned id_number;
|
||||
perm_string scope_name;
|
||||
|
||||
// This is used during parsing to stack lexical scopes within
|
||||
// this generate scheme.
|
||||
// LexicalScope*lexical_scope;
|
||||
|
||||
enum scheme_t {GS_NONE, GS_LOOP, GS_CONDIT, GS_ELSE,
|
||||
GS_CASE, GS_CASE_ITEM, GS_NBLOCK};
|
||||
scheme_t scheme_type;
|
||||
|
||||
// generate loops have an index variable and three
|
||||
// expressions: for (index = <init>; <test>; index=<step>)
|
||||
// the index is local if it was declared in the init expression,
|
||||
// e.g. for (genvar index = <init>; <test>; index=<step>)
|
||||
bool local_index;
|
||||
perm_string loop_index;
|
||||
PExpr*loop_init;
|
||||
PExpr*loop_test;
|
||||
PExpr*loop_step;
|
||||
// Case items may have multiple guard expression values. It is
|
||||
// enough for any on of the guards to match the case statement
|
||||
// test value.
|
||||
std::valarray<PExpr*> item_test;
|
||||
|
||||
// defparam assignments found in this scope.
|
||||
typedef pair<pform_name_t,PExpr*> named_expr_t;
|
||||
list<named_expr_t>defparms;
|
||||
|
||||
list<PGate*> gates;
|
||||
void add_gate(PGate*);
|
||||
|
||||
// Tasks instantiated within this scheme.
|
||||
map<perm_string,PTask*> tasks;
|
||||
map<perm_string,PFunction*>funcs;
|
||||
|
||||
// Generate schemes can contain further generate schemes.
|
||||
list<PGenerate*> generate_schemes;
|
||||
// PGenerate*parent;
|
||||
|
||||
// This method is called by the elaboration of a module to
|
||||
// generate scopes. the container is the scope that is to
|
||||
// contain the generated scope.
|
||||
bool generate_scope(Design*des, NetScope*container);
|
||||
|
||||
// Elaborate signals within any of the generated scopes that
|
||||
// were made by this generate block within the given container scope.
|
||||
bool elaborate_sig(Design*des, NetScope*container) const;
|
||||
bool elaborate(Design*des, NetScope*container) const;
|
||||
|
||||
void dump(ostream&out, unsigned indent) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
bool generate_scope_loop_(Design*des, NetScope*container);
|
||||
bool generate_scope_condit_(Design*des, NetScope*container, bool else_flag);
|
||||
bool generate_scope_case_(Design*des, NetScope*container);
|
||||
bool generate_scope_nblock_(Design*des, NetScope*container);
|
||||
|
||||
// Call probe during elaborate_scope to calculate the
|
||||
// direct_nested_ flag. It is OK to store the direct_nested_
|
||||
// information here because "direct nested" is a property of
|
||||
// the lexical generate code.
|
||||
void probe_for_direct_nesting_(void);
|
||||
bool direct_nested_;
|
||||
|
||||
// Elaborate_scope within a generated scope.
|
||||
void elaborate_subscope_(Design*des, NetScope*scope);
|
||||
void elaborate_subscope_direct_(Design*des, NetScope*scope);
|
||||
|
||||
// These are the scopes created by generate_scope.
|
||||
list<NetScope*>scope_list_;
|
||||
// internal function called on each scope generated by this scheme.
|
||||
bool elaborate_sig_(Design*des, NetScope*scope) const;
|
||||
bool elaborate_sig_direct_(Design*des, NetScope*scope) const;
|
||||
bool elaborate_(Design*des, NetScope*scope) const;
|
||||
bool elaborate_direct_(Design*des, NetScope*scope) const;
|
||||
|
||||
private: // not implemented
|
||||
PGenerate(const PGenerate&);
|
||||
PGenerate& operator= (const PGenerate&);
|
||||
};
|
||||
|
||||
extern std::ostream& operator << (std::ostream&, PGenerate::scheme_t);
|
||||
|
||||
#endif /* IVL_PGenerate_H */
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "PModport.h"
|
||||
|
||||
PModport::PModport(perm_string n)
|
||||
: name_(n)
|
||||
{
|
||||
}
|
||||
|
||||
PModport::~PModport()
|
||||
{
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PModport::symbol_type() const
|
||||
{
|
||||
return MODPORT;
|
||||
}
|
||||
-54
@@ -1,54 +0,0 @@
|
||||
#ifndef IVL_PModport_H
|
||||
#define IVL_PModport_H
|
||||
/*
|
||||
* Copyright (c) 2015-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PNamedItem.h"
|
||||
# include "PScope.h"
|
||||
# include "StringHeap.h"
|
||||
# include "netlist.h"
|
||||
# include <vector>
|
||||
|
||||
/*
|
||||
* The PModport class represents a parsed SystemVerilog modport list.
|
||||
*/
|
||||
class PModport : public PNamedItem {
|
||||
|
||||
public:
|
||||
// The name is a perm-allocated string. It is the simple name
|
||||
// of the modport, without any scope.
|
||||
explicit PModport(perm_string name);
|
||||
~PModport();
|
||||
|
||||
perm_string name() const { return name_; }
|
||||
|
||||
typedef pair <NetNet::PortType,PExpr*> simple_port_t;
|
||||
map<perm_string,simple_port_t> simple_ports;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
|
||||
private: // not implemented
|
||||
PModport(const PModport&);
|
||||
PModport& operator= (const PModport&);
|
||||
};
|
||||
|
||||
#endif /* IVL_PModport_H */
|
||||
-116
@@ -1,116 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Martin Whitaker ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PNamedItem.h"
|
||||
# include <ostream>
|
||||
|
||||
PNamedItem::PNamedItem()
|
||||
{
|
||||
}
|
||||
|
||||
PNamedItem::~PNamedItem()
|
||||
{
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PNamedItem::symbol_type() const
|
||||
{
|
||||
return ANY;
|
||||
}
|
||||
|
||||
std::ostream& operator << (std::ostream&o, PNamedItem::SymbolType st)
|
||||
{
|
||||
switch (st) {
|
||||
case PNamedItem::ANY:
|
||||
o << "a symbol";
|
||||
break;
|
||||
case PNamedItem::PARAM:
|
||||
o << "a parameter";
|
||||
break;
|
||||
case PNamedItem::NET:
|
||||
o << "a net";
|
||||
break;
|
||||
case PNamedItem::VAR:
|
||||
o << "a variable";
|
||||
break;
|
||||
case PNamedItem::GENVAR:
|
||||
o << "a genvar";
|
||||
break;
|
||||
case PNamedItem::EVENT:
|
||||
o << "an event";
|
||||
break;
|
||||
case PNamedItem::TYPE:
|
||||
o << "a type";
|
||||
break;
|
||||
case PNamedItem::ENUM:
|
||||
o << "an enum type or value";
|
||||
break;
|
||||
case PNamedItem::CLASS:
|
||||
o << "a class";
|
||||
break;
|
||||
case PNamedItem::FUNCTION:
|
||||
o << "a function";
|
||||
break;
|
||||
case PNamedItem::TASK:
|
||||
o << "a task";
|
||||
break;
|
||||
case PNamedItem::BLOCK:
|
||||
o << "a named block";
|
||||
break;
|
||||
case PNamedItem::GENBLOCK:
|
||||
o << "a generate block";
|
||||
break;
|
||||
case PNamedItem::MODPORT:
|
||||
o << "a modport";
|
||||
break;
|
||||
case PNamedItem::PACKAGE:
|
||||
o << "a package";
|
||||
break;
|
||||
case PNamedItem::MODULE:
|
||||
o << "a module";
|
||||
break;
|
||||
case PNamedItem::PROGRAM:
|
||||
o << "a program";
|
||||
break;
|
||||
case PNamedItem::INTERFACE:
|
||||
o << "an interface";
|
||||
break;
|
||||
case PNamedItem::PRIMITIVE:
|
||||
o << "a primitive";
|
||||
break;
|
||||
case PNamedItem::INSTANCE:
|
||||
o << "an instance name";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return o;
|
||||
}
|
||||
|
||||
PGenvar::PGenvar()
|
||||
{
|
||||
}
|
||||
|
||||
PGenvar::~PGenvar()
|
||||
{
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PGenvar::symbol_type() const
|
||||
{
|
||||
return GENVAR;
|
||||
}
|
||||
@@ -1,57 +0,0 @@
|
||||
#ifndef IVL_PNamedItem_H
|
||||
#define IVL_PNamedItem_H
|
||||
/*
|
||||
* Copyright (c) 2019 Martin Whitaker ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "LineInfo.h"
|
||||
|
||||
/*
|
||||
* The PNamedItem class is the base class for all items that can be added
|
||||
* to a scope's local symbol map.
|
||||
*/
|
||||
class PNamedItem : virtual public LineInfo {
|
||||
|
||||
public:
|
||||
enum SymbolType { ANY, PARAM, NET, VAR, GENVAR, EVENT, TYPE, ENUM,
|
||||
CLASS, FUNCTION, TASK, BLOCK, GENBLOCK, MODPORT,
|
||||
PACKAGE, MODULE, PROGRAM, INTERFACE, PRIMITIVE,
|
||||
INSTANCE };
|
||||
|
||||
explicit PNamedItem();
|
||||
virtual ~PNamedItem();
|
||||
|
||||
virtual SymbolType symbol_type() const;
|
||||
};
|
||||
|
||||
extern std::ostream& operator << (std::ostream&, PNamedItem::SymbolType);
|
||||
|
||||
/*
|
||||
* The PGenvar class represents a genvar. This is only used to represent
|
||||
* genvar in a scope's local symbol map.
|
||||
*/
|
||||
class PGenvar : public PNamedItem {
|
||||
|
||||
public:
|
||||
explicit PGenvar();
|
||||
virtual ~PGenvar();
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
};
|
||||
|
||||
#endif /* IVL_PNamedItem_H */
|
||||
-30
@@ -1,30 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2012 Stephen Williams ([email protected])
|
||||
* Copyright CERN 2013 / Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PPackage.h"
|
||||
|
||||
PPackage::PPackage(perm_string name, LexicalScope*parent)
|
||||
: PScopeExtra(name, parent)
|
||||
{
|
||||
}
|
||||
|
||||
PPackage::~PPackage()
|
||||
{
|
||||
}
|
||||
-47
@@ -1,47 +0,0 @@
|
||||
#ifndef IVL_PPackage_H
|
||||
#define IVL_PPackage_H
|
||||
/*
|
||||
* Copyright (c) 2012-2014 Stephen Williams ([email protected])
|
||||
* Copyright CERN 2013 / Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PScope.h"
|
||||
# include "LineInfo.h"
|
||||
# include "StringHeap.h"
|
||||
# include <iostream>
|
||||
|
||||
/*
|
||||
* SystemVerilog supports class declarations with their own lexical
|
||||
* scope, etc. The parser arranges for these to be created and
|
||||
* collected.
|
||||
*/
|
||||
|
||||
class PPackage : public PScopeExtra, public LineInfo {
|
||||
|
||||
public:
|
||||
explicit PPackage (perm_string name, LexicalScope*parent);
|
||||
~PPackage();
|
||||
|
||||
bool elaborate_scope(Design*des, NetScope*scope);
|
||||
bool elaborate_sig(Design*des, NetScope*scope) const;
|
||||
bool elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
void pform_dump(std::ostream&out) const;
|
||||
};
|
||||
|
||||
#endif /* IVL_PPackage_H */
|
||||
@@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2008-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PScope.h"
|
||||
|
||||
bool LexicalScope::var_init_needs_explicit_lifetime() const
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
PWire* LexicalScope::wires_find(perm_string name)
|
||||
{
|
||||
map<perm_string,PWire*>::const_iterator cur = wires.find(name);
|
||||
if (cur == wires.end())
|
||||
return 0;
|
||||
else
|
||||
return (*cur).second;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType LexicalScope::param_expr_t::symbol_type() const
|
||||
{
|
||||
return PARAM;
|
||||
}
|
||||
|
||||
PScope::PScope(perm_string n, LexicalScope*parent)
|
||||
: LexicalScope(parent), name_(n)
|
||||
{
|
||||
time_unit = 0;
|
||||
time_precision = 0;
|
||||
time_unit_is_default = true;
|
||||
time_prec_is_default = true;
|
||||
}
|
||||
|
||||
PScope::~PScope()
|
||||
{
|
||||
for(map<perm_string, data_type_t*>::iterator it = typedefs.begin();
|
||||
it != typedefs.end(); ++it)
|
||||
delete it->second;
|
||||
}
|
||||
|
||||
PScopeExtra::PScopeExtra(perm_string n, LexicalScope*parent)
|
||||
: PScope(n, parent)
|
||||
{
|
||||
time_unit_is_local = false;
|
||||
time_prec_is_local = false;
|
||||
}
|
||||
|
||||
PScopeExtra::~PScopeExtra()
|
||||
{
|
||||
}
|
||||
@@ -1,235 +0,0 @@
|
||||
#ifndef IVL_PScope_H
|
||||
#define IVL_PScope_H
|
||||
/*
|
||||
* Copyright (c) 2008-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PNamedItem.h"
|
||||
# include "StringHeap.h"
|
||||
# include "pform_types.h"
|
||||
# include "ivl_target.h"
|
||||
# include <map>
|
||||
# include <set>
|
||||
# include <vector>
|
||||
|
||||
class PEvent;
|
||||
class PExpr;
|
||||
class PFunction;
|
||||
class PPackage;
|
||||
class AProcess;
|
||||
class PProcess;
|
||||
class PClass;
|
||||
class PTask;
|
||||
class PWire;
|
||||
class Statement;
|
||||
|
||||
class Design;
|
||||
class NetScope;
|
||||
|
||||
/*
|
||||
* The PScope class is a base representation of an object that
|
||||
* represents lexical scope. For example, a module, a function/task, a
|
||||
* named block is derived from a PScope.
|
||||
*
|
||||
* NOTE: This is not the same concept as the "scope" of an elaborated
|
||||
* hierarchy. That is represented by NetScope objects after elaboration.
|
||||
*/
|
||||
|
||||
class LexicalScope {
|
||||
|
||||
public:
|
||||
enum lifetime_t { INHERITED, STATIC, AUTOMATIC };
|
||||
|
||||
explicit LexicalScope(LexicalScope*parent) : default_lifetime(INHERITED), parent_(parent) { }
|
||||
// A virtual destructor is so that dynamic_cast can work.
|
||||
virtual ~LexicalScope() { }
|
||||
|
||||
lifetime_t default_lifetime;
|
||||
|
||||
// Symbols that are defined or declared in this scope.
|
||||
std::map<perm_string,PNamedItem*>local_symbols;
|
||||
|
||||
// Symbols that are explicitly imported. Bind the imported name
|
||||
// to the package from which the name is imported.
|
||||
std::map<perm_string,PPackage*>explicit_imports;
|
||||
|
||||
// Packages that are wildcard imported. When identifiers from
|
||||
// these packages are referenced, they will be added to the
|
||||
// explicit imports (IEEE 1800-2012 26.3).
|
||||
std::set<PPackage*>potential_imports;
|
||||
|
||||
// A task or function call may reference a task or function defined
|
||||
// later in the scope. So here we stash the potential imports for
|
||||
// task and function calls. They will be added to the explicit
|
||||
// imports if we don't find a local definition.
|
||||
std::map<perm_string,PPackage*>possible_imports;
|
||||
|
||||
struct range_t {
|
||||
// True if this is an exclude
|
||||
bool exclude_flag;
|
||||
// lower bound
|
||||
// If low_open_flag is false and low_expr=0, then use -inf
|
||||
bool low_open_flag;
|
||||
PExpr*low_expr;
|
||||
// upper bound
|
||||
// If high_open_flag is false and high_expr=0, then use +inf
|
||||
bool high_open_flag;
|
||||
PExpr*high_expr;
|
||||
// Next range description in list
|
||||
struct range_t*next;
|
||||
};
|
||||
|
||||
/* The scope has parameters that are evaluated when the scope
|
||||
is elaborated. During parsing, I put the parameters into
|
||||
this map. */
|
||||
struct param_expr_t : public PNamedItem {
|
||||
param_expr_t() : type(IVL_VT_NO_TYPE), msb(0), lsb(0), signed_flag(false), expr(0), range(0) { }
|
||||
// Type information
|
||||
ivl_variable_type_t type;
|
||||
PExpr*msb;
|
||||
PExpr*lsb;
|
||||
bool signed_flag;
|
||||
// Value expression
|
||||
PExpr*expr;
|
||||
// If there are range constraints, list them here
|
||||
range_t*range;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
};
|
||||
map<perm_string,param_expr_t*>parameters;
|
||||
map<perm_string,param_expr_t*>localparams;
|
||||
|
||||
// Defined types in the scope.
|
||||
map<perm_string,data_type_t*>typedefs;
|
||||
|
||||
// Named events in the scope.
|
||||
map<perm_string,PEvent*>events;
|
||||
|
||||
// Nets and variables (wires) in the scope
|
||||
map<perm_string,PWire*>wires;
|
||||
PWire* wires_find(perm_string name);
|
||||
|
||||
// Genvars in the scope. These will only be present in module
|
||||
// scopes, but are listed here to allow them to be found when
|
||||
// creating implicit nets.
|
||||
map<perm_string,LineInfo*> genvars;
|
||||
|
||||
// Variable initializations in this scope
|
||||
vector<Statement*> var_inits;
|
||||
|
||||
// Behaviors (processes) in this scope
|
||||
list<PProcess*> behaviors;
|
||||
list<AProcess*> analog_behaviors;
|
||||
|
||||
// Enumeration sets.
|
||||
std::set<enum_type_t*> enum_sets;
|
||||
|
||||
LexicalScope* parent_scope() const { return parent_; }
|
||||
|
||||
virtual bool var_init_needs_explicit_lifetime() const;
|
||||
|
||||
protected:
|
||||
void dump_typedefs_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_parameters_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_localparams_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_enumerations_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_events_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_wires_(ostream&out, unsigned indent) const;
|
||||
|
||||
void dump_var_inits_(ostream&out, unsigned indent) const;
|
||||
|
||||
bool elaborate_var_inits_(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
LexicalScope*parent_;
|
||||
};
|
||||
|
||||
class PScope : public LexicalScope {
|
||||
|
||||
public:
|
||||
// When created, a scope has a name and a parent. The name is
|
||||
// the name of the definition. For example, if this is a
|
||||
// module declaration, the name is the name after the "module"
|
||||
// keyword, and if this is a task scope, the name is the task
|
||||
// name. The parent is the lexical parent of this scope. Since
|
||||
// modules do not nest in Verilog, the parent must be nil for
|
||||
// modules. Scopes for tasks and functions point to their
|
||||
// containing module.
|
||||
explicit PScope(perm_string name, LexicalScope*parent =0);
|
||||
virtual ~PScope();
|
||||
|
||||
perm_string pscope_name() const { return name_; }
|
||||
|
||||
/* These are the timescale for this scope. The value is
|
||||
set by the `timescale directive or, in SystemVerilog,
|
||||
by timeunit and timeprecision statements. */
|
||||
int time_unit, time_precision;
|
||||
|
||||
/* Flags used to support warnings about timescales. */
|
||||
bool time_unit_is_default;
|
||||
bool time_prec_is_default;
|
||||
|
||||
bool has_explicit_timescale() const {
|
||||
return !(time_unit_is_default || time_prec_is_default);
|
||||
}
|
||||
|
||||
protected:
|
||||
bool elaborate_sig_wires_(Design*des, NetScope*scope) const;
|
||||
|
||||
bool elaborate_behaviors_(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
};
|
||||
|
||||
/*
|
||||
* Some scopes can carry definitions. These include Modules and PClass
|
||||
* scopes. These derive from PScopeExtra so that they hold the maps of
|
||||
* extra definitions.
|
||||
*/
|
||||
class PScopeExtra : public PScope {
|
||||
|
||||
public:
|
||||
explicit PScopeExtra(perm_string, LexicalScope*parent =0);
|
||||
~PScopeExtra();
|
||||
|
||||
/* Task definitions within this module */
|
||||
std::map<perm_string,PTask*> tasks;
|
||||
std::map<perm_string,PFunction*> funcs;
|
||||
/* Class definitions within this module. */
|
||||
std::map<perm_string,PClass*> classes;
|
||||
/* This is the lexical order of the classes, and is used by
|
||||
elaboration to choose an elaboration order. */
|
||||
std::vector<PClass*> classes_lexical;
|
||||
|
||||
/* Flags used to support warnings about timescales. */
|
||||
bool time_unit_is_local;
|
||||
bool time_prec_is_local;
|
||||
|
||||
protected:
|
||||
void dump_classes_(ostream&out, unsigned indent) const;
|
||||
void dump_tasks_(ostream&out, unsigned indent) const;
|
||||
void dump_funcs_(ostream&out, unsigned indent) const;
|
||||
};
|
||||
|
||||
#endif /* IVL_PScope_H */
|
||||
@@ -1,34 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2011 Stephen Williams <[email protected]>
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PSpec.h"
|
||||
|
||||
PSpecPath::PSpecPath(unsigned src_cnt, unsigned dst_cnt, char polarity,
|
||||
bool full_flag)
|
||||
: conditional(false), condition(0), edge(0),
|
||||
src(src_cnt), dst(dst_cnt),
|
||||
data_source_expression(0)
|
||||
{
|
||||
full_flag_ = full_flag;
|
||||
polarity_ = polarity;
|
||||
}
|
||||
|
||||
PSpecPath::~PSpecPath()
|
||||
{
|
||||
}
|
||||
@@ -1,87 +0,0 @@
|
||||
#ifndef IVL_PSpec_H
|
||||
#define IVL_PSpec_H
|
||||
/*
|
||||
* Copyright (c) 2006-2014 Stephen Williams <[email protected]>
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "LineInfo.h"
|
||||
# include "StringHeap.h"
|
||||
# include <vector>
|
||||
|
||||
class PExpr;
|
||||
|
||||
/*
|
||||
* The PSpecPath is the parse of a specify path, which is in its most
|
||||
* general form <path> = <delays>. The <delays> are collected into the
|
||||
* "delays" vector in all cases, and the variety is in the other
|
||||
* members.
|
||||
*
|
||||
* All paths also have a list of source names in the src vector, and a
|
||||
* list of destination names in the dst vector. These pairs are the
|
||||
* actual paths.
|
||||
*
|
||||
* If the path is a simple path, then:
|
||||
* condition == nil
|
||||
* edge == 0
|
||||
* data_source_expression == nil
|
||||
*
|
||||
* If the path is conditional, then conditional == true and condition
|
||||
* is the condition expression. If the condition expression is nil,
|
||||
* then this is an ifnone conditional path.
|
||||
*
|
||||
* If data_source_expression != nil, then the path is edge sensitive
|
||||
* and the edge might not be 0.
|
||||
*
|
||||
* The full flag is used to verify that only vectors of the same size
|
||||
* are used in a parallel connection. Icarus always creates a full
|
||||
* connection between the source and destination. The polarity is for
|
||||
* informational (display) purposes only. The polarity is either '+',
|
||||
* '-' or 0.
|
||||
*/
|
||||
class PSpecPath : public LineInfo {
|
||||
|
||||
public:
|
||||
PSpecPath(unsigned src_cnt, unsigned dst_cnt, char polarity,
|
||||
bool full_flag);
|
||||
~PSpecPath();
|
||||
|
||||
void elaborate(class Design*des, class NetScope*scope) const;
|
||||
|
||||
void dump(std::ostream&out, unsigned ind) const;
|
||||
|
||||
public:
|
||||
// Condition expression, if present.
|
||||
bool conditional;
|
||||
class PExpr* condition;
|
||||
// Edge specification (-1==negedge, 0 = no edge, 1==posedge)
|
||||
int edge;
|
||||
// Is this a full connection.
|
||||
bool full_flag_;
|
||||
// What is the polarity of the connection.
|
||||
char polarity_;
|
||||
// Ordered set of source nodes of a path
|
||||
std::vector<perm_string> src;
|
||||
// Ordered set of destination nodes of a path
|
||||
std::vector<perm_string> dst;
|
||||
// Data source expression
|
||||
class PExpr* data_source_expression;
|
||||
|
||||
std::vector<class PExpr*>delays;
|
||||
};
|
||||
|
||||
#endif /* IVL_PSpec_H */
|
||||
@@ -1,80 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1999-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
# include "PTask.h"
|
||||
# include <cassert>
|
||||
|
||||
PTaskFunc::PTaskFunc(perm_string n, LexicalScope*p)
|
||||
: PScope(n,p), this_type_(0), ports_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PTaskFunc::~PTaskFunc()
|
||||
{
|
||||
}
|
||||
|
||||
bool PTaskFunc::var_init_needs_explicit_lifetime() const
|
||||
{
|
||||
return default_lifetime == STATIC;
|
||||
}
|
||||
|
||||
void PTaskFunc::set_ports(vector<pform_tf_port_t>*p)
|
||||
{
|
||||
assert(ports_ == 0);
|
||||
ports_ = p;
|
||||
}
|
||||
|
||||
void PTaskFunc::set_this(class_type_t*type, PWire*this_wire)
|
||||
{
|
||||
assert(this_type_ == 0);
|
||||
this_type_ = type;
|
||||
|
||||
// Push a synthesis argument that is the "this" value.
|
||||
if (ports_==0)
|
||||
ports_ = new vector<pform_tf_port_t>;
|
||||
|
||||
size_t use_size = ports_->size();
|
||||
ports_->resize(use_size + 1);
|
||||
for (size_t idx = use_size ; idx > 0 ; idx -= 1)
|
||||
ports_->at(idx) = ports_->at(idx-1);
|
||||
|
||||
ports_->at(0) = pform_tf_port_t(this_wire);
|
||||
}
|
||||
|
||||
PTask::PTask(perm_string name, LexicalScope*parent, bool is_auto__)
|
||||
: PTaskFunc(name, parent), statement_(0)
|
||||
{
|
||||
is_auto_ = is_auto__;
|
||||
}
|
||||
|
||||
PTask::~PTask()
|
||||
{
|
||||
}
|
||||
|
||||
void PTask::set_statement(Statement*s)
|
||||
{
|
||||
assert(statement_ == 0);
|
||||
statement_ = s;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PTask::symbol_type() const
|
||||
{
|
||||
return TASK;
|
||||
}
|
||||
@@ -1,161 +0,0 @@
|
||||
#ifndef IVL_PTask_H
|
||||
#define IVL_PTask_H
|
||||
/*
|
||||
* Copyright (c) 1999-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PScope.h"
|
||||
# include "PNamedItem.h"
|
||||
# include "StringHeap.h"
|
||||
# include <string>
|
||||
# include <vector>
|
||||
# include <list>
|
||||
class Design;
|
||||
class NetExpr;
|
||||
class NetNet;
|
||||
class NetScope;
|
||||
class PChainConstructor;
|
||||
class PWire;
|
||||
class Statement;
|
||||
class PExpr;
|
||||
|
||||
|
||||
class PTaskFunc : public PScope, public PNamedItem {
|
||||
|
||||
public:
|
||||
PTaskFunc(perm_string name, LexicalScope*parent);
|
||||
~PTaskFunc();
|
||||
|
||||
bool var_init_needs_explicit_lifetime() const;
|
||||
|
||||
void set_ports(std::vector<pform_tf_port_t>*p);
|
||||
|
||||
void set_this(class_type_t*use_type, PWire*this_wire);
|
||||
|
||||
// If this task is a method of a class, this returns a pointer
|
||||
// to the class type.
|
||||
inline class_type_t* method_of() const { return this_type_; }
|
||||
|
||||
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const =0;
|
||||
virtual void elaborate(Design*des, NetScope*scope) const =0;
|
||||
|
||||
virtual void dump(std::ostream&, unsigned) const =0;
|
||||
|
||||
protected:
|
||||
// Elaborate the ports list. Write into the ports vector the
|
||||
// NetNet pointers for the ports, and write into the pdefs the
|
||||
// default value expressions, if any.
|
||||
void elaborate_sig_ports_(Design*des, NetScope*scope,
|
||||
std::vector<NetNet*>&ports,
|
||||
std::vector<NetExpr*>&pdefs) const;
|
||||
|
||||
void dump_ports_(std::ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
class_type_t*this_type_;
|
||||
std::vector<pform_tf_port_t>*ports_;
|
||||
};
|
||||
|
||||
/*
|
||||
* The PTask holds the parsed definitions of a task.
|
||||
*/
|
||||
class PTask : public PTaskFunc {
|
||||
|
||||
public:
|
||||
explicit PTask(perm_string name, LexicalScope*parent, bool is_auto);
|
||||
~PTask();
|
||||
|
||||
void set_statement(Statement *s);
|
||||
|
||||
// Tasks introduce scope, to need to be handled during the
|
||||
// scope elaboration pass. The scope passed is my scope,
|
||||
// created by the containing scope. I fill it in with stuff if
|
||||
// I need to.
|
||||
void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
|
||||
// Bind the ports to the regs that are the ports.
|
||||
void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
// Elaborate the statement to finish off the task definition.
|
||||
void elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
bool is_auto() const { return is_auto_; };
|
||||
|
||||
void dump(ostream&, unsigned) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
Statement*statement_;
|
||||
bool is_auto_;
|
||||
|
||||
private: // Not implemented
|
||||
PTask(const PTask&);
|
||||
PTask& operator=(const PTask&);
|
||||
};
|
||||
|
||||
/*
|
||||
* The function is similar to a task (in this context) but there is a
|
||||
* single output port and a set of input ports. The output port is the
|
||||
* function return value.
|
||||
*
|
||||
* The output value is not elaborated until elaborate_sig.
|
||||
*/
|
||||
class PFunction : public PTaskFunc {
|
||||
|
||||
public:
|
||||
explicit PFunction(perm_string name, LexicalScope*parent, bool is_auto);
|
||||
~PFunction();
|
||||
|
||||
void set_statement(Statement *s);
|
||||
void set_return(data_type_t*t);
|
||||
|
||||
inline Statement* get_statement() { return statement_; }
|
||||
|
||||
// Push this statement to the front of the existing
|
||||
// definition. If the statement is a simple statement, make a
|
||||
// block to contain the statements.
|
||||
void push_statement_front(Statement*stmt);
|
||||
|
||||
// This is only used if this function is a constructor. In
|
||||
// that case, this method looks for a PChainConstructor in the
|
||||
// statement and extracts it if found.
|
||||
PChainConstructor*extract_chain_constructor();
|
||||
|
||||
void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
|
||||
/* elaborate the ports and return value. */
|
||||
void elaborate_sig(Design *des, NetScope*) const;
|
||||
|
||||
/* Elaborate the behavioral statement. */
|
||||
void elaborate(Design *des, NetScope*) const;
|
||||
|
||||
bool is_auto() const { return is_auto_; };
|
||||
|
||||
void dump(ostream&, unsigned) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
data_type_t* return_type_;
|
||||
Statement *statement_;
|
||||
bool is_auto_;
|
||||
};
|
||||
|
||||
#endif /* IVL_PTask_H */
|
||||
@@ -1,37 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2003-2004 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "PUdp.h"
|
||||
|
||||
PUdp::PUdp(perm_string n, unsigned nports)
|
||||
: ports(nports), sequential(false), initial(verinum::Vx), name_(n)
|
||||
{
|
||||
}
|
||||
|
||||
unsigned PUdp::find_port(const char*name)
|
||||
{
|
||||
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
|
||||
|
||||
if (ports[idx] == name)
|
||||
return idx;
|
||||
}
|
||||
|
||||
return ports.count();
|
||||
}
|
||||
|
||||
@@ -1,79 +0,0 @@
|
||||
#ifndef IVL_PUdp_H
|
||||
#define IVL_PUdp_H
|
||||
/*
|
||||
* Copyright (c) 1998-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include <map>
|
||||
# include "LineInfo.h"
|
||||
# include "StringHeap.h"
|
||||
# include "svector.h"
|
||||
# include "verinum.h"
|
||||
|
||||
class PExpr;
|
||||
|
||||
/*
|
||||
* This class represents a parsed UDP. This is a much simpler object
|
||||
* than a module or macromodule.
|
||||
*
|
||||
* - all ports are scalar,
|
||||
* - pin 0 (the first port) is always output,
|
||||
* and the remaining pins are input.
|
||||
*
|
||||
* Thus, the ports can be represented as an ordered list of pin names.
|
||||
* If the output port is declared as a register in the Verilog source,
|
||||
* then this is a sequential UDP and the sequential flag is set to true.
|
||||
*
|
||||
* STATE TABLE
|
||||
* Each entry in the state table is given as a string with the same
|
||||
* number of characters as inputs. If the UDP is sequential, a
|
||||
* character is also included at the end of the string to represent
|
||||
* the current output.
|
||||
*
|
||||
* If the UDP is sequential, the "initial" member is taken to be the
|
||||
* initial value assigned in the source, or 'x' if none is given.
|
||||
*/
|
||||
class PUdp : public LineInfo {
|
||||
|
||||
public:
|
||||
explicit PUdp(perm_string n, unsigned nports);
|
||||
|
||||
svector<string>ports;
|
||||
unsigned find_port(const char*name);
|
||||
|
||||
bool sequential;
|
||||
|
||||
svector<string>tinput;
|
||||
svector<char> tcurrent;
|
||||
svector<char> toutput;
|
||||
|
||||
verinum::V initial;
|
||||
|
||||
map<string,PExpr*> attributes;
|
||||
|
||||
void dump(ostream&out) const;
|
||||
|
||||
perm_string name_;
|
||||
private:
|
||||
|
||||
private: // Not implemented
|
||||
PUdp(const PUdp&);
|
||||
PUdp& operator= (const PUdp&);
|
||||
};
|
||||
|
||||
#endif /* IVL_PUdp_H */
|
||||
@@ -1,297 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1999-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
# include "PWire.h"
|
||||
# include "PExpr.h"
|
||||
# include <cassert>
|
||||
|
||||
PWire::PWire(perm_string n,
|
||||
NetNet::Type t,
|
||||
NetNet::PortType pt,
|
||||
ivl_variable_type_t dt)
|
||||
: name_(n), type_(t), port_type_(pt), data_type_(dt),
|
||||
signed_(false), isint_(false),
|
||||
port_set_(false), net_set_(false), is_scalar_(false),
|
||||
error_cnt_(0), uarray_type_(0), set_data_type_(0),
|
||||
discipline_(0)
|
||||
{
|
||||
if (t == NetNet::INTEGER) {
|
||||
type_ = NetNet::REG;
|
||||
signed_ = true;
|
||||
isint_ = true;
|
||||
}
|
||||
}
|
||||
|
||||
NetNet::Type PWire::get_wire_type() const
|
||||
{
|
||||
return type_;
|
||||
}
|
||||
|
||||
perm_string PWire::basename() const
|
||||
{
|
||||
return name_;
|
||||
}
|
||||
|
||||
bool PWire::set_wire_type(NetNet::Type t)
|
||||
{
|
||||
assert(t != NetNet::IMPLICIT);
|
||||
|
||||
switch (type_) {
|
||||
case NetNet::IMPLICIT:
|
||||
type_ = t;
|
||||
return true;
|
||||
case NetNet::IMPLICIT_REG:
|
||||
if (t == NetNet::REG) {
|
||||
type_ = t;
|
||||
return true;
|
||||
}
|
||||
if (t == NetNet::INTEGER) {
|
||||
type_ = NetNet::REG;
|
||||
isint_ = true;
|
||||
return true;
|
||||
}
|
||||
if (t == NetNet::IMPLICIT_REG) return true;
|
||||
return false;
|
||||
case NetNet::REG:
|
||||
if (t == NetNet::INTEGER) {
|
||||
isint_ = true;
|
||||
return true;
|
||||
}
|
||||
if (t == NetNet::REG) return true;
|
||||
return false;
|
||||
default:
|
||||
if (type_ != t)
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
NetNet::PortType PWire::get_port_type() const
|
||||
{
|
||||
return port_type_;
|
||||
}
|
||||
|
||||
bool PWire::set_port_type(NetNet::PortType pt)
|
||||
{
|
||||
assert(pt != NetNet::NOT_A_PORT);
|
||||
assert(pt != NetNet::PIMPLICIT);
|
||||
|
||||
switch (port_type_) {
|
||||
case NetNet::PIMPLICIT:
|
||||
port_type_ = pt;
|
||||
return true;
|
||||
|
||||
case NetNet::NOT_A_PORT:
|
||||
return false;
|
||||
|
||||
default:
|
||||
if (port_type_ != pt)
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
bool PWire::set_data_type(ivl_variable_type_t dt)
|
||||
{
|
||||
if (data_type_ != IVL_VT_NO_TYPE) {
|
||||
if (data_type_ != dt)
|
||||
return false;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
|
||||
assert(data_type_ == IVL_VT_NO_TYPE);
|
||||
data_type_ = dt;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
ivl_variable_type_t PWire::get_data_type() const
|
||||
{
|
||||
return data_type_;
|
||||
}
|
||||
|
||||
void PWire::set_signed(bool flag)
|
||||
{
|
||||
signed_ = flag;
|
||||
}
|
||||
|
||||
bool PWire::get_signed() const
|
||||
{
|
||||
return signed_;
|
||||
}
|
||||
|
||||
bool PWire::get_isint() const
|
||||
{
|
||||
if (isint_)
|
||||
return true;
|
||||
|
||||
if (vector_type_t*tmp = dynamic_cast<vector_type_t*>(set_data_type_)) {
|
||||
return tmp->integer_flag;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool PWire::get_scalar() const
|
||||
{
|
||||
return is_scalar_;
|
||||
}
|
||||
|
||||
void PWire::set_range_scalar(PWSRType type)
|
||||
{
|
||||
is_scalar_ = true;
|
||||
switch (type) {
|
||||
case SR_PORT:
|
||||
if (port_set_) {
|
||||
cerr << get_fileline() << ": error: Port ``" << name_
|
||||
<< "'' has already been declared a port." << endl;
|
||||
error_cnt_ += 1;
|
||||
} else {
|
||||
port_set_ = true;
|
||||
}
|
||||
return;
|
||||
|
||||
case SR_NET:
|
||||
if (net_set_) {
|
||||
cerr << get_fileline() << ": error: Net ``" << name_
|
||||
<< "'' has already been declared." << endl;
|
||||
error_cnt_ += 1;
|
||||
} else {
|
||||
net_set_ = true;
|
||||
}
|
||||
return;
|
||||
|
||||
case SR_BOTH:
|
||||
if (port_set_ || net_set_) {
|
||||
if (port_set_) {
|
||||
cerr << get_fileline() << ": error: Port ``" << name_
|
||||
<< "'' has already been declared a port." << endl;
|
||||
error_cnt_ += 1;
|
||||
}
|
||||
if (net_set_) {
|
||||
cerr << get_fileline() << ": error: Net ``" << name_
|
||||
<< "'' has already been declared." << endl;
|
||||
error_cnt_ += 1;
|
||||
}
|
||||
} else {
|
||||
port_set_ = true;
|
||||
net_set_ = true;
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void PWire::set_range(const list<pform_range_t>&rlist, PWSRType type)
|
||||
{
|
||||
switch (type) {
|
||||
case SR_PORT:
|
||||
if (port_set_) {
|
||||
cerr << get_fileline() << ": error: Port ``" << name_
|
||||
<< "'' has already been declared a port." << endl;
|
||||
error_cnt_ += 1;
|
||||
} else {
|
||||
port_ = rlist;
|
||||
port_set_ = true;
|
||||
is_scalar_ = false;
|
||||
}
|
||||
return;
|
||||
|
||||
case SR_NET:
|
||||
if (net_set_) {
|
||||
cerr << get_fileline() << ": error: Net ``" << name_
|
||||
<< "'' has already been declared." << endl;
|
||||
error_cnt_ += 1;
|
||||
} else {
|
||||
net_ = rlist;
|
||||
net_set_ = true;
|
||||
is_scalar_ = false;
|
||||
}
|
||||
return;
|
||||
|
||||
case SR_BOTH:
|
||||
if (port_set_ || net_set_) {
|
||||
if (port_set_) {
|
||||
cerr << get_fileline() << ": error: Port ``" << name_
|
||||
<< "'' has already been declared a port." << endl;
|
||||
error_cnt_ += 1;
|
||||
}
|
||||
if (net_set_) {
|
||||
cerr << get_fileline() << ": error: Net ``" << name_
|
||||
<< "'' has already been declared." << endl;
|
||||
error_cnt_ += 1;
|
||||
}
|
||||
} else {
|
||||
port_ = rlist;
|
||||
port_set_ = true;
|
||||
net_ = rlist;
|
||||
net_set_ = true;
|
||||
is_scalar_ = false;
|
||||
}
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void PWire::set_unpacked_idx(const list<pform_range_t>&ranges)
|
||||
{
|
||||
if (! unpacked_.empty()) {
|
||||
cerr << get_fileline() << ": error: Array ``" << name_
|
||||
<< "'' has already been declared." << endl;
|
||||
error_cnt_ += 1;
|
||||
} else {
|
||||
unpacked_ = ranges;
|
||||
}
|
||||
}
|
||||
|
||||
void PWire::set_data_type(data_type_t*type)
|
||||
{
|
||||
assert(set_data_type_ == 0);
|
||||
set_data_type_ = type;
|
||||
|
||||
if (vector_type_t*tmp = dynamic_cast<vector_type_t*>(type)) {
|
||||
if (tmp->integer_flag)
|
||||
isint_ = true;
|
||||
}
|
||||
}
|
||||
|
||||
void PWire::set_discipline(ivl_discipline_t d)
|
||||
{
|
||||
assert(discipline_ == 0);
|
||||
discipline_ = d;
|
||||
}
|
||||
|
||||
ivl_discipline_t PWire::get_discipline(void) const
|
||||
{
|
||||
return discipline_;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PWire::symbol_type() const
|
||||
{
|
||||
switch (type_) {
|
||||
case NetNet::IMPLICIT_REG:
|
||||
case NetNet::INTEGER:
|
||||
case NetNet::REG:
|
||||
return VAR;
|
||||
default:
|
||||
return NET;
|
||||
}
|
||||
}
|
||||
@@ -1,136 +0,0 @@
|
||||
#ifndef IVL_PWire_H
|
||||
#define IVL_PWire_H
|
||||
/*
|
||||
* Copyright (c) 1998-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "netlist.h"
|
||||
# include "PNamedItem.h"
|
||||
# include <list>
|
||||
# include <map>
|
||||
# include "StringHeap.h"
|
||||
|
||||
#ifdef HAVE_IOSFWD
|
||||
# include <iosfwd>
|
||||
#else
|
||||
class ostream;
|
||||
#endif
|
||||
|
||||
class PExpr;
|
||||
class Design;
|
||||
class netdarray_t;
|
||||
|
||||
/*
|
||||
* The different type of PWire::set_range() calls.
|
||||
*/
|
||||
enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
|
||||
|
||||
/*
|
||||
* Wires include nets, registers and ports. A net or register becomes
|
||||
* a port by declaration, so ports are not separate. The module
|
||||
* identifies a port by keeping it in its port list.
|
||||
*
|
||||
* The hname parameter to the constructor is a hierarchical name. It
|
||||
* is the name of the wire within a module, so does not include the
|
||||
* current scope or any instances. Modules contain all the wires, so
|
||||
* from that perspective, sub-scopes within the module are a part of
|
||||
* the wire name.
|
||||
*/
|
||||
class PWire : public PNamedItem {
|
||||
|
||||
public:
|
||||
PWire(perm_string name,
|
||||
NetNet::Type t,
|
||||
NetNet::PortType pt,
|
||||
ivl_variable_type_t dt);
|
||||
|
||||
// Return a hierarchical name.
|
||||
perm_string basename() const;
|
||||
|
||||
NetNet::Type get_wire_type() const;
|
||||
bool set_wire_type(NetNet::Type);
|
||||
|
||||
NetNet::PortType get_port_type() const;
|
||||
bool set_port_type(NetNet::PortType);
|
||||
|
||||
void set_signed(bool flag);
|
||||
bool get_signed() const;
|
||||
bool get_isint() const;
|
||||
bool get_scalar() const;
|
||||
|
||||
bool set_data_type(ivl_variable_type_t dt);
|
||||
ivl_variable_type_t get_data_type() const;
|
||||
|
||||
void set_range_scalar(PWSRType type);
|
||||
void set_range(const std::list<pform_range_t>&ranges, PWSRType type);
|
||||
|
||||
void set_unpacked_idx(const std::list<pform_range_t>&ranges);
|
||||
void set_uarray_type(uarray_type_t*type) { uarray_type_ = type; }
|
||||
|
||||
void set_data_type(data_type_t*type);
|
||||
|
||||
void set_discipline(ivl_discipline_t);
|
||||
ivl_discipline_t get_discipline(void) const;
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
// Write myself to the specified stream.
|
||||
void dump(ostream&out, unsigned ind=4) const;
|
||||
|
||||
NetNet* elaborate_sig(Design*, NetScope*scope) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
perm_string name_;
|
||||
NetNet::Type type_;
|
||||
NetNet::PortType port_type_;
|
||||
ivl_variable_type_t data_type_;
|
||||
bool signed_;
|
||||
bool isint_; // original type of integer
|
||||
|
||||
// These members hold expressions for the bit width of the
|
||||
// wire. If they do not exist, the wire is 1 bit wide. If they
|
||||
// do exist, they represent the packed dimensions of the
|
||||
// bit. The first item in the list is the first range, and so
|
||||
// on. For example "reg [3:0][7:0] ..." will contains the
|
||||
// range_t object for [3:0] first and [7:0] last.
|
||||
std::list<pform_range_t>port_;
|
||||
bool port_set_;
|
||||
std::list<pform_range_t>net_;
|
||||
bool net_set_;
|
||||
bool is_scalar_;
|
||||
unsigned error_cnt_;
|
||||
|
||||
// If this wire is actually a memory, these indices will give
|
||||
// me the size and address ranges of the memory.
|
||||
std::list<pform_range_t>unpacked_;
|
||||
uarray_type_t*uarray_type_;
|
||||
|
||||
// This is the complex type of the wire. the data_type_ may
|
||||
// modify how this is interpreted.
|
||||
data_type_t*set_data_type_;
|
||||
|
||||
ivl_discipline_t discipline_;
|
||||
|
||||
private: // not implemented
|
||||
PWire(const PWire&);
|
||||
PWire& operator= (const PWire&);
|
||||
};
|
||||
|
||||
#endif /* IVL_PWire_H */
|
||||
@@ -1,83 +0,0 @@
|
||||
|
||||
* Getting Started with Icarus Verilog
|
||||
|
||||
Icarus Verilog is a Verilog compiler. It is suitable for use as a
|
||||
simulator, and, to some degree, synthesizer. Icarus Verilog runs under
|
||||
Linux and a variety of UNIX systems, as well as Windows as a command
|
||||
line tool, so the instructions are generally applicable to all
|
||||
environments. Note that this is only a quick start. For more detailed
|
||||
documentation, see the manual page for the iverilog command.
|
||||
|
||||
|
||||
* Hello, World!
|
||||
|
||||
The first thing you want to do as a user is learn how to compile and
|
||||
execute even the most trivial design. For the purposes of simulation,
|
||||
we use as our example *the* most trivial simulation:
|
||||
|
||||
module main;
|
||||
|
||||
initial
|
||||
begin
|
||||
$display("Hello, World");
|
||||
$finish ;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
By a text editor (or copy hello.vl from the Icarus Verilog examples
|
||||
directory) arrange for this program to be in a text file, "hello.vl".
|
||||
Next, compile this program with a command like this:
|
||||
|
||||
% iverilog -o hello hello.vl
|
||||
|
||||
The results of this compile are placed into the file "hello", as the
|
||||
"-o" flag tells the compiler where to place the compiled result. Next,
|
||||
execute the compiled program like so:
|
||||
|
||||
% vvp hello
|
||||
Hello, World
|
||||
|
||||
And there it is, the program has been executed. So what happened? The
|
||||
first step, the "iverilog" command, read and interpreted the source
|
||||
file, then generated a compiled result. The compiled form may be
|
||||
selected by command line switches, but the default form is the VVP
|
||||
format, which is actually run by the "vvp" command.
|
||||
|
||||
The "iverilog" and "vvp" commands are the only commands that users
|
||||
use to invoke Icarus Verilog. What the compiler actually does is
|
||||
controlled by command line switches. In our little example, we asked
|
||||
the compiler to compile the source program to the default vvp form,
|
||||
which is in turn executed by the vvp program.
|
||||
|
||||
|
||||
* Windows Install
|
||||
|
||||
The easiest way to install under Windows is to get a precompiled
|
||||
installer for the version you wish to install. Icarus Verilog is
|
||||
distributed for Windows users as a self-installing .exe. Just execute
|
||||
the installer and follow the instructions. During the install, take
|
||||
note of the directory where the program is installed: for example,
|
||||
C:\iverilog is a good place to install.
|
||||
|
||||
Once the binary is installed, you need to add the bin directory to
|
||||
your execution path. The executables you need are in C:\iverilog\bin,
|
||||
where the "C:\iverilog" part is actually the root of where you
|
||||
installed the package. The programs are in the bin subdirectory. Put
|
||||
this directory in your PATH environment variable, and the above
|
||||
commands become accessible to you at the command line prompt, or even
|
||||
in batch files.
|
||||
|
||||
|
||||
* Linux Install
|
||||
|
||||
Under Linux, the install is even easier. For RedHat and Mandrake based
|
||||
systems, there is the appropriate RPM file. Just install the package
|
||||
with the "rpm -U <file>" command. Debian users should get Icarus
|
||||
Verilog packages from the main Debian software site.
|
||||
|
||||
|
||||
* Install From Source
|
||||
|
||||
In this case, see README.txt and other documentation that comes with
|
||||
the source.
|
||||
-493
@@ -1,493 +0,0 @@
|
||||
THE ICARUS VERILOG COMPILATION SYSTEM
|
||||
Copyright 2000-2019 Stephen Williams
|
||||
|
||||
|
||||
1.0 What is ICARUS Verilog?
|
||||
|
||||
Icarus Verilog is intended to compile ALL of the Verilog HDL as
|
||||
described in the IEEE-1364 standard. Of course, it's not quite there
|
||||
yet. It does currently handle a mix of structural and behavioural
|
||||
constructs. For a view of the current state of Icarus Verilog, see its
|
||||
home page at <http://iverilog.icarus.com/>.
|
||||
|
||||
Icarus Verilog is not aimed at being a simulator in the traditional
|
||||
sense, but a compiler that generates code employed by back-end
|
||||
tools.
|
||||
|
||||
For instructions on how to run Icarus Verilog,
|
||||
see the ``iverilog'' man page.
|
||||
|
||||
|
||||
2.0 Building/Installing Icarus Verilog From Source
|
||||
|
||||
If you are starting from the source, the build process is designed to be
|
||||
as simple as practical. Someone basically familiar with the target
|
||||
system and C/C++ compilation should be able to build the source
|
||||
distribution with little effort. Some actual programming skills are
|
||||
not required, but helpful in case of problems.
|
||||
|
||||
If you are building on Windows, see the mingw.txt file.
|
||||
|
||||
2.1 Compile Time Prerequisites
|
||||
|
||||
You need the following software to compile Icarus Verilog from source
|
||||
on a UNIX-like system:
|
||||
|
||||
- GNU Make
|
||||
The Makefiles use some GNU extensions, so a basic POSIX
|
||||
make will not work. Linux systems typically come with a
|
||||
satisfactory make. BSD based systems (i.e., NetBSD, FreeBSD)
|
||||
typically have GNU make as the gmake program.
|
||||
|
||||
- ISO C++ Compiler
|
||||
The ivl and ivlpp programs are written in C++ and make use
|
||||
of templates and some of the standard C++ library. egcs and
|
||||
recent gcc compilers with the associated libstdc++ are known
|
||||
to work. MSVC++ 5 and 6 are known to definitely *not* work.
|
||||
|
||||
- bison and flex
|
||||
OSX note: bison 2.3 shipped with MacOS including Catalina generates
|
||||
broken code, but bison 3+ works. We recommend using the Fink
|
||||
project version of bison and flex (finkproject.org), brew version
|
||||
works fine either.
|
||||
|
||||
- gperf 3.0 or later
|
||||
The lexical analyzer doesn't recognize keywords directly,
|
||||
but instead matches symbols and looks them up in a hash
|
||||
table in order to get the proper lexical code. The gperf
|
||||
program generates the lookup table.
|
||||
|
||||
A version problem with this program is the most common cause
|
||||
of difficulty. See the Icarus Verilog FAQ.
|
||||
|
||||
- readline 4.2 or later
|
||||
On Linux systems, this usually means the readline-devel
|
||||
rpm. In any case, it is the development headers of readline
|
||||
that are needed.
|
||||
|
||||
- termcap
|
||||
The readline library, in turn, uses termcap.
|
||||
|
||||
If you are building from git, you will also need software to generate
|
||||
the configure scripts.
|
||||
|
||||
- autoconf 2.53 or later
|
||||
This generates configure scripts from configure.in. The 2.53
|
||||
or later versions are known to work, autoconf 2.13 is
|
||||
reported to *not* work.
|
||||
|
||||
2.2 Compilation
|
||||
|
||||
Unpack the tar-ball and cd into the verilog-######### directory
|
||||
(presumably, that is how you got to this README) and compile the source
|
||||
with the commands:
|
||||
|
||||
./configure
|
||||
make
|
||||
|
||||
If you are building from git, you have to run the command below before
|
||||
compiling the source. This will generate the "configure" file, which is
|
||||
automatically done when building from tarball.
|
||||
|
||||
sh autoconf.sh
|
||||
|
||||
Normally, this command automatically figures out everything it needs
|
||||
to know. It generally works pretty well. There are a few flags to the
|
||||
configure script that modify its behaviour:
|
||||
|
||||
--prefix=<root>
|
||||
The default is /usr/local, which causes the tool suite to
|
||||
be compiled for install in /usr/local/bin,
|
||||
/usr/local/share/ivl, etc.
|
||||
|
||||
I recommend that if you are configuring for precompiled
|
||||
binaries, use --prefix=/usr. On Solaris systems, it is
|
||||
common to use --prefix=/opt. You can configure for a non-root
|
||||
install with --prefix=$HOME.
|
||||
|
||||
--enable-suffix
|
||||
--enable-suffix=<your-suffix>
|
||||
--disable-suffix
|
||||
Enable/disable changing the names of install files to use
|
||||
a suffix string so that this version or install can co-
|
||||
exist with other versions. This renames the installed
|
||||
commands (iverilog, iverilog-vpi, vvp) and the installed
|
||||
library files and include directory so that installations
|
||||
with the same prefix but different suffix are guaranteed
|
||||
to not interfere with each other.
|
||||
|
||||
--host=<host-type>
|
||||
Compile iverilog for a different platform. You can use:
|
||||
x64_64-w64-mingw32 for building 64-bit Windows executables
|
||||
i686-w64-mingw32 for building 32-bit Windows executables
|
||||
Both options require installing the required mingw-w64 packages.
|
||||
|
||||
2.3 (Optional) Testing
|
||||
|
||||
To run a simple test before installation, execute
|
||||
|
||||
make check
|
||||
|
||||
The commands printed by this run might help you in running Icarus
|
||||
Verilog on your own Verilog sources before the package is installed
|
||||
by root.
|
||||
|
||||
2.4 Installation
|
||||
|
||||
Now install the files in an appropriate place. (The makefiles by
|
||||
default install in /usr/local unless you specify a different prefix
|
||||
with the --prefix=<path> flag to the configure command.) You may need
|
||||
to do this as root to gain access to installation directories.
|
||||
|
||||
make install
|
||||
|
||||
2.5 Uninstallation
|
||||
|
||||
The generated Makefiles also include the uninstall target. This should
|
||||
remove all the files that ``make install'' creates.
|
||||
|
||||
3.0 How Icarus Verilog Works
|
||||
|
||||
This tool includes a parser which reads in Verilog (plus extensions)
|
||||
and generates an internal netlist. The netlist is passed to various
|
||||
processing steps that transform the design to more optimal/practical
|
||||
forms, then is passed to a code generator for final output. The
|
||||
processing steps and the code generator are selected by command line
|
||||
switches.
|
||||
|
||||
3.1 Preprocessing
|
||||
|
||||
There is a separate program, ivlpp, that does the preprocessing. This
|
||||
program implements the `include and `define directives producing
|
||||
output that is equivalent but without the directives. The output is a
|
||||
single file with line number directives, so that the actual compiler
|
||||
only sees a single input file. See ivlpp/ivlpp.txt for details.
|
||||
|
||||
3.2 Parse
|
||||
|
||||
The Verilog compiler starts by parsing the Verilog source file. The
|
||||
output of the parse is a list of Module objects in "pform". The pform
|
||||
(see pform.h) is mostly a direct reflection of the compilation
|
||||
step. There may be dangling references, and it is not yet clear which
|
||||
module is the root.
|
||||
|
||||
One can see a human-readable version of the final pform by using the
|
||||
``-P <path>'' flag to the ``ivl'' subcommand. This will cause ivl
|
||||
to dump the pform into the file named <path>. (Note that this is not
|
||||
normally done, unless debugging the ``ivl'' subcommand.)
|
||||
|
||||
3.3 Elaboration
|
||||
|
||||
This phase takes the pform and generates a netlist. The driver selects
|
||||
(by user request or lucky guess) the root module to elaborate,
|
||||
resolves references and expands the instantiations to form the design
|
||||
netlist. (See netlist.txt.) Final semantic checks are performed during
|
||||
elaboration, and some simple optimizations are performed. The netlist
|
||||
includes all the behavioural descriptions, as well as gates and wires.
|
||||
|
||||
The elaborate() function performs the elaboration.
|
||||
|
||||
One can see a human-readable version of the final, elaborated and
|
||||
optimized netlist by using the ``-N <path>'' flag to the compiler. If
|
||||
elaboration succeeds, the final netlist (i.e., after optimizations but
|
||||
before code generation) will be dumped into the file named <path>.
|
||||
|
||||
Elaboration is performed in two steps: scopes and parameters
|
||||
first, followed by the structural and behavioural elaboration.
|
||||
|
||||
3.3.1 Scope Elaboration
|
||||
|
||||
This pass scans through the pform looking for scopes and parameters. A
|
||||
tree of NetScope objects is built up and placed in the Design object,
|
||||
with the root module represented by the root NetScope object. The
|
||||
elab_scope.cc file contains most of the code for handling this phase.
|
||||
|
||||
The tail of the elaborate_scope behaviour (after the pform is
|
||||
traversed) includes a scan of the NetScope tree to locate defparam
|
||||
assignments that were collected during scope elaboration. This is when
|
||||
the defparam overrides are applied to the parameters.
|
||||
|
||||
3.3.2 Netlist Elaboration
|
||||
|
||||
After the scopes and parameters are generated and the NetScope tree
|
||||
fully formed, the elaboration runs through the pform again, this time
|
||||
generating the structural and behavioural netlist. Parameters are
|
||||
elaborated and evaluated by now so all the constants of code
|
||||
generation are now known locally, so the netlist can be generated by
|
||||
simply passing through the pform.
|
||||
|
||||
3.4 Optimization
|
||||
|
||||
This is a collection of processing steps that perform
|
||||
optimizations that do not depend on the target technology. Examples of
|
||||
some useful transformations are
|
||||
|
||||
- eliminate null effect circuitry
|
||||
- combinational reduction
|
||||
- constant propagation
|
||||
|
||||
The actual functions performed are specified on the ivl command line by
|
||||
the -F flags (see below).
|
||||
|
||||
3.5 Code Generation
|
||||
|
||||
This step takes the design netlist and uses it to drive the code
|
||||
generator (see target.h). This may require transforming the
|
||||
design to suit the technology.
|
||||
|
||||
The emit() method of the Design class performs this step. It runs
|
||||
through the design elements, calling target functions as the need arises
|
||||
to generate actual output.
|
||||
|
||||
The user selects the target code generator with the -t flag on the
|
||||
command line.
|
||||
|
||||
3.6 ATTRIBUTES
|
||||
|
||||
NOTE: The $attribute syntax will soon be deprecated in favour of the
|
||||
Verilog-2001 attribute syntax, which is cleaner and standardized.
|
||||
|
||||
The parser accepts, as an extension to Verilog, the $attribute module
|
||||
item. The syntax of the $attribute item is:
|
||||
|
||||
$attribute (<identifier>, <key>, <value>);
|
||||
|
||||
The $attribute keyword looks like a system task invocation. The
|
||||
difference here is that the parameters are more restricted than those
|
||||
of a system task. The <identifier> must be an identifier. This will be
|
||||
the item to get an attribute. The <key> and <value> are strings, not
|
||||
expressions, that give the key and the value of the attribute to be
|
||||
attached to the identified object.
|
||||
|
||||
Attributes are [<key> <value>] pairs and are used to communicate with
|
||||
the various processing steps. See the documentation for the processing
|
||||
step for a list of the pertinent attributes.
|
||||
|
||||
Attributes can also be applied to gate types. When this is done, the
|
||||
attribute is given to every instantiation of the primitive. The syntax
|
||||
for the attribute statement is the same, except that the <identifier>
|
||||
names a primitive earlier in the compilation unit and the statement is
|
||||
placed in the global scope, instead of within a module. The semicolon is
|
||||
not part of a type attribute.
|
||||
|
||||
Note that attributes are also occasionally used for communication
|
||||
between processing steps. Processing steps that are aware of others
|
||||
may place attributes on netlist objects to communicate information to
|
||||
later steps.
|
||||
|
||||
Icarus Verilog also accepts the Verilog 2001 syntax for
|
||||
attributes. They have the same general meaning as with the $attribute
|
||||
syntax, but they are attached to objects by position instead of by
|
||||
name. Also, the key is a Verilog identifier instead of a string.
|
||||
|
||||
4.0 Running iverilog
|
||||
|
||||
The preferred way to invoke the compiler is with the iverilog(1)
|
||||
command. This program invokes the preprocessor (ivlpp) and the
|
||||
compiler (ivl) with the proper command line options to get the job
|
||||
done in a friendly way. See the iverilog(1) man page for usage details.
|
||||
|
||||
|
||||
4.1 EXAMPLES
|
||||
|
||||
Example: Compiling "hello.vl"
|
||||
|
||||
------------------------ hello.vl ----------------------------
|
||||
module main();
|
||||
|
||||
initial
|
||||
begin
|
||||
$display("Hi there");
|
||||
$finish ;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
--------------------------------------------------------------
|
||||
|
||||
Ensure that "iverilog" is on your search path, and the vpi library
|
||||
is available.
|
||||
|
||||
To compile the program:
|
||||
|
||||
iverilog hello.vl
|
||||
|
||||
(The above presumes that /usr/local/include and /usr/local/lib are
|
||||
part of the compiler search path, which is usually the case for gcc.)
|
||||
|
||||
To run the program:
|
||||
|
||||
./a.out
|
||||
|
||||
You can use the "-o" switch to name the output command to be generated
|
||||
by the compiler. See the iverilog(1) man page.
|
||||
|
||||
5.0 Unsupported Constructs
|
||||
|
||||
Icarus Verilog is in development - as such it still only supports a
|
||||
(growing) subset of Verilog. Below is a description of some of the
|
||||
currently unsupported Verilog features. This list is not exhaustive
|
||||
and does not account for errors in the compiler. See the Icarus
|
||||
Verilog web page for the current state of support for Verilog, and in
|
||||
particular, browse the bug report database for reported unsupported
|
||||
constructs.
|
||||
|
||||
- System functions are supported, but the return value is a little
|
||||
tricky. See SYSTEM FUNCTION TABLE FILES in the iverilog man page.
|
||||
|
||||
- Specify blocks are parsed but ignored in general.
|
||||
|
||||
- trireg is not supported. tri0 and tri1 are supported.
|
||||
|
||||
- tran primitives, i.e. tran, tranif1, tranif0, rtran, rtranif1
|
||||
and rtranif0 are not supported.
|
||||
|
||||
- Net delays, of the form "wire #N foo;" do not work. Delays in
|
||||
every other context do work properly, including the V2001 form
|
||||
"wire #5 foo = bar;"
|
||||
|
||||
- Event controls inside non-blocking assignments are not supported.
|
||||
i.e.: a <= @(posedge clk) b;
|
||||
|
||||
- Macro arguments are not supported. `define macros are supported,
|
||||
but they cannot take arguments.
|
||||
|
||||
5.1 Nonstandard Constructs or Behaviors
|
||||
|
||||
Icarus Verilog includes some features that are not part of the
|
||||
IEEE1364 standard, but have well-defined meaning, and also sometimes
|
||||
gives nonstandard (but extended) meanings to some features of the
|
||||
language that are defined. See the "extensions.txt" documentation for
|
||||
more details.
|
||||
|
||||
$is_signed(<expr>)
|
||||
This system function returns 1 if the expression contained is
|
||||
signed, or 0 otherwise. This is mostly of use for compiler
|
||||
regression tests.
|
||||
|
||||
$sizeof(<expr>)
|
||||
$bits(<expr>)
|
||||
The $bits system function returns the size in bits of the
|
||||
expression that is its argument. The result of this
|
||||
function is undefined if the argument doesn't have a
|
||||
self-determined size.
|
||||
|
||||
The $sizeof function is deprecated in favour of $bits, which is
|
||||
the same thing, but included in the SystemVerilog definition.
|
||||
|
||||
$simtime
|
||||
The $simtime system function returns as a 64bit value the
|
||||
simulation time, unscaled by the time units of local
|
||||
scope. This is different from the $time and $stime functions
|
||||
which return the scaled times. This function is added for
|
||||
regression testing of the compiler and run time, but can be
|
||||
used by applications who really want the simulation time.
|
||||
|
||||
Note that the simulation time can be confusing if there are
|
||||
lots of different `timescales within a design. It is not in
|
||||
general possible to predict what the simulation precision will
|
||||
turn out to be.
|
||||
|
||||
$mti_random()
|
||||
$mti_dist_uniform
|
||||
These functions are similar to the IEEE1364 standard $random
|
||||
functions, but they use the Mersenne Twister (MT19937)
|
||||
algorithm. This is considered an excellent random number
|
||||
generator, but does not generate the same sequence as the
|
||||
standardized $random.
|
||||
|
||||
Builtin system functions
|
||||
|
||||
Certain of the system functions have well-defined meanings, so
|
||||
can theoretically be evaluated at compile-time, instead of
|
||||
using runtime VPI code. Doing so means that VPI cannot
|
||||
override the definitions of functions handled in this
|
||||
manner. On the other hand, this makes them synthesizable, and
|
||||
also allows for more aggressive constant propagation. The
|
||||
functions handled in this manner are:
|
||||
|
||||
$bits
|
||||
$signed
|
||||
$sizeof
|
||||
$unsigned
|
||||
|
||||
Implementations of these system functions in VPI modules will
|
||||
be ignored.
|
||||
|
||||
Preprocessing Library Modules
|
||||
|
||||
Icarus Verilog does preprocess modules that are loaded from
|
||||
libraries via the -y mechanism. However, the only macros
|
||||
defined during the compilation of that file are those that it
|
||||
defines itself (or includes) or that are defined in the
|
||||
command line or command file.
|
||||
|
||||
Specifically, macros defined in the non-library source files
|
||||
are not remembered when the library module is loaded. This is
|
||||
intentional. If it were otherwise, then compilation results
|
||||
might vary depending on the order that libraries are loaded,
|
||||
and that is too unpredictable.
|
||||
|
||||
It is said that some commercial compilers do allow macro
|
||||
definitions to span library modules. That's just plain weird.
|
||||
|
||||
Width in %t Time Formats
|
||||
|
||||
Standard Verilog does not allow width fields in the %t formats
|
||||
of display strings. For example, this is illegal:
|
||||
|
||||
$display("Time is %0t", $time);
|
||||
|
||||
Standard Verilog instead relies on the $timeformat to
|
||||
completely specify the format.
|
||||
|
||||
Icarus Verilog allows the programmer to specify the field
|
||||
width. The "%t" format in Icarus Verilog works exactly as it
|
||||
does in standard Verilog. However, if the programmer chooses
|
||||
to specify a minimum width (i.e., "%5t"), then for that display
|
||||
Icarus Verilog will override the $timeformat minimum width and
|
||||
use the explicit minimum width.
|
||||
|
||||
vpiScope iterator on vpiScope objects.
|
||||
|
||||
In the VPI, the normal way to iterate over vpiScope objects
|
||||
contained within a vpiScope object, is the vpiInternalScope
|
||||
iterator. Icarus Verilog adds support for the vpiScope
|
||||
iterator of a vpiScope object, that iterates over *everything*
|
||||
the is contained in the current scope. This is useful in cases
|
||||
where one wants to iterate over all the objects in a scope
|
||||
without iterating over all the contained types explicitly.
|
||||
|
||||
time 0 race resolution.
|
||||
|
||||
Combinational logic is routinely modelled using always
|
||||
blocks. However, this can lead to race conditions if the
|
||||
inputs to the combinational block are initialized in initial
|
||||
statements. Icarus Verilog slightly modifies time 0 scheduling
|
||||
by arranging for always statements with ANYEDGE sensitivity
|
||||
lists to be scheduled before any other threads. This causes
|
||||
combinational always blocks to be triggered when the values in
|
||||
the sensitivity list are initialized by initial threads.
|
||||
|
||||
Nets with Types
|
||||
|
||||
Icarus Verilog supports an extended syntax that allows nets
|
||||
and regs to be explicitly typed. The currently supported types
|
||||
are logic, bool and real. This implies that "logic" and "bool"
|
||||
are new keywords. Typical syntax is:
|
||||
|
||||
wire real foo = 1.0;
|
||||
reg logic bar, bat;
|
||||
|
||||
... and so forth. The syntax can be turned off by using the
|
||||
-g2 flag to iverilog, and turned on explicitly with the -g2x
|
||||
flag to iverilog.
|
||||
|
||||
6.0 CREDITS
|
||||
|
||||
Except where otherwise noted, Icarus Verilog, ivl and ivlpp are
|
||||
Copyright Stephen Williams. The proper notices are in the head of each
|
||||
file. However, I have early on received aid in the form of fixes,
|
||||
Verilog guidance, and especially testing from many people. Testers, in
|
||||
particular, include a larger community of people interested in a GPL
|
||||
Verilog for Linux.
|
||||
-437
@@ -1,437 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1998-2019 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include "config.h"
|
||||
|
||||
# include "Statement.h"
|
||||
# include "PExpr.h"
|
||||
# include "ivl_assert.h"
|
||||
|
||||
Statement::~Statement()
|
||||
{
|
||||
}
|
||||
|
||||
PAssign_::PAssign_(PExpr*lval__, PExpr*ex, bool is_constant)
|
||||
: event_(0), count_(0), lval_(lval__), rval_(ex), is_constant_(is_constant)
|
||||
{
|
||||
delay_ = 0;
|
||||
}
|
||||
|
||||
PAssign_::PAssign_(PExpr*lval__, PExpr*de, PExpr*ex)
|
||||
: event_(0), count_(0), lval_(lval__), rval_(ex), is_constant_(false)
|
||||
{
|
||||
delay_ = de;
|
||||
}
|
||||
|
||||
PAssign_::PAssign_(PExpr*lval__, PExpr*cnt, PEventStatement*ev, PExpr*ex)
|
||||
: event_(ev), count_(cnt), lval_(lval__), rval_(ex), is_constant_(false)
|
||||
{
|
||||
delay_ = 0;
|
||||
}
|
||||
|
||||
PAssign_::~PAssign_()
|
||||
{
|
||||
delete lval_;
|
||||
delete rval_;
|
||||
}
|
||||
|
||||
PAssign::PAssign(PExpr*lval__, PExpr*ex)
|
||||
: PAssign_(lval__, ex, false), op_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PAssign::PAssign(PExpr*lval__, char op, PExpr*ex)
|
||||
: PAssign_(lval__, ex, false), op_(op)
|
||||
{
|
||||
}
|
||||
|
||||
PAssign::PAssign(PExpr*lval__, PExpr*d, PExpr*ex)
|
||||
: PAssign_(lval__, d, ex), op_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PAssign::PAssign(PExpr*lval__, PExpr*cnt, PEventStatement*d, PExpr*ex)
|
||||
: PAssign_(lval__, cnt, d, ex), op_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PAssign::PAssign(PExpr*lval__, PExpr*ex, bool is_constant)
|
||||
: PAssign_(lval__, ex, is_constant), op_(0)
|
||||
{
|
||||
}
|
||||
|
||||
PAssign::~PAssign()
|
||||
{
|
||||
}
|
||||
|
||||
PAssignNB::PAssignNB(PExpr*lval__, PExpr*ex)
|
||||
: PAssign_(lval__, ex, false)
|
||||
{
|
||||
}
|
||||
|
||||
PAssignNB::PAssignNB(PExpr*lval__, PExpr*d, PExpr*ex)
|
||||
: PAssign_(lval__, d, ex)
|
||||
{
|
||||
}
|
||||
|
||||
PAssignNB::PAssignNB(PExpr*lval__, PExpr*cnt, PEventStatement*d, PExpr*ex)
|
||||
: PAssign_(lval__, cnt, d, ex)
|
||||
{
|
||||
}
|
||||
|
||||
PAssignNB::~PAssignNB()
|
||||
{
|
||||
}
|
||||
|
||||
PBlock::PBlock(perm_string n, LexicalScope*parent, BL_TYPE t)
|
||||
: PScope(n, parent), bl_type_(t)
|
||||
{
|
||||
}
|
||||
|
||||
PBlock::PBlock(BL_TYPE t)
|
||||
: PScope(perm_string()), bl_type_(t)
|
||||
{
|
||||
}
|
||||
|
||||
PBlock::~PBlock()
|
||||
{
|
||||
for (unsigned idx = 0 ; idx < list_.size() ; idx += 1)
|
||||
delete list_[idx];
|
||||
}
|
||||
|
||||
bool PBlock::var_init_needs_explicit_lifetime() const
|
||||
{
|
||||
return default_lifetime == STATIC;
|
||||
}
|
||||
|
||||
PChainConstructor* PBlock::extract_chain_constructor()
|
||||
{
|
||||
if (list_.empty())
|
||||
return 0;
|
||||
|
||||
if (PChainConstructor*res = dynamic_cast<PChainConstructor*> (list_[0])) {
|
||||
for (size_t idx = 0 ; idx < list_.size()-1 ; idx += 1)
|
||||
list_[idx] = list_[idx+1];
|
||||
list_.resize(list_.size()-1);
|
||||
return res;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void PBlock::set_join_type(PBlock::BL_TYPE type)
|
||||
{
|
||||
assert(bl_type_ == BL_PAR);
|
||||
assert(type==BL_PAR || type==BL_JOIN_NONE || type==BL_JOIN_ANY);
|
||||
bl_type_ = type;
|
||||
}
|
||||
|
||||
void PBlock::set_statement(const vector<Statement*>&st)
|
||||
{
|
||||
list_ = st;
|
||||
}
|
||||
|
||||
void PBlock::push_statement_front(Statement*that)
|
||||
{
|
||||
ivl_assert(*this, bl_type_==BL_SEQ);
|
||||
|
||||
list_.resize(list_.size()+1);
|
||||
for (size_t idx = list_.size()-1 ; idx > 0 ; idx -= 1)
|
||||
list_[idx] = list_[idx-1];
|
||||
|
||||
list_[0] = that;
|
||||
}
|
||||
|
||||
PNamedItem::SymbolType PBlock::symbol_type() const
|
||||
{
|
||||
return BLOCK;
|
||||
}
|
||||
|
||||
PCallTask::PCallTask(const pform_name_t&n, const list<PExpr*>&p)
|
||||
: package_(0), path_(n), parms_(p.size())
|
||||
{
|
||||
list<PExpr*>::const_iterator cur = p.begin();
|
||||
for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx] = *cur;
|
||||
++cur;
|
||||
}
|
||||
assert(cur == p.end());
|
||||
}
|
||||
|
||||
PCallTask::PCallTask(PPackage*pkg, const pform_name_t&n, const list<PExpr*>&p)
|
||||
: package_(pkg), path_(n), parms_(p.size())
|
||||
{
|
||||
list<PExpr*>::const_iterator cur = p.begin();
|
||||
for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx] = *cur;
|
||||
++cur;
|
||||
}
|
||||
assert(cur == p.end());
|
||||
}
|
||||
|
||||
PCallTask::PCallTask(perm_string n, const list<PExpr*>&p)
|
||||
: package_(0), parms_(p.size())
|
||||
{
|
||||
list<PExpr*>::const_iterator cur = p.begin();
|
||||
for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx] = *cur;
|
||||
++cur;
|
||||
}
|
||||
assert(cur == p.end());
|
||||
path_.push_back(name_component_t(n));
|
||||
}
|
||||
|
||||
PCallTask::~PCallTask()
|
||||
{
|
||||
}
|
||||
|
||||
const pform_name_t& PCallTask::path() const
|
||||
{
|
||||
return path_;
|
||||
}
|
||||
|
||||
PCase::PCase(ivl_case_quality_t q, NetCase::TYPE t, PExpr*ex, svector<PCase::Item*>*l)
|
||||
: quality_(q), type_(t), expr_(ex), items_(l)
|
||||
{
|
||||
}
|
||||
|
||||
PCase::~PCase()
|
||||
{
|
||||
delete expr_;
|
||||
for (unsigned idx = 0 ; idx < items_->count() ; idx += 1)
|
||||
if ((*items_)[idx]->stat) delete (*items_)[idx]->stat;
|
||||
|
||||
delete[]items_;
|
||||
}
|
||||
|
||||
PCAssign::PCAssign(PExpr*l, PExpr*r)
|
||||
: lval_(l), expr_(r)
|
||||
{
|
||||
}
|
||||
|
||||
PCAssign::~PCAssign()
|
||||
{
|
||||
delete lval_;
|
||||
delete expr_;
|
||||
}
|
||||
|
||||
PChainConstructor::PChainConstructor(const list<PExpr*>&parms)
|
||||
: parms_(parms.size())
|
||||
{
|
||||
list<PExpr*>::const_iterator cur = parms.begin();
|
||||
for (size_t idx = 0 ; idx < parms_.size() ; idx += 1) {
|
||||
parms_[idx] = *cur;
|
||||
++cur;
|
||||
}
|
||||
assert(cur == parms.end());
|
||||
}
|
||||
|
||||
PChainConstructor::~PChainConstructor()
|
||||
{
|
||||
}
|
||||
|
||||
PCondit::PCondit(PExpr*ex, Statement*i, Statement*e)
|
||||
: expr_(ex), if_(i), else_(e)
|
||||
{
|
||||
}
|
||||
|
||||
PCondit::~PCondit()
|
||||
{
|
||||
delete expr_;
|
||||
delete if_;
|
||||
delete else_;
|
||||
}
|
||||
|
||||
PDeassign::PDeassign(PExpr*l)
|
||||
: lval_(l)
|
||||
{
|
||||
}
|
||||
|
||||
PDeassign::~PDeassign()
|
||||
{
|
||||
delete lval_;
|
||||
}
|
||||
|
||||
|
||||
PDelayStatement::PDelayStatement(PExpr*d, Statement*st)
|
||||
: delay_(d), statement_(st)
|
||||
{
|
||||
}
|
||||
|
||||
PDelayStatement::~PDelayStatement()
|
||||
{
|
||||
}
|
||||
|
||||
PDisable::PDisable(const pform_name_t&sc)
|
||||
: scope_(sc)
|
||||
{
|
||||
}
|
||||
|
||||
PDisable::~PDisable()
|
||||
{
|
||||
}
|
||||
|
||||
PDoWhile::PDoWhile(PExpr*ex, Statement*st)
|
||||
: cond_(ex), statement_(st)
|
||||
{
|
||||
}
|
||||
|
||||
PDoWhile::~PDoWhile()
|
||||
{
|
||||
delete cond_;
|
||||
delete statement_;
|
||||
}
|
||||
|
||||
PEventStatement::PEventStatement(const svector<PEEvent*>&ee)
|
||||
: expr_(ee), statement_(0), always_sens_(false)
|
||||
{
|
||||
assert(expr_.count() > 0);
|
||||
}
|
||||
|
||||
|
||||
PEventStatement::PEventStatement(PEEvent*ee)
|
||||
: expr_(1), statement_(0), always_sens_(false)
|
||||
{
|
||||
expr_[0] = ee;
|
||||
}
|
||||
|
||||
PEventStatement::PEventStatement(bool always_sens)
|
||||
: statement_(0), always_sens_(always_sens)
|
||||
{
|
||||
}
|
||||
|
||||
PEventStatement::~PEventStatement()
|
||||
{
|
||||
// delete the events and the statement?
|
||||
}
|
||||
|
||||
void PEventStatement::set_statement(Statement*st)
|
||||
{
|
||||
statement_ = st;
|
||||
}
|
||||
|
||||
bool PEventStatement::has_aa_term(Design*des, NetScope*scope)
|
||||
{
|
||||
bool flag = false;
|
||||
for (unsigned idx = 0 ; idx < expr_.count() ; idx += 1) {
|
||||
flag = expr_[idx]->has_aa_term(des, scope) || flag;
|
||||
}
|
||||
return flag;
|
||||
}
|
||||
|
||||
PForce::PForce(PExpr*l, PExpr*r)
|
||||
: lval_(l), expr_(r)
|
||||
{
|
||||
}
|
||||
|
||||
PForce::~PForce()
|
||||
{
|
||||
delete lval_;
|
||||
delete expr_;
|
||||
}
|
||||
|
||||
PForeach::PForeach(perm_string av, const list<perm_string>&ix, Statement*s)
|
||||
: array_var_(av), index_vars_(ix.size()), statement_(s)
|
||||
{
|
||||
size_t idx = 0;
|
||||
for (list<perm_string>::const_iterator cur = ix.begin()
|
||||
; cur != ix.end() ; ++cur)
|
||||
index_vars_[idx++] = *cur;
|
||||
}
|
||||
|
||||
PForeach::~PForeach()
|
||||
{
|
||||
delete statement_;
|
||||
}
|
||||
|
||||
PForever::PForever(Statement*s)
|
||||
: statement_(s)
|
||||
{
|
||||
}
|
||||
|
||||
PForever::~PForever()
|
||||
{
|
||||
delete statement_;
|
||||
}
|
||||
|
||||
PForStatement::PForStatement(PExpr*n1, PExpr*e1, PExpr*cond,
|
||||
Statement*step, Statement*st)
|
||||
: name1_(n1), expr1_(e1), cond_(cond), step_(step), statement_(st)
|
||||
{
|
||||
}
|
||||
|
||||
PForStatement::~PForStatement()
|
||||
{
|
||||
}
|
||||
|
||||
PProcess::~PProcess()
|
||||
{
|
||||
delete statement_;
|
||||
}
|
||||
|
||||
PRelease::PRelease(PExpr*l)
|
||||
: lval_(l)
|
||||
{
|
||||
}
|
||||
|
||||
PRelease::~PRelease()
|
||||
{
|
||||
delete lval_;
|
||||
}
|
||||
|
||||
PRepeat::PRepeat(PExpr*e, Statement*s)
|
||||
: expr_(e), statement_(s)
|
||||
{
|
||||
}
|
||||
|
||||
PRepeat::~PRepeat()
|
||||
{
|
||||
delete expr_;
|
||||
delete statement_;
|
||||
}
|
||||
|
||||
PReturn::PReturn(PExpr*e)
|
||||
: expr_(e)
|
||||
{
|
||||
}
|
||||
|
||||
PReturn::~PReturn()
|
||||
{
|
||||
delete expr_;
|
||||
}
|
||||
|
||||
PTrigger::PTrigger(PPackage*pkg, const pform_name_t&e)
|
||||
: package_(pkg), event_(e)
|
||||
{
|
||||
}
|
||||
|
||||
PTrigger::~PTrigger()
|
||||
{
|
||||
}
|
||||
|
||||
PWhile::PWhile(PExpr*ex, Statement*st)
|
||||
: cond_(ex), statement_(st)
|
||||
{
|
||||
}
|
||||
|
||||
PWhile::~PWhile()
|
||||
{
|
||||
delete cond_;
|
||||
delete statement_;
|
||||
}
|
||||
-600
@@ -1,600 +0,0 @@
|
||||
#ifndef IVL_Statement_H
|
||||
#define IVL_Statement_H
|
||||
/*
|
||||
* Copyright (c) 1998-2020 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# include <string>
|
||||
# include <vector>
|
||||
# include <list>
|
||||
# include "ivl_target.h"
|
||||
# include "svector.h"
|
||||
# include "StringHeap.h"
|
||||
# include "PDelays.h"
|
||||
# include "PExpr.h"
|
||||
# include "PScope.h"
|
||||
# include "HName.h"
|
||||
# include "LineInfo.h"
|
||||
class PExpr;
|
||||
class PChainConstructor;
|
||||
class PPackage;
|
||||
class Statement;
|
||||
class PEventStatement;
|
||||
class Design;
|
||||
class NetAssign_;
|
||||
class NetCAssign;
|
||||
class NetDeassign;
|
||||
class NetForce;
|
||||
class NetScope;
|
||||
|
||||
/*
|
||||
* The PProcess is the root of a behavioral process. Each process gets
|
||||
* one of these, which contains its type (initial, always, or final)
|
||||
* and a pointer to the single statement that is the process. A module
|
||||
* may have several concurrent processes.
|
||||
*/
|
||||
class PProcess : public LineInfo {
|
||||
|
||||
public:
|
||||
PProcess(ivl_process_type_t t, Statement*st)
|
||||
: type_(t), statement_(st) { }
|
||||
|
||||
virtual ~PProcess();
|
||||
|
||||
bool elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
ivl_process_type_t type() const { return type_; }
|
||||
Statement*statement() { return statement_; }
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
ivl_process_type_t type_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
/*
|
||||
* The PProcess is a process, the Statement is the actual action. In
|
||||
* fact, the Statement class is abstract and represents all the
|
||||
* possible kinds of statements that exist in Verilog.
|
||||
*/
|
||||
class Statement : virtual public LineInfo {
|
||||
|
||||
public:
|
||||
Statement() { }
|
||||
virtual ~Statement() =0;
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
map<perm_string,PExpr*> attributes;
|
||||
};
|
||||
|
||||
/*
|
||||
* Assignment statements of the various forms are handled by this
|
||||
* type. The rvalue is an expression. The lvalue needs to be figured
|
||||
* out by the parser as much as possible.
|
||||
*/
|
||||
class PAssign_ : public Statement {
|
||||
public:
|
||||
explicit PAssign_(PExpr*lval, PExpr*ex, bool is_constant);
|
||||
explicit PAssign_(PExpr*lval, PExpr*de, PExpr*ex);
|
||||
explicit PAssign_(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
|
||||
virtual ~PAssign_() =0;
|
||||
|
||||
const PExpr* lval() const { return lval_; }
|
||||
PExpr* rval() const { return rval_; }
|
||||
|
||||
protected:
|
||||
NetAssign_* elaborate_lval(Design*, NetScope*scope) const;
|
||||
NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t lv_net_type,
|
||||
ivl_variable_type_t lv_type,
|
||||
unsigned lv_width,
|
||||
bool force_unsigned =false) const;
|
||||
NetExpr* elaborate_rval_(Design*, NetScope*, ivl_type_t ntype) const;
|
||||
|
||||
NetExpr* elaborate_rval_obj_(Design*, NetScope*,
|
||||
ivl_variable_type_t type) const;
|
||||
|
||||
PExpr* delay_;
|
||||
PEventStatement*event_;
|
||||
PExpr* count_;
|
||||
|
||||
private:
|
||||
PExpr* lval_;
|
||||
PExpr* rval_;
|
||||
bool is_constant_;
|
||||
};
|
||||
|
||||
class PAssign : public PAssign_ {
|
||||
|
||||
public:
|
||||
// lval - assignment l-value
|
||||
// ex - assignment r-value
|
||||
// op - compressed assignment operator (i.e. '+', '-', ...)
|
||||
// de - delayed assignment delay expression
|
||||
explicit PAssign(PExpr*lval, PExpr*ex);
|
||||
explicit PAssign(PExpr*lval, char op, PExpr*ex);
|
||||
explicit PAssign(PExpr*lval, PExpr*de, PExpr*ex);
|
||||
explicit PAssign(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
|
||||
explicit PAssign(PExpr*lval, PExpr*ex, bool is_constant);
|
||||
~PAssign();
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
NetProc* elaborate_compressed_(Design*des, NetScope*scope) const;
|
||||
char op_;
|
||||
};
|
||||
|
||||
class PAssignNB : public PAssign_ {
|
||||
|
||||
public:
|
||||
explicit PAssignNB(PExpr*lval, PExpr*ex);
|
||||
explicit PAssignNB(PExpr*lval, PExpr*de, PExpr*ex);
|
||||
explicit PAssignNB(PExpr*lval, PExpr*cnt, PEventStatement*de, PExpr*ex);
|
||||
~PAssignNB();
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
NetProc*assign_to_memory_(class NetMemory*, PExpr*,
|
||||
Design*des, NetScope*scope) const;
|
||||
};
|
||||
|
||||
/*
|
||||
* A block statement is an ordered list of statements that make up the
|
||||
* block. The block can be sequential or parallel, which only affects
|
||||
* how the block is interpreted. The parser collects the list of
|
||||
* statements before constructing this object, so it knows a priori
|
||||
* what is contained.
|
||||
*/
|
||||
class PBlock : public PScope, public Statement, public PNamedItem {
|
||||
|
||||
public:
|
||||
enum BL_TYPE { BL_SEQ, BL_PAR, BL_JOIN_NONE, BL_JOIN_ANY };
|
||||
|
||||
// If the block has a name, it is a scope and also has a parent.
|
||||
explicit PBlock(perm_string n, LexicalScope*parent, BL_TYPE t);
|
||||
// If it doesn't have a name, it's not a scope
|
||||
explicit PBlock(BL_TYPE t);
|
||||
~PBlock();
|
||||
|
||||
BL_TYPE bl_type() const { return bl_type_; }
|
||||
|
||||
bool var_init_needs_explicit_lifetime() const;
|
||||
|
||||
// This is only used if this block is the statement list for a
|
||||
// constructor. We look for a PChainConstructor as the first
|
||||
// statement, and if it is there, extract it.
|
||||
PChainConstructor*extract_chain_constructor();
|
||||
|
||||
// If the bl_type() is BL_PAR, it is possible to replace it
|
||||
// with JOIN_NONE or JOIN_ANY. This is to help the parser.
|
||||
void set_join_type(BL_TYPE);
|
||||
|
||||
void set_statement(const std::vector<Statement*>&st);
|
||||
|
||||
// Copy the statement from that block to the front of this
|
||||
// block.
|
||||
void push_statement_front(Statement*that);
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
SymbolType symbol_type() const;
|
||||
|
||||
private:
|
||||
BL_TYPE bl_type_;
|
||||
std::vector<Statement*>list_;
|
||||
};
|
||||
|
||||
class PCallTask : public Statement {
|
||||
|
||||
public:
|
||||
explicit PCallTask(PPackage*pkg, const pform_name_t&n, const list<PExpr*>&parms);
|
||||
explicit PCallTask(const pform_name_t&n, const list<PExpr*>&parms);
|
||||
explicit PCallTask(perm_string n, const list<PExpr*>&parms);
|
||||
~PCallTask();
|
||||
|
||||
const pform_name_t& path() const;
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
NetProc* elaborate_sys(Design*des, NetScope*scope) const;
|
||||
NetProc* elaborate_usr(Design*des, NetScope*scope) const;
|
||||
|
||||
NetProc*elaborate_method_(Design*des, NetScope*scope,
|
||||
bool add_this_flag = false) const;
|
||||
NetProc*elaborate_function_(Design*des, NetScope*scope) const;
|
||||
NetProc*elaborate_void_function_(Design*des, NetScope*scope,
|
||||
NetFuncDef*def) const;
|
||||
|
||||
NetProc*elaborate_build_call_(Design*des, NetScope*scope,
|
||||
NetScope*task, NetExpr*use_this) const;
|
||||
NetProc*elaborate_sys_task_method_(Design*des, NetScope*scope,
|
||||
NetNet*net,
|
||||
perm_string method_name,
|
||||
const char*sys_task_name) const;
|
||||
NetProc*elaborate_queue_method_(Design*des, NetScope*scope,
|
||||
NetNet*net,
|
||||
perm_string method_name,
|
||||
const char*sys_task_name) const;
|
||||
bool test_task_calls_ok_(Design*des, NetScope*scope) const;
|
||||
|
||||
PPackage*package_;
|
||||
pform_name_t path_;
|
||||
vector<PExpr*> parms_;
|
||||
};
|
||||
|
||||
class PCase : public Statement {
|
||||
|
||||
public:
|
||||
struct Item {
|
||||
list<PExpr*>expr;
|
||||
Statement*stat;
|
||||
};
|
||||
|
||||
PCase(ivl_case_quality_t, NetCase::TYPE, PExpr*ex, svector<Item*>*);
|
||||
~PCase();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
ivl_case_quality_t quality_;
|
||||
NetCase::TYPE type_;
|
||||
PExpr*expr_;
|
||||
|
||||
svector<Item*>*items_;
|
||||
|
||||
private: // not implemented
|
||||
PCase(const PCase&);
|
||||
PCase& operator= (const PCase&);
|
||||
};
|
||||
|
||||
class PCAssign : public Statement {
|
||||
|
||||
public:
|
||||
explicit PCAssign(PExpr*l, PExpr*r);
|
||||
~PCAssign();
|
||||
|
||||
virtual NetCAssign* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*lval_;
|
||||
PExpr*expr_;
|
||||
};
|
||||
|
||||
/*
|
||||
* This represents the syntax "super.new(...)". This is not really an
|
||||
* executable statement, but the elaborator will handle these
|
||||
* specially and will remove them from the statement stream. If any
|
||||
*/
|
||||
class PChainConstructor : public Statement {
|
||||
public:
|
||||
explicit PChainConstructor(const list<PExpr*>&parms);
|
||||
~PChainConstructor();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
inline const std::vector<PExpr*>& chain_args(void) const
|
||||
{ return parms_; }
|
||||
|
||||
private:
|
||||
std::vector<PExpr*> parms_;
|
||||
};
|
||||
|
||||
class PCondit : public Statement {
|
||||
|
||||
public:
|
||||
PCondit(PExpr*ex, Statement*i, Statement*e);
|
||||
~PCondit();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*expr_;
|
||||
Statement*if_;
|
||||
Statement*else_;
|
||||
|
||||
private: // not implemented
|
||||
PCondit(const PCondit&);
|
||||
PCondit& operator= (const PCondit&);
|
||||
};
|
||||
|
||||
class PDeassign : public Statement {
|
||||
|
||||
public:
|
||||
explicit PDeassign(PExpr*l);
|
||||
~PDeassign();
|
||||
|
||||
virtual NetDeassign* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*lval_;
|
||||
};
|
||||
|
||||
class PDelayStatement : public Statement {
|
||||
|
||||
public:
|
||||
PDelayStatement(PExpr*d, Statement*st);
|
||||
~PDelayStatement();
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
PExpr*delay_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* This represents the parsing of a disable <scope> statement.
|
||||
*/
|
||||
class PDisable : public Statement {
|
||||
|
||||
public:
|
||||
explicit PDisable(const pform_name_t&sc);
|
||||
~PDisable();
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
pform_name_t scope_;
|
||||
};
|
||||
|
||||
class PDoWhile : public Statement {
|
||||
|
||||
public:
|
||||
PDoWhile(PExpr*ex, Statement*st);
|
||||
~PDoWhile();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*cond_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
/*
|
||||
* The event statement represents the event delay in behavioral
|
||||
* code. It comes from such things as:
|
||||
*
|
||||
* @name <statement>;
|
||||
* @(expr) <statement>;
|
||||
* @* <statement>;
|
||||
*/
|
||||
class PEventStatement : public Statement {
|
||||
|
||||
public:
|
||||
|
||||
explicit PEventStatement(const svector<PEEvent*>&ee);
|
||||
explicit PEventStatement(PEEvent*ee);
|
||||
// Make an @* statement or make a special @* version with the items
|
||||
// from functions added and outputs removed for always_comb/latch.
|
||||
explicit PEventStatement(bool always_sens = false);
|
||||
|
||||
~PEventStatement();
|
||||
|
||||
void set_statement(Statement*st);
|
||||
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
// Call this with a NULL statement only. It is used to print
|
||||
// the event expression for inter-assignment event controls.
|
||||
virtual void dump_inline(ostream&out) const;
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
|
||||
bool has_aa_term(Design*des, NetScope*scope);
|
||||
|
||||
// This method is used to elaborate, but attach a previously
|
||||
// elaborated statement to the event.
|
||||
NetProc* elaborate_st(Design*des, NetScope*scope, NetProc*st) const;
|
||||
|
||||
NetProc* elaborate_wait(Design*des, NetScope*scope, NetProc*st) const;
|
||||
NetProc* elaborate_wait_fork(Design*des, NetScope*scope) const;
|
||||
|
||||
private:
|
||||
svector<PEEvent*>expr_;
|
||||
Statement*statement_;
|
||||
bool always_sens_;
|
||||
};
|
||||
|
||||
ostream& operator << (ostream&o, const PEventStatement&obj);
|
||||
|
||||
class PForce : public Statement {
|
||||
|
||||
public:
|
||||
explicit PForce(PExpr*l, PExpr*r);
|
||||
~PForce();
|
||||
|
||||
virtual NetForce* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*lval_;
|
||||
PExpr*expr_;
|
||||
};
|
||||
|
||||
class PForeach : public Statement {
|
||||
public:
|
||||
explicit PForeach(perm_string var, const std::list<perm_string>&ix, Statement*stmt);
|
||||
~PForeach();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
NetProc* elaborate_static_array_(Design*des, NetScope*scope,
|
||||
const std::vector<netrange_t>&dims) const;
|
||||
|
||||
private:
|
||||
perm_string array_var_;
|
||||
std::vector<perm_string> index_vars_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
class PForever : public Statement {
|
||||
public:
|
||||
explicit PForever(Statement*s);
|
||||
~PForever();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
class PForStatement : public Statement {
|
||||
|
||||
public:
|
||||
PForStatement(PExpr*n1, PExpr*e1, PExpr*cond,
|
||||
Statement*step, Statement*body);
|
||||
~PForStatement();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr* name1_;
|
||||
PExpr* expr1_;
|
||||
|
||||
PExpr*cond_;
|
||||
|
||||
Statement*step_;
|
||||
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
class PNoop : public Statement {
|
||||
|
||||
public:
|
||||
PNoop() { }
|
||||
~PNoop() { }
|
||||
};
|
||||
|
||||
class PRepeat : public Statement {
|
||||
public:
|
||||
explicit PRepeat(PExpr*expr, Statement*s);
|
||||
~PRepeat();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*expr_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
class PRelease : public Statement {
|
||||
|
||||
public:
|
||||
explicit PRelease(PExpr*l);
|
||||
~PRelease();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*lval_;
|
||||
};
|
||||
|
||||
class PReturn : public Statement {
|
||||
|
||||
public:
|
||||
explicit PReturn(PExpr*e);
|
||||
~PReturn();
|
||||
|
||||
NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(std::ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*expr_;
|
||||
};
|
||||
|
||||
/*
|
||||
* The PTrigger statement sends a trigger to a named event. Take the
|
||||
* name here.
|
||||
*/
|
||||
class PTrigger : public Statement {
|
||||
|
||||
public:
|
||||
explicit PTrigger(PPackage*pkg, const pform_name_t&ev);
|
||||
~PTrigger();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PPackage*package_;
|
||||
pform_name_t event_;
|
||||
};
|
||||
|
||||
class PWhile : public Statement {
|
||||
|
||||
public:
|
||||
PWhile(PExpr*ex, Statement*st);
|
||||
~PWhile();
|
||||
|
||||
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_scope(Design*des, NetScope*scope) const;
|
||||
virtual void elaborate_sig(Design*des, NetScope*scope) const;
|
||||
virtual void dump(ostream&out, unsigned ind) const;
|
||||
|
||||
private:
|
||||
PExpr*cond_;
|
||||
Statement*statement_;
|
||||
};
|
||||
|
||||
#endif /* IVL_Statement_H */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 40 KiB |
@@ -1,88 +0,0 @@
|
||||
#ifndef PLI_TYPES_H
|
||||
#define PLI_TYPES_H
|
||||
/*
|
||||
* Copyright (c) 2003-2014 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
# undef HAVE_INTTYPES_H
|
||||
|
||||
#ifdef HAVE_INTTYPES_H
|
||||
|
||||
/*
|
||||
* If the host environment has the stdint.h header file,
|
||||
* then use that to size our PLI types.
|
||||
*/
|
||||
#ifndef __STDC_FORMAT_MACROS
|
||||
# define __STDC_FORMAT_MACROS
|
||||
#endif
|
||||
|
||||
# include <inttypes.h>
|
||||
typedef uint64_t PLI_UINT64;
|
||||
typedef int64_t PLI_INT64;
|
||||
typedef uint32_t PLI_UINT32;
|
||||
typedef int32_t PLI_INT32;
|
||||
|
||||
typedef signed short PLI_INT16;
|
||||
typedef unsigned short PLI_UINT16;
|
||||
typedef char PLI_BYTE8;
|
||||
typedef unsigned char PLI_UBYTE8;
|
||||
|
||||
# define PLI_UINT64_FMT PRIu64
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* If we do not have the c99 stdint.h header file, then use
|
||||
* configure detection to guess the pli types ourselves.
|
||||
*/
|
||||
|
||||
# define SIZEOF_UNSIGNED_LONG_LONG 8
|
||||
# define SIZEOF_UNSIGNED_LONG 8
|
||||
# define SIZEOF_UNSIGNED 4
|
||||
|
||||
#if SIZEOF_UNSIGNED >= 8
|
||||
typedef unsigned PLI_UINT64;
|
||||
typedef int PLI_INT64;
|
||||
# define PLI_UINT64_FMT "u"
|
||||
#else
|
||||
# if SIZEOF_UNSIGNED_LONG >= 8
|
||||
typedef unsigned long PLI_UINT64;
|
||||
typedef long PLI_INT64;
|
||||
# define PLI_UINT64_FMT "lu"
|
||||
# else
|
||||
# if SIZEOF_UNSIGNED_LONG_LONG > SIZEOF_UNSIGNED_LONG
|
||||
typedef unsigned long long PLI_UINT64;
|
||||
typedef long long PLI_INT64;
|
||||
# define PLI_UINT64_FMT "llu"
|
||||
# else
|
||||
typedef unsigned long PLI_UINT64;
|
||||
typedef long PLI_INT64;
|
||||
# define PLI_UINT64_FMT "lu"
|
||||
# endif
|
||||
# endif
|
||||
#endif
|
||||
|
||||
typedef signed int PLI_INT32;
|
||||
typedef unsigned int PLI_UINT32;
|
||||
typedef signed short PLI_INT16;
|
||||
typedef unsigned short PLI_UINT16;
|
||||
typedef char PLI_BYTE8;
|
||||
typedef unsigned char PLI_UBYTE8;
|
||||
#endif
|
||||
|
||||
#endif /* PLI_TYPES_H */
|
||||
@@ -0,0 +1,248 @@
|
||||
|
||||
Getting Started as a Contributor
|
||||
================================
|
||||
|
||||
Icarus Verilog development is centered around the github repository at
|
||||
`github.com/steveicarus/iverilog <http://github.com/steveicarus/iverilog>`_.
|
||||
Contributing to Icarus Verilog requires a basic knowledge of git and github,
|
||||
so see the github documentation for more information. The sections below will
|
||||
step you through the basics of getting the source code from github, making a
|
||||
branch, and submitting a pull request for review.
|
||||
|
||||
Getting Icarus Verilog
|
||||
----------------------
|
||||
|
||||
To start, you will need to clone the code. It is preferred that you use the
|
||||
"ssh" method, and the ssh based clone with the command:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git clone [email protected]:steveicarus/iverilog.git
|
||||
|
||||
This assumes that you have a github account (accounts are free) and you have
|
||||
set up your ssh authentication keys. See the
|
||||
`Authentication Guides here <https://docs.github.com/en/authentication>`_.
|
||||
|
||||
The "git clone" command will get you all the source:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git clone [email protected]:steveicarus/iverilog.git
|
||||
Cloning into 'iverilog'...
|
||||
remote: Enumerating objects: 66234, done.
|
||||
remote: Counting objects: 100% (6472/6472), done.
|
||||
remote: Compressing objects: 100% (4123/4123), done.
|
||||
remote: Total 66234 (delta 2412), reused 6039 (delta 2190), pack-reused 59762
|
||||
Receiving objects: 100% (66234/66234), 27.98 MiB | 2.53 MiB/s, done.
|
||||
Resolving deltas: 100% (50234/50234), done.
|
||||
% cd iverilog/
|
||||
|
||||
Normally, this is enough as you are now pointing at the most current
|
||||
development code, and you have implicitly created a branch "master" that
|
||||
tracks the development head. However, If you want to actually be working on a
|
||||
specific version, say for example version 11, the v11-branch, you checkout
|
||||
that branch with the command:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git checkout --track -b v11-branch origin/v11-branch
|
||||
|
||||
This creates a local branch that tracks the v11-branch in the repository, and
|
||||
switches you over to your new v11-branch. The tracking is important as it
|
||||
causes pulls from the repository to re-merge your local branch with the remote
|
||||
v11-branch. You always work on a local branch, then merge only when you
|
||||
push/pull from the remote repository.
|
||||
|
||||
Now that you've cloned the repository and optionally selected the branch you
|
||||
want to work on, your local source tree may later be synced up with the
|
||||
development source by using the git command:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git pull
|
||||
Already up to date.
|
||||
|
||||
Finally, configuration files are built by the extra step:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% sh autoconf.sh
|
||||
Autoconf in root...
|
||||
Precompiling lexor_keyword.gperf
|
||||
Precompiling vhdlpp/lexor_keyword.gperf
|
||||
|
||||
You will need autoconf and gperf installed in order for the script to work.
|
||||
If you get errors such as:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% sh autoconf.sh
|
||||
Autoconf in root...
|
||||
autoconf.sh: 10: autoconf: not found
|
||||
Precompiling lexor_keyword.gperf
|
||||
autoconf.sh: 13: gperf: not found.
|
||||
|
||||
You will need to install download and install the autoconf and gperf tools.
|
||||
|
||||
Now you are ready to configure and compile the source.
|
||||
|
||||
Icarus Specific Configuration Options
|
||||
-------------------------------------
|
||||
|
||||
Icarus takes many of the standard configuration options and those will not be
|
||||
described here. The following are specific to Icarus Verilog:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
--enable-suffix[=suffix]
|
||||
|
||||
This option allows the user to build Icarus with a default suffix or when
|
||||
provided a user defined suffix. All programs or directories are tagged with
|
||||
this suffix. e.g.(iverilog-0.8, vvp-0.8, etc.). The output of iverilog will
|
||||
reference the correct run time files and directories. The run time will check
|
||||
that it is running a file with a compatible version e.g.(you can not run a
|
||||
V0.9 file with the V0.8 run time).
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
--enable-libvvp
|
||||
|
||||
The vvp program is built as a small stub linked to a shared library,
|
||||
libvvp.so, that may be linked with other programs so that they can host
|
||||
a vvp simulation.
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
--enable-libveriuser
|
||||
|
||||
PLI version 1 (the ACC and TF routines) were deprecated in IEEE 1364-2005.
|
||||
These are supported in Icarus Verilog by the libveriuser library and cadpli
|
||||
module. Starting with v13, these will only be built if this option is used.
|
||||
|
||||
A debug options is:
|
||||
|
||||
.. code-block:: none
|
||||
|
||||
--with-valgrind
|
||||
|
||||
This option adds extra memory cleanup code and pool management code to allow
|
||||
better memory leak checking when valgrind is available. This option is not
|
||||
needed when checking for basic errors with valgrind.
|
||||
|
||||
Compiling on Linux
|
||||
------------------
|
||||
|
||||
(Note: You will need to install bison, flex, g++ and gcc) This is probably the
|
||||
easiest step. Given that you have the source tree from the above instructions,
|
||||
the compile and install is generally as simple as:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% ./configure
|
||||
configure: loading site script /usr/share/site/x86_64-unknown-linux-gnu
|
||||
checking build system type... x86_64-unknown-linux-gnu
|
||||
checking host system type... x86_64-unknown-linux-gnu
|
||||
checking for gcc... gcc
|
||||
checking whether the C compiler works... yes
|
||||
checking for C compiler default output file name... a.out
|
||||
checking for suffix of executables...
|
||||
[...and so on...]
|
||||
|
||||
% make
|
||||
mkdir dep
|
||||
Using git-describe for VERSION_TAG
|
||||
g++ -DHAVE_CONFIG_H -I. -Ilibmisc -Wall -Wextra -Wshadow -g -O2 -MD -c main.cc -o main.o
|
||||
mv main.d dep/main.d
|
||||
g++ -DHAVE_CONFIG_H -I. -Ilibmisc -Wall -Wextra -Wshadow -g -O2 -MD -c async.cc -o async.o
|
||||
mv async.d dep/async.d
|
||||
g++ -DHAVE_CONFIG_H -I. -Ilibmisc -Wall -Wextra -Wshadow -g -O2 -MD -c design_dump.cc -o design_dump.o
|
||||
mv design_dump.d dep/design_dump.d
|
||||
g++ -DHAVE_CONFIG_H -I. -Ilibmisc -Wall -Wextra -Wshadow -g -O2 -MD -c discipline.cc -o discipline.o
|
||||
[...and so on...]
|
||||
|
||||
The end result is a complete build of Icarus Verilog. You can install your
|
||||
compiled version with a command like this:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% sudo make install
|
||||
|
||||
Regression Tests
|
||||
----------------
|
||||
|
||||
Icarus Verilog comes with a fairly extensive regression test suite. As of
|
||||
2022, that test suite is included with the source in the "ivtest"
|
||||
directory. Contained in that directory are a couple driver scripts that run
|
||||
all the regression tests on the installed version of Icarus Verilog. So for
|
||||
example:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% cd ivtest
|
||||
% ./vvp_reg.pl
|
||||
% ./vvp_reg.py
|
||||
% ./vpi_reg.pl
|
||||
|
||||
will run all the regression tests for the simulation engine. (This is what
|
||||
most people will want to do.) You should rerun these tests before submitting
|
||||
patches to the developers. Also, if you are adding a new feature, you should
|
||||
add test programs to the regression test suite to validate your new feature
|
||||
(or bug fix.). The python script is the preferred method to add new tests.
|
||||
|
||||
All of these scripts take other options to test various configurations. What
|
||||
options are supported can be found by using the ``-h/--help`` argument. There
|
||||
is also a separate ``vlog95_reg.pl`` script for testing the vlog95 translation
|
||||
of the original tests. This is integrated into the existing Python test script
|
||||
for the new tests.
|
||||
|
||||
Note that pull requests will be required to pass these regression tests before
|
||||
being merged.
|
||||
|
||||
Forks, Branches and Pull Requests
|
||||
---------------------------------
|
||||
|
||||
Currently, the preferred way to submit patches to Icarus Verilog is via pull
|
||||
requests.
|
||||
`Pull requests <https://docs.github.com/en/github-ae@latest/pull-requests>`_
|
||||
can be created from the main repository if you have write access (very few
|
||||
people have write access) or more commonly from a fork, so the first step is
|
||||
to create a fork that you can work with. It is easy enough to create a fork,
|
||||
just go to the
|
||||
`github.com/steveicarus/iverilog <http://github.com/steveicarus/iverilog>`_
|
||||
page and use the "fork" button in the upper right corner. This will create
|
||||
a new repository that you can clone instead of the steveicarus/iverilog
|
||||
repository. You then use your local repository to create feature branches,
|
||||
then submit them for inclusion in the main repository as pull
|
||||
requests. Remember to `synchronize your fork
|
||||
<https://docs.github.com/en/github-ae@latest/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork>`_
|
||||
periodically with the main repository. This will make sure your work is based
|
||||
on the latest upstream and avoid merge conflicts.
|
||||
|
||||
Create your patch by first creating a branch that contains your commits:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git checkout -b my-github-id/branch-name
|
||||
|
||||
We are encouraging using this scheme for naming your branches that are
|
||||
destined for pull requests. Use your github id in the branch name. So for
|
||||
example:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git checkout -b steveicarus/foo-feature
|
||||
|
||||
Do your work in this branch, then when you are ready to create a pull request,
|
||||
first push the branch up to github:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
% git push -u origin my-github-id/branch-name
|
||||
|
||||
Then go to github.com to create your pull request. `Create your pull request
|
||||
against the "master" branch of the upstream repository
|
||||
<https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/creating-a-pull-request-from-a-fork>`_,
|
||||
or the version branch that you are working on. Your pull request will be run
|
||||
through continuous integration, and reviewed by one of the main
|
||||
authors. Feedback may be offered to your PR, and once accepted, an approved
|
||||
individual will merge it for you. Then you are done.
|
||||
@@ -1,4 +1,7 @@
|
||||
|
||||
Glossary
|
||||
========
|
||||
|
||||
Throughout Icarus Verilog descriptions and source code, I use a
|
||||
variety of terms and acronyms that might be specific to Icarus
|
||||
Verilog, have an Icarus Verilog specific meaning, or just aren't
|
||||
@@ -22,7 +25,7 @@ UDP - User Defined Primitive
|
||||
syntax for defining them is described in the LRM.
|
||||
|
||||
|
||||
VPI -
|
||||
VPI - Verilog Procedural Interface
|
||||
This is the C API that is defined by the Verilog standard, and
|
||||
that Icarus Verilog partially implements. See also PLI.
|
||||
|
||||
@@ -34,6 +37,12 @@ VVM - Verilog Virtual Machine
|
||||
|
||||
VVP - Verilog Virtual Processor
|
||||
This is the Icarus Verilog runtime that reads in custom code in a
|
||||
form that I call "VVP Assembly". See the vvp/ directory for
|
||||
documentation on that.
|
||||
form that I call "VVP Assembly".
|
||||
|
||||
LPM - Library of Parameterized Modules
|
||||
LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
|
||||
a standard library of abstract devices that are designed to be close
|
||||
enough to the target hardware to be easily translated, yet abstract
|
||||
enough to support a variety of target technologies without excessive
|
||||
constraints. Icarus Verilog uses LPM internally to represent idealized
|
||||
hardware, especially when doing target neutral synthesis.
|
||||
@@ -1,7 +1,6 @@
|
||||
|
||||
CADENCE PLI1 MODULES
|
||||
|
||||
Copyright 2003 Stephen Williams
|
||||
Cadence PLI1 Modules
|
||||
====================
|
||||
|
||||
With the cadpli module, Icarus Verilog is able to load PLI1
|
||||
applications that were compiled and linked to be dynamic loaded by
|
||||
@@ -17,7 +16,7 @@ is invoked by the usual -m flag to iverilog or vvp. This module in
|
||||
turn scans the extended arguments, looking for +cadpli= arguments. The
|
||||
latter specify the share object and bootstrap function for running the
|
||||
module. For example, to run the module product.so, that has the
|
||||
bootstrap function "my_boot":
|
||||
bootstrap function "my_boot"::
|
||||
|
||||
vvp -mcadpli a.out -cadpli=./product.so:my_boot
|
||||
|
||||
@@ -1,21 +1,24 @@
|
||||
|
||||
Developer Quick Start for Icarus Verilog
|
||||
Developer Guide
|
||||
===============
|
||||
|
||||
The documentation for getting, building and installing Icarus Verilog
|
||||
is kept and maintained at the iverilog documentation wiki at
|
||||
<http://iverilog.wikia.com>. See the Installation Guide for getting
|
||||
the current source from the git repository (and how to use the git
|
||||
repository) and see the Developer Guide for instructions on
|
||||
participating in the Icarus Verilog development process. That
|
||||
information will not be repeated here.
|
||||
|
||||
What this documentation *will* cover is the gross structure of the
|
||||
The developer guide is intended to give you a gross structure of the
|
||||
Icarus Verilog compiler source. This will help orient you to the
|
||||
source code itself, so that you can find the global parts where you
|
||||
can look for even better detail.
|
||||
|
||||
The documentation for getting, building and installing Icarus Verilog
|
||||
is kept and maintained at :doc:`Getting Started as a Contributor <../getting_started>`
|
||||
|
||||
* Compiler Components
|
||||
See the Installation Guide for getting the current source from the git
|
||||
repository (and how to use the git repository) and see the Developer Guide
|
||||
for instructions on participating in the Icarus Verilog development process.
|
||||
That information will not be repeated here.
|
||||
|
||||
Scroll down to a listing with further readings.
|
||||
|
||||
Compiler Components
|
||||
-------------------
|
||||
|
||||
- The compiler driver (driver/)
|
||||
|
||||
@@ -26,28 +29,29 @@ subcommands to perform the steps of compilation.
|
||||
- The preprocessor (ivlpp/)
|
||||
|
||||
This implements the Verilog pre-processor. In Icarus Verilog, the
|
||||
compiler directives `define, `include, `ifdef and etc. are implemented
|
||||
compiler directives \`define, \`include, \`ifdef and etc. are implemented
|
||||
in an external program. The ivlpp/ directory contains the source for
|
||||
this program.
|
||||
|
||||
- The core compiler (this directory)
|
||||
- The core compiler (root directory)
|
||||
|
||||
The "ivl" program is the core that does all the Verilog compiler
|
||||
processing that is not handled elsewhere. This is the main core of the
|
||||
Icarus Verilog compiler, not the runtime. See below for more details
|
||||
on the core itself.
|
||||
|
||||
- The loadable code generators (tgt-*/)
|
||||
- The loadable code generators (tgt-\*/)
|
||||
|
||||
This core compiler, after it is finished with parsing and semantic
|
||||
analysis, uses loadable code generators to emit code for supported
|
||||
targets. The tgt-*/ directories contains the source for the target
|
||||
targets. The tgt-\*/ directories contains the source for the target
|
||||
code generators that are bundled with Icarus Verilog. The tgt-vvp/
|
||||
directory in particular contains the code generator for the vvp
|
||||
runtime.
|
||||
|
||||
|
||||
* Runtime Components
|
||||
Runtime Components
|
||||
------------------
|
||||
|
||||
- The vvp runtime (vvp/)
|
||||
|
||||
@@ -75,7 +79,8 @@ PLI-1 code written for Verilog-XL. This directory contains the source
|
||||
for the module that provides the Cadence PLI interface.
|
||||
|
||||
|
||||
* The Core Compiler
|
||||
The Core Compiler
|
||||
-----------------
|
||||
|
||||
The "ivl" binary is the core compiler that does the heavy lifting of
|
||||
compiling the Verilog source (including libraries) and generating the
|
||||
@@ -147,3 +152,18 @@ parameters must be intermingled with the elaboration of scopes because
|
||||
the exact values of parameters may impact the scopes created (imagine
|
||||
generate schemes and instance arrays) and the created scopes in turn
|
||||
create new parameters that need override and evaluation.
|
||||
|
||||
Further Reading
|
||||
---------------
|
||||
|
||||
For further information on the individual parts of Icarus Verilog, see this listing:
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
|
||||
ivl/index
|
||||
vvp/index
|
||||
tgt-vvp/tgt-vvp
|
||||
vpi/index
|
||||
cadpli/cadpli
|
||||
misc/index
|
||||
@@ -1,14 +1,19 @@
|
||||
|
||||
ATTRIBUTE NAMING CONVENTIONS
|
||||
Icarus Verilog Attributes
|
||||
=========================
|
||||
|
||||
Attribute Naming Conventions
|
||||
----------------------------
|
||||
|
||||
Attributes that are specific to Icarus Verilog, and are intended to be
|
||||
of use to programmers, start with the prefix "ivl_".
|
||||
of use to programmers, start with the prefix "ivl\_".
|
||||
|
||||
Attributes with the "_ivl_" prefix are set aside for internal
|
||||
use. They may be generated internally by the compiler. They need not
|
||||
be documented here.
|
||||
|
||||
ATTRIBUTES TO CONTROL SYNTHESIS
|
||||
Attributes To Control Synthesis
|
||||
-------------------------------
|
||||
|
||||
The following is a summary of Verilog attributes that Icarus Verilog
|
||||
understands within Verilog source files to control synthesis
|
||||
@@ -23,7 +28,7 @@ warning.)
|
||||
|
||||
* Attributes for "always" and "initial" statements
|
||||
|
||||
(* ivl_combinational *)
|
||||
(\* ivl_combinational \*)
|
||||
|
||||
This attribute tells the compiler that the statement models
|
||||
combinational logic. If the compiler finds that it cannot make
|
||||
@@ -34,14 +39,14 @@ warning.)
|
||||
latches or flip-flops where the user intended combinational
|
||||
logic.
|
||||
|
||||
(* ivl_synthesis_on *)
|
||||
(\* ivl_synthesis_on \*)
|
||||
|
||||
This attribute tells the compiler that the marked always statement
|
||||
is synthesizable. The compiler will attempt to synthesize the
|
||||
code in the marked "always" statement. If it cannot in any way
|
||||
synthesize it, then it will report an error.
|
||||
|
||||
(* ivl_synthesis_off *)
|
||||
(\* ivl_synthesis_off \*)
|
||||
|
||||
If this value is attached to an "always" statement, then the
|
||||
compiler will *not* synthesize the "always" statement. This can be
|
||||
@@ -50,7 +55,7 @@ warning.)
|
||||
|
||||
* Attributes for modules
|
||||
|
||||
(* ivl_synthesis_cell *)
|
||||
(\* ivl_synthesis_cell \*)
|
||||
|
||||
If this value is attached to a module during synthesis, that
|
||||
module will be considered a target architecture primitive, and
|
||||
@@ -60,7 +65,7 @@ warning.)
|
||||
|
||||
* Attributes for signals (wire/reg/integer/tri/etc.)
|
||||
|
||||
(* PAD = "<pad assignment list>" *)
|
||||
(\* PAD = "<pad assignment list>" \*)
|
||||
|
||||
If this attribute is attached to a signal that happens to be a
|
||||
root module port, then targets that support it will use the string
|
||||
@@ -73,9 +78,10 @@ warning.)
|
||||
[ none defined yet ]
|
||||
|
||||
|
||||
MISC
|
||||
Misc
|
||||
----
|
||||
|
||||
(* _ivl_schedule_push *)
|
||||
(\* _ivl_schedule_push \*)
|
||||
|
||||
If this attribute is attached to a thread object (always or
|
||||
initial statement) then the vvp code generator will generate code
|
||||
@@ -0,0 +1,12 @@
|
||||
|
||||
IVL - The Core Compiler
|
||||
=======================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
netlist
|
||||
attributes
|
||||
ivl_target
|
||||
lpm
|
||||
t-dll
|
||||
@@ -0,0 +1,131 @@
|
||||
|
||||
Loadable Target API (ivl_target)
|
||||
================================
|
||||
|
||||
In addition to the standard VPI API, Icarus Verilog supports a non-standard
|
||||
loadable target module API. This API helps C programmers write modules that
|
||||
Icarus Verilog can use to generate code. These modules are used at compile
|
||||
time to write the elaborated design to the simulation or netlist files. For
|
||||
example, the vvp code generator is a loadable target module that writes vvp
|
||||
code into the specified file.
|
||||
|
||||
Loadable target modules gain access to the 'elaborated' design. That means,
|
||||
the source files have been checked for syntax and correctness, any synthesis
|
||||
and general optimization steps have been performed, and what is left is a
|
||||
design that reflects but is not exactly the same as the input Verilog source
|
||||
code. This relieves the modules of the burden of supporting all the odd
|
||||
corners and complexities of the Verilog language.
|
||||
|
||||
The Target Module API
|
||||
---------------------
|
||||
|
||||
The API is defined in the header file "ivl_target.h" which is installed with
|
||||
Icarus Verilog. The header defines the functions that the module writer can
|
||||
use to get at the elaborated design during the course of writing the output
|
||||
format.
|
||||
|
||||
The target module API function "target_design" is special in that the API does
|
||||
not provide this function: The target module itself provides it. When the
|
||||
compiler loads the target module, it invokes the "target_design" function with
|
||||
a handle to the design. This is the point where the target module takes over
|
||||
to process the design.
|
||||
|
||||
Compiling Target Modules
|
||||
------------------------
|
||||
|
||||
Compiling loadable target modules is similar to compiling VPI modules, in that
|
||||
the module must be compiled with the "-fPIC" flag to gcc, and linked with the
|
||||
"-shared" flag. The module that you compile is then installed in a place where
|
||||
the "iverilog" command can find it, and configuration files are adjusted to
|
||||
account for the new module.
|
||||
|
||||
This code::
|
||||
|
||||
# include <ivl_target.h>
|
||||
|
||||
int target_design(ivl_design_t des)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
is an example module that we can write into the file "empty.c"; and let us
|
||||
compile it into the module file "empty.tgt" like so::
|
||||
|
||||
% gcc -o empty.tgt -fpic -shared empty.c
|
||||
|
||||
This makes the "empty.tgt" file an a dynamically loaded shared object.
|
||||
|
||||
Creating the Target Config File
|
||||
-------------------------------
|
||||
|
||||
The target config file tells the Icarus Verilog core how to process your new
|
||||
code generator. The ivl core expects two configuration files: the name.conf
|
||||
and the name-s.config files. The "-s" version is what is used if the user
|
||||
gives the "-S" (synthesis) flag on the command line.
|
||||
|
||||
The stub target, included in most distributions, demonstrates the config
|
||||
files. The "stub.conf" file is::
|
||||
|
||||
functor:cprop
|
||||
functor:nodangle
|
||||
-t:dll
|
||||
flag:DLL=stub.tgt
|
||||
|
||||
and the "stub-s.conf" file is::
|
||||
|
||||
functor:synth2
|
||||
functor:synth
|
||||
functor:syn-rules
|
||||
functor:cprop
|
||||
functor:nodangle
|
||||
-t:dll
|
||||
flag:DLL=stub.tgt
|
||||
|
||||
Note that the "stub-s.conf" file contains more lines to invoke internal
|
||||
synthesis functions, whereas the "stub.conf" invokes only the basic
|
||||
optimization steps.
|
||||
|
||||
In general, only the last line (The "flag:DLL=<name>.tgt" record) varies for
|
||||
each target. For your target, replace the <name> with the name of your target
|
||||
and you have a configuration file ready to install. Note that this is the name
|
||||
of your target module. This is in fact how the config file tells the compiler
|
||||
the name of your module.
|
||||
|
||||
The rest of the config file is best taken as boiler plate and installed as is,
|
||||
with one difference. If your target is a synthesis target (for example a mosis
|
||||
code generator or a pld code generator) that expects synthesis to happen, then
|
||||
it makes the most sense to create both your config file like the "stub-s.conf"
|
||||
config file. This causes the compiler to do synthesis for your target whether
|
||||
the user gives the "-S" flag or not.
|
||||
|
||||
Installing the Target Module
|
||||
----------------------------
|
||||
|
||||
Finally, the "empty.conf", the "empty-s.conf" and the "empty.tgt" files need
|
||||
to be installed. Where they go depends on your system, but in Linux they are
|
||||
normally installed in "/usr/lib/ivl".
|
||||
|
||||
|
||||
LPM Devices
|
||||
-----------
|
||||
|
||||
All LPM devices support a small set of common LPM functions, as
|
||||
described in the ivl_target header file. The ivl_lpm_t object has a
|
||||
type enumerated by ivl_lpm_type_t, and that type is accessible via the
|
||||
ivl_lpm_type function.
|
||||
|
||||
The following are type specific aspects of LPM devices.
|
||||
|
||||
* IVL_LPM_UFUNC
|
||||
|
||||
This LPM represents a user defined function. It is a way to connect
|
||||
behavioral code into a structural network. The UFUNC device has a
|
||||
vector output and a set of inputs. The ivl_lpm_define function returns
|
||||
the definition as an ivl_scope_t object.
|
||||
|
||||
The output vector is accessible through the ivl_lpm_q, and the output
|
||||
has the width defined by ivl_lpm_width. This similar to most every
|
||||
other LPM device with outputs.
|
||||
|
||||
There are ivl_lpm_size() input ports, each with the width
|
||||
ivl_lpm_data2_width(). The actual nexus is indexed by ivl_lpm_data2().
|
||||
@@ -1,5 +1,6 @@
|
||||
|
||||
WHAT IS LPM
|
||||
What Is LPM
|
||||
===========
|
||||
|
||||
LPM (Library of Parameterized Modules) is EIS-IS standard 103-A. It is
|
||||
a standard library of abstract devices that are designed to be close
|
||||
@@ -13,11 +14,12 @@ generates, because the LPM devices are translated into technology
|
||||
specific devices by the final code generator or target specific
|
||||
optimizers.
|
||||
|
||||
INTERNAL USES OF LPM
|
||||
Internal Uses Of LPM
|
||||
--------------------
|
||||
|
||||
Internally, Icarus Verilog uses LPM devices to represent the design in
|
||||
abstract, especially when synthesizing such functions as addition,
|
||||
flip-flops, etc. The ``synth'' functor generates LPM modules when
|
||||
flip-flops, etc. The `synth` functor generates LPM modules when
|
||||
interpreting procedural constructs. The functor generates the LPM
|
||||
objects needed to replace a behavioral description, and uses
|
||||
attributes to tag the devices with LPM properties.
|
||||
@@ -1,27 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 1998-1999 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
|
||||
|
||||
Note that the netlist.h header contains detailed descriptions of how
|
||||
things work. This is just an overview.
|
||||
|
||||
NETLIST FORMAT
|
||||
Netlist Format
|
||||
==============
|
||||
|
||||
The output from the parse and elaboration steps is a "netlist" rooted
|
||||
in a Design object. Parsing translates the design described in the
|
||||
@@ -35,7 +14,8 @@ translating it to a (hopefully) better netlist after each step. The
|
||||
complete netlist is then passed to the code generator, the emit
|
||||
function, where the final code (in the target format) is produced.
|
||||
|
||||
STRUCTURAL ITEMS: NetNode and NetNet
|
||||
Structural Items: NetNode and NetNet
|
||||
------------------------------------
|
||||
|
||||
Components and wires, memories and registers all at their base are
|
||||
either NetNode objects or NetNet objects. Even these classes are
|
||||
@@ -56,7 +36,8 @@ destructors for nets and nodes automatically arrange for pins to be
|
||||
disconnected when the item is deleted, so that the netlist can be
|
||||
changed during processing.
|
||||
|
||||
STRUCTURAL LINKS
|
||||
Structural Links
|
||||
----------------
|
||||
|
||||
The NetNode and NetNet classes contain arrays of Link objects, one
|
||||
object per pin. Each pin is a single bit. The Link objects link to all
|
||||
@@ -88,12 +69,13 @@ Currently, a link has 3 possible direction properties:
|
||||
three-state.)
|
||||
|
||||
|
||||
BEHAVIORAL ITEMS: NetProcTop, NetProc and derived classes
|
||||
Behavioral Items: NetProcTop, NetProc and derived classes
|
||||
---------------------------------------------------------
|
||||
|
||||
Behavioral items are not in general linked to the netlist. Instead,
|
||||
they represent elaborated behavioral statements. The type of the object
|
||||
implies what the behavior of the statement does. For example, a
|
||||
NetCondit object represents an ``if'' statement, and carries a
|
||||
NetCondit object represents an `if` statement, and carries a
|
||||
condition expression and up to two alternative sub-statements.
|
||||
|
||||
At the root of a process is a NetProcTop object. This class carries a
|
||||
@@ -104,7 +86,8 @@ tree is the NetProcTop object. The Design class keeps a list of the
|
||||
elaborated NetProcTop objects. That list represents the list of
|
||||
processes in the design.
|
||||
|
||||
INTERACTION OF BEHAVIORAL AND STRUCTURAL: NetAssign_
|
||||
Interaction Of Behavioral And Structural: NetAssign\_
|
||||
-----------------------------------------------------
|
||||
|
||||
The behavioral statements in a Verilog design effect the structural
|
||||
aspects through assignments to registers. Registers are structural
|
||||
@@ -113,26 +96,27 @@ statement through pins. This implies that the l-value of an assignment
|
||||
is structural. It also implies that the statement itself is
|
||||
structural, and indeed it is derived from NetNode.
|
||||
|
||||
The NetAssign_ class is also derived from the NetProc class because
|
||||
The NetAssign\_ class is also derived from the NetProc class because
|
||||
what it does is brought on by executing the process. By multiple
|
||||
inheritance we have therefore that the assignment is both a NetNode
|
||||
and a NetProc. The NetAssign_ node has pins that represent the l-value
|
||||
and a NetProc. The NetAssign\_ node has pins that represent the l-value
|
||||
of the statement, and carries behavioral expressions that represent
|
||||
the r-value of the assignment.
|
||||
|
||||
MEMORIES
|
||||
Memories
|
||||
--------
|
||||
|
||||
The netlist form includes the NetMemory type to hold the content of a
|
||||
memory. Instances of this type represent the declaration of a memory,
|
||||
and occur once for each memory. References to the memory are managed
|
||||
by the NetEMemory and NetAssignMem_ classes.
|
||||
by the NetEMemory and NetAssignMem\_ classes.
|
||||
|
||||
An instance of the NetEMemory class is created whenever a procedural
|
||||
expression references a memory element. The operand is the index to
|
||||
use to address (and read) the memory.
|
||||
|
||||
An instance of the NetAssignMem_ class is created when there is a
|
||||
procedural assignment to the memory. The NetAssignMem_ object
|
||||
An instance of the NetAssignMem\_ class is created when there is a
|
||||
procedural assignment to the memory. The NetAssignMem\_ object
|
||||
represents the l-value reference (a write) to the memory. As with the
|
||||
NetEMemory class, this is a procedural reference only.
|
||||
|
||||
@@ -143,13 +127,14 @@ unconnected for now, because memories cannot appear is l-values of
|
||||
continuous assignments. However, the synthesis functor may connect
|
||||
signals to the write control lines to get a fully operational RAM.
|
||||
|
||||
By the time elaboration completes, there may be many NetAssignMem_,
|
||||
By the time elaboration completes, there may be many NetAssignMem\_,
|
||||
NetEMemory and NetRamDq objects referencing the same NetMemory
|
||||
object. Each represents a port into the memory. It is up to the
|
||||
synthesis steps (and the target code) to figure out what to do with
|
||||
these ports.
|
||||
|
||||
EXPRESSIONS
|
||||
Expressions
|
||||
-----------
|
||||
|
||||
Expressions are represented as a tree of NetExpr nodes. The NetExpr
|
||||
base class contains the core methods that represent an expression
|
||||
@@ -168,7 +153,8 @@ However, typical expressions the behavioral description are
|
||||
represented as a tree of NetExpr nodes. The derived class of the node
|
||||
encodes what kind of operator the node represents.
|
||||
|
||||
EXPRESSION BIT WIDTH
|
||||
Expression Bit Width
|
||||
--------------------
|
||||
|
||||
The expression (represented by the NetExpr class) has a bit width that
|
||||
it either explicitly specified, or implied by context or contents.
|
||||
@@ -200,14 +186,17 @@ determined and please adapt. If the expression cannot reasonably
|
||||
adapt, it will return false. Otherwise, it will adjust bit widths and
|
||||
return true.
|
||||
|
||||
XXXX I do not yet properly deal with cases where elaboration knows for
|
||||
XXXX certain that the bit width does not matter. In this case, I
|
||||
XXXX really should tell the expression node about it so that it can
|
||||
XXXX pick a practical (and optimal) width.
|
||||
::
|
||||
|
||||
INTERACTION OF EXPRESSIONS AND STRUCTURE: NetESignal
|
||||
I do not yet properly deal with cases where elaboration knows for
|
||||
certain that the bit width does not matter. In this case, I
|
||||
really should tell the expression node about it so that it can
|
||||
pick a practical (and optimal) width.
|
||||
|
||||
The NetAssign_ class described above is the means for processes to
|
||||
Interaction Of Expressions And Structure: NetESignal
|
||||
----------------------------------------------------
|
||||
|
||||
The NetAssign\_ class described above is the means for processes to
|
||||
manipulate the net, but values are read from the net by NetESignal
|
||||
objects. These objects are class NetExpr because they can appear in
|
||||
expressions (and have width). They are not NetNode object, but hold
|
||||
@@ -215,7 +204,8 @@ pointers to a NetNet object, which is used to retrieve values with the
|
||||
expression is evaluated.
|
||||
|
||||
|
||||
HIERARCHY IN NETLISTS
|
||||
Hierarchy In Netlists
|
||||
---------------------
|
||||
|
||||
The obvious hierarchical structure of Verilog is the module. The
|
||||
Verilog program may contain any number of instantiations of modules in
|
||||
@@ -236,7 +226,8 @@ boundaries. This makes coding of netlist transform functions such as
|
||||
constant propagation more effective and easier to write.
|
||||
|
||||
|
||||
SCOPE REPRESENTATION IN NETLISTS
|
||||
Scope Representation In Netlists
|
||||
--------------------------------
|
||||
|
||||
In spite of the literal flattening of the design, scope information is
|
||||
preserved in the netlist, with the NetScope class. The Design class
|
||||
@@ -258,7 +249,8 @@ scope. Overrides are managed during the scan, and once the scan is
|
||||
complete, defparam overrides are applied.
|
||||
|
||||
|
||||
TASKS IN NETLISTS
|
||||
Tasks In Netlists
|
||||
-----------------
|
||||
|
||||
The flattening of the design does not include tasks and named
|
||||
begin-end blocks. Tasks are behavioral hierarchy (whereas modules are
|
||||
@@ -268,7 +260,8 @@ recurse. (The elaboration process does reserve the right to flatten
|
||||
some task calls. C++ programmers recognize this as inlining a task.)
|
||||
|
||||
|
||||
TIME SCALE IN NETLISTS
|
||||
Time Scale In Netlists
|
||||
----------------------
|
||||
|
||||
The Design class and the NetScope classes carry time scale and
|
||||
resolution information of the elaborated design. There is a global
|
||||
@@ -1,5 +1,6 @@
|
||||
|
||||
LOADABLE TARGETS
|
||||
Loadable Targets
|
||||
================
|
||||
|
||||
Icarus Verilog supports dynamically loading code generator modules to
|
||||
perform the back-end processing of the completed design. The user
|
||||
@@ -12,24 +13,28 @@ compiler calls to pass the design to it, and the module in turn uses a
|
||||
collection of functions in the core (the API) to access details of the
|
||||
design.
|
||||
|
||||
LOADING TARGET MODULES
|
||||
Loading Target Modules
|
||||
----------------------
|
||||
|
||||
The target module loader is invoked with the ivl flag "-tdll". That
|
||||
is, the DLL loader is a linked in target type. The name of the target
|
||||
module to load is then specified with the DLL flag, i.e. "-fDLL=<path>".
|
||||
|
||||
COMPILING TARGET MODULES
|
||||
Compiling Target Modules
|
||||
------------------------
|
||||
|
||||
<write me>
|
||||
|
||||
LOADABLE TARGET MODULE API
|
||||
Loadable Target Module Api
|
||||
--------------------------
|
||||
|
||||
The target module API is defined in the ivl_target.h header file. This
|
||||
declares all the type and functions that a loadable module needs to
|
||||
access the design.
|
||||
|
||||
|
||||
ABOUT SPECIFIC EXPRESSION TYPES
|
||||
About Specific Expression Types
|
||||
-------------------------------
|
||||
|
||||
In this section find notes about the various kinds of expression
|
||||
nodes. The notes here are in addition to the more general
|
||||
@@ -1,9 +1,6 @@
|
||||
|
||||
NOTE: THE CONTENTS OF THIS FILE ARE BEING MOVED TO THE DOCUMENTATION
|
||||
WIKI AT http://iverilog.wikia.com. PLEASE ADD NEW ENTRIES THERE.
|
||||
|
||||
Icarus Verilog vs. IEEE1364
|
||||
Copyright 2000 Stephen Williams
|
||||
IEEE1364 Notes
|
||||
==============
|
||||
|
||||
The IEEE1364 standard is the bible that defines the correctness of the
|
||||
Icarus Verilog implementation and behavior of the compiled
|
||||
@@ -19,7 +16,8 @@ and common to write programs that produce different results when run
|
||||
by different Verilog implementations.
|
||||
|
||||
|
||||
STANDARDIZATION ISSUES
|
||||
Standardization Issues
|
||||
----------------------
|
||||
|
||||
These are some issues where the IEEE1364 left unclear, unspecified or
|
||||
simply wrong. I'll try to be precise as I can, and reference the
|
||||
@@ -29,19 +27,19 @@ affect the language.
|
||||
|
||||
* OBJECTS CAN BE DECLARED ANYWHERE IN THE MODULE
|
||||
|
||||
Consider this module:
|
||||
Consider this module::
|
||||
|
||||
module sample1;
|
||||
initial foo = 1;
|
||||
reg foo;
|
||||
wire tmp = bar;
|
||||
initial #1 $display("foo = %b, bar = %b", foo, tmp);
|
||||
reg foo;
|
||||
wire tmp = bar;
|
||||
initial #1 $display("foo = %b, bar = %b", foo, tmp);
|
||||
endmodule
|
||||
|
||||
Notice that the ``reg foo;'' declaration is placed after the first
|
||||
Notice that the `reg foo;` declaration is placed after the first
|
||||
initial statement. It turns out that this is a perfectly legal module
|
||||
according to the -1995 and -2000 versions of the standard. The
|
||||
statement ``reg foo;'' is a module_item_declaration which is in turn a
|
||||
statement `reg foo;` is a module_item_declaration which is in turn a
|
||||
module_item. The BNF in the appendix of IEEE1364-1995 treats all
|
||||
module_item statements equally, so no order is imposed.
|
||||
|
||||
@@ -53,12 +51,12 @@ textually before they are referenced." Such statements simply do not
|
||||
exist. (Personally, I think it is fine that they don't.)
|
||||
|
||||
The closest is the rules for implicit declarations of variables that
|
||||
are otherwise undeclared. In the above example, ``bar'' is implicitly
|
||||
declared and is therefore a wire. However, although ``initial foo = 1;''
|
||||
are otherwise undeclared. In the above example, `bar` is implicitly
|
||||
declared and is therefore a wire. However, although `initial foo = 1;`
|
||||
is written before foo is declared, foo *is* declared within the
|
||||
module, and declared legally by the BNF of the standard.
|
||||
|
||||
Here is another example:
|
||||
Here is another example::
|
||||
|
||||
module sample2;
|
||||
initial x.foo = 1;
|
||||
@@ -80,7 +78,7 @@ Icarus Verilog interprets both of these examples according to "The
|
||||
Standard As I Understand It." However, commercial tools in general
|
||||
break down with these programs. In particular, the first example
|
||||
may generate different errors depending on the tool. The most common
|
||||
error is to claim that ``foo'' is declared twice, once (implicitly) as
|
||||
error is to claim that `foo` is declared twice, once (implicitly) as
|
||||
a wire and once as a reg.
|
||||
|
||||
So the question now becomes, "Is the standard broken, or are the tools
|
||||
@@ -107,7 +105,7 @@ ordering, by requiring that modules that are used be first defined.
|
||||
* TASK AND FUNCTION PARAMETERS CANNOT HAVE EXPLICIT TYPES
|
||||
|
||||
Consider a function negate that wants to take a signed integer value
|
||||
and return its negative:
|
||||
and return its negative::
|
||||
|
||||
function integer negate;
|
||||
input [15:0] val;
|
||||
@@ -123,7 +121,7 @@ the bit pattern of a 16bit number, but that is not the point. What's
|
||||
needed is clarification on whether an input can be declared in the
|
||||
port declaration as well as in the contained block declaration.
|
||||
|
||||
As I understand the situation, this should be allowed:
|
||||
As I understand the situation, this should be allowed::
|
||||
|
||||
function integer negate;
|
||||
input [15:0] val;
|
||||
@@ -152,10 +150,10 @@ commercial tools seem to work similarly.
|
||||
|
||||
* ROUNDING OF TIME
|
||||
|
||||
When the `timescale directive is present, the compiler is supposed to
|
||||
When the \`timescale directive is present, the compiler is supposed to
|
||||
round fractional times (after scaling) to the nearest integer. The
|
||||
confusing bit here is that it is apparently conventional that if the
|
||||
`timescale directive is *not* present, times are rounded towards zero
|
||||
\`timescale directive is *not* present, times are rounded towards zero
|
||||
always.
|
||||
|
||||
|
||||
@@ -173,12 +171,12 @@ take it that x is allowed, as that is what Verilog-XL does.
|
||||
|
||||
* REPEAT LOOPS vs. REPEAT EVENT CONTROL
|
||||
|
||||
There seems to be ambiguity in how code like this should be parsed:
|
||||
There seems to be ambiguity in how code like this should be parsed::
|
||||
|
||||
repeat (5) @(posedge clk) <statement>;
|
||||
|
||||
There are two valid interpretations of this code, from the
|
||||
IEEE1364-1995 standard. One looks like this:
|
||||
IEEE1364-1995 standard. One looks like this::
|
||||
|
||||
procedural_timing_control_statement ::=
|
||||
delay_or_event_control statement_or_null
|
||||
@@ -189,7 +187,7 @@ IEEE1364-1995 standard. One looks like this:
|
||||
|
||||
If this interpretation is used, then the statement <statement> should
|
||||
be executed after the 5th posedge of clk. However, there is also this
|
||||
interpretation:
|
||||
interpretation::
|
||||
|
||||
loop_statement ::=
|
||||
repeat ( expression ) statement
|
||||
@@ -218,7 +216,7 @@ compiler may just as easily choose another width limit, for example
|
||||
However, it is not *required* that an implementation truncate at 32
|
||||
bits, and in fact Icarus Verilog does not truncate at all. It will
|
||||
make the unsized constant as big as it needs to be to hold the value
|
||||
accurately. This is especially useful in situations like this;
|
||||
accurately. This is especially useful in situations like this::
|
||||
|
||||
reg [width-1:0] foo = 17179869183;
|
||||
|
||||
@@ -237,7 +235,7 @@ truncation point.
|
||||
|
||||
* UNSIZED EXPRESSIONS AS PARAMETERS TO CONCATENATION {}
|
||||
|
||||
The Verilog standard clearly states in 4.1.14:
|
||||
The Verilog standard clearly states in 4.1.14::
|
||||
|
||||
"Unsized constant numbers shall not be allowed in
|
||||
concatenations. This is because the size of each
|
||||
@@ -257,7 +255,7 @@ simple unsized constant is accepted there, even if all the operands of
|
||||
all the operators that make up the expression are unsized integers.
|
||||
|
||||
This is a semantic problem. Icarus Verilog doesn't limit the size of
|
||||
integer constants. This is valid as stated in 2.5.1 Note 3:
|
||||
integer constants. This is valid as stated in 2.5.1 Note 3::
|
||||
|
||||
"The number of bits that make up an unsized number
|
||||
(which is a simple decimal number or a number without
|
||||
@@ -268,6 +266,8 @@ Icarus Verilog will hold any integer constant, so the size will be as
|
||||
large as it needs to be, whether that is 64bits, 128bits, or
|
||||
more. With this in mind, what is the value of these expressions?
|
||||
|
||||
::
|
||||
|
||||
{'h1_00_00_00_00}
|
||||
{'h1 << 32}
|
||||
{'h0_00_00_00_01 << 32}
|
||||
@@ -301,7 +301,7 @@ generate appropriate error messages.
|
||||
|
||||
* MODULE INSTANCE WITH WRONG SIZE PORT LIST
|
||||
|
||||
A module declaration like this declares a module that takes three ports:
|
||||
A module declaration like this declares a module that takes three ports::
|
||||
|
||||
module three (a, b, c);
|
||||
input a, b, c;
|
||||
@@ -309,7 +309,7 @@ A module declaration like this declares a module that takes three ports:
|
||||
endmodule
|
||||
|
||||
This is fine and obvious. It is also clear from the standard that
|
||||
these are legal instantiations of this module:
|
||||
these are legal instantiations of this module::
|
||||
|
||||
three u1 (x,y,z);
|
||||
three u2 ( ,y, );
|
||||
@@ -320,7 +320,7 @@ In some of the above examples, there are unconnected ports. In the
|
||||
case of u4, the pass by name connects only port b, and leaves a and c
|
||||
unconnected. u2 and u4 are the same thing, in fact, but using
|
||||
positional or by-name syntax. The next example is a little less
|
||||
obvious:
|
||||
obvious::
|
||||
|
||||
three u4 ();
|
||||
|
||||
@@ -331,7 +331,7 @@ positional list, then the wrong number of ports is given, but if it is
|
||||
an empty by-name list, it is an obviously valid instantiation. So it
|
||||
is fine to accept this case as valid.
|
||||
|
||||
These are more doubtful:
|
||||
These are more doubtful::
|
||||
|
||||
three u5(x,y);
|
||||
three u6(,);
|
||||
@@ -351,7 +351,7 @@ other.
|
||||
|
||||
* UNKNOWN VALUES IN L-VALUE BIT SELECTS
|
||||
|
||||
Consider this example:
|
||||
Consider this example::
|
||||
|
||||
reg [7:0] vec;
|
||||
wire [4:0] idx = <expr>;
|
||||
@@ -375,7 +375,7 @@ assignment will have no effect.
|
||||
|
||||
The interaction between blocking assignments in procedural code and
|
||||
logic gates in gate-level code and expressions is poorly defined in
|
||||
Verilog. Consider this example:
|
||||
Verilog. Consider this example::
|
||||
|
||||
reg a;
|
||||
reg b;
|
||||
@@ -438,7 +438,7 @@ bit and part selects.
|
||||
|
||||
* EDGES OF VECTORS
|
||||
|
||||
Consider this example:
|
||||
Consider this example::
|
||||
|
||||
reg [ 5:0] clock;
|
||||
always @(posedge clock) [do stuff]
|
||||
@@ -446,7 +446,7 @@ Consider this example:
|
||||
The IEEE1364 standard clearly states that the @(posedge clock) looks
|
||||
only at the bit clock[0] (the least significant bit) to search for
|
||||
edges. It has been pointed out by some that Verilog XL instead
|
||||
implements it as "@(posedge |clock)": it looks for a rise in the
|
||||
implements it as `@(posedge |clock)`: it looks for a rise in the
|
||||
reduction or of the vector. Cadence Design Systems technical support
|
||||
has been rumored to claim that the IEEE1364 specification is wrong,
|
||||
but NC-Verilog behaves according to the specification, and thus
|
||||
@@ -462,7 +462,7 @@ matter.
|
||||
The IEEE1364 standard clearly states that in VCD files, the $dumpoff
|
||||
section checkpoints all the dumped variables as X values. For reg and
|
||||
wire bits/vectors, this obviously means 'bx values. Icarus Verilog
|
||||
does this, for example:
|
||||
does this, for example::
|
||||
|
||||
$dumpoff
|
||||
x!
|
||||
@@ -475,7 +475,7 @@ section of the VCD file. Verilog-XL dumps "r0 !" to set the real
|
||||
variables to the dead-zone value of 0.0, whereas other tools, such as
|
||||
ModelTech, ignore real variables in this section.
|
||||
|
||||
For example (from XL):
|
||||
For example (from XL)::
|
||||
|
||||
$dumpoff
|
||||
r0 !
|
||||
@@ -485,7 +485,7 @@ For example (from XL):
|
||||
Icarus Verilog dumps NaN values for real variables in the
|
||||
$dumpoff-$end section of the VCD file. The NaN value is the IEEE754
|
||||
equivalent of an unknown value, and so better reflects the unknown
|
||||
(during the dead zone) status of the variable, like this:
|
||||
(during the dead zone) status of the variable, like this::
|
||||
|
||||
$dumpoff
|
||||
rNaN !
|
||||
@@ -0,0 +1,10 @@
|
||||
|
||||
Miscellaneous
|
||||
=============
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
ieee1364-notes
|
||||
swift
|
||||
xilinx-hint
|
||||
@@ -1,7 +1,8 @@
|
||||
|
||||
SWIFT MODEL SUPPORT FOR Icarus Verilog (PRELIMINARY)
|
||||
Swift Model Support (Preliminary)
|
||||
=================================
|
||||
|
||||
Copyright 2003 Stephen Williams
|
||||
Copyright 2003-2024 Stephen Williams
|
||||
|
||||
NOTE: SWIFT support does not work yet, these are provisional
|
||||
instructions, intended to show what's supposed to happen when I get
|
||||
@@ -24,7 +25,7 @@ When compiling your Verilog design to include a SWIFT model, you need
|
||||
to include wrappers for the model you intend to use. You may choose to
|
||||
use ncverilog or verilogxl compatible wrappers, they work the
|
||||
same. Locate your smartmodel directory, and include it in your command
|
||||
file like so:
|
||||
file like so::
|
||||
|
||||
+libdir+.../smartmodel/sol/wrappers/verilogxl
|
||||
|
||||
@@ -42,11 +43,11 @@ support for your model.
|
||||
* Execution
|
||||
|
||||
After your simulation is compiled, run the simulation with the vvp
|
||||
command, like this:
|
||||
command, like this::
|
||||
|
||||
% vvp -mcadpli a.out -cadpli=$LMC_HOME/lib/x86_linux.lib/swiftpli.so:swift_boot
|
||||
|
||||
What this command line means is:
|
||||
What this command line means is::
|
||||
|
||||
-mcadpli
|
||||
Include the cadpli compatibility module
|
||||
@@ -0,0 +1,113 @@
|
||||
|
||||
Xilinx Hint
|
||||
===========
|
||||
|
||||
For those of you who wish to use Icarus Verilog, in combination with
|
||||
the Xilinx back end (Foundation or Alliance), it can be done. I have
|
||||
run some admittedly simple (2300 equivalent gates) designs through this
|
||||
setup, targeting a Spartan XCS10.
|
||||
|
||||
Verilog:
|
||||
--------
|
||||
|
||||
Older versions of Icarus Verilog (like 19990814) couldn't synthesize
|
||||
logic buried in procedural (flip-flop) assignment. Newer versions
|
||||
(like 20000120) don't have this limitation.
|
||||
|
||||
Procedural assignments have to be given one at a time, to be
|
||||
"found" by xnfsyn. Say
|
||||
|
||||
::
|
||||
|
||||
always @ (posedge Clk) Y = newY;
|
||||
always @ (posedge Clk) Z = newZ;
|
||||
|
||||
rather than
|
||||
|
||||
::
|
||||
|
||||
always @ (posedge Clk) begin
|
||||
Y = newY;
|
||||
Z = newZ;
|
||||
end
|
||||
|
||||
Steve's xnf.txt covers most buffer and pin constructs, but I had reason
|
||||
to use a global clock net not connected to an input pin. The standard
|
||||
Verilog for a buffer, combined with a declaration to turn that into a
|
||||
BUFG, is::
|
||||
|
||||
buf BUFG( your_output_here, your_input_here );
|
||||
$attribute(BUFG,"XNF-LCA","BUFG:O,I")
|
||||
|
||||
I use post-processing on my .xnf files to add "FAST" attributes to
|
||||
output pins.
|
||||
|
||||
Running ivl:
|
||||
------------
|
||||
|
||||
The -F switches are important. The following order seems to robustly
|
||||
generate valid XNF files, and is used by "verilog -X"::
|
||||
|
||||
-Fsynth -Fnodangle -Fxnfio
|
||||
|
||||
Generating .pcf files:
|
||||
----------------------
|
||||
|
||||
The ngdbuild step seems to lose pin placement information that ivl
|
||||
puts in the XNF file. Use xnf2pcf to extract this information to
|
||||
a .pcf file, which the Xilinx place-and-route software _will_ pay
|
||||
attention to. Steve says he now makes that information available
|
||||
in an NCF file, with -fncf=<path>, but I haven't tested that.
|
||||
|
||||
Running the Xilinx back end:
|
||||
|
||||
You can presumably use the GUI, but that doesn't fit in Makefiles :-).
|
||||
Here is the command sequence in pseudo-shell-script::
|
||||
|
||||
ngdbuild -p $part $1.xnf $1.ngd
|
||||
map -p $part -o map.ncd $1.ngd
|
||||
xnf2pcf <$1.xnf >$1.pcf # see above
|
||||
par -w -ol 2 -d 0 map.ncd $1.ncd $1.pcf
|
||||
bitgen_flags = -g ConfigRate:SLOW -g TdoPin:PULLNONE -g DonePin:PULLUP \
|
||||
-g CRC:enable -g StartUpClk:CCLK -g SyncToDone:no \
|
||||
-g DoneActive:C1 -g OutputsActive:C3 -g GSRInactive:C4 \
|
||||
-g ReadClk:CCLK -g ReadCapture:enable -g ReadAbort:disable
|
||||
bitgen $1.ncd -l -w $bitgen_flags
|
||||
|
||||
The Xilinx software has diarrhea of the temp files (14, not including
|
||||
.xnf, .pcf, .ngd, .ncd, and .bit), so this sequence is best done in a
|
||||
dedicated directory. Note in particular that map.ncd is a generic name.
|
||||
|
||||
I had reason to run this remotely (and transparently within a Makefile)
|
||||
via ssh. I use the gmake rule::
|
||||
|
||||
%.bit : %.xnf
|
||||
ssh -x -a -o 'BatchMode yes' ${ALLIANCE_HOST} \
|
||||
remote_alliance ${REMOTE_DIR} $(basename $@) 2>&1 < $<
|
||||
scp ${ALLIANCE_HOST}:${REMOTE_DIR}/$@ .
|
||||
|
||||
and the remote_alliance script (on ${ALLIANCE_HOST})::
|
||||
|
||||
/bin/csh
|
||||
cd $1
|
||||
cat >! $2.xnf
|
||||
xnf2pcf <$2.xnf >! $2.pcf
|
||||
./backend $2
|
||||
|
||||
There is now a "Xilinx on Linux HOWTO" at http://www.polybus.com/xilinx_on_linux.html
|
||||
I haven't tried this yet, it looks interesting.
|
||||
|
||||
Downloading:
|
||||
------------
|
||||
|
||||
I use the XESS (http://www.xess.com/) XSP-10 development board, which
|
||||
uses the PC parallel (printer) port for downloading and interaction
|
||||
with the host. They made an old version of their download program
|
||||
public domain, posted it at http://www.xess.com/FPGA/xstools.zip ,
|
||||
and now there is a Linux port at ftp://ftp.microux.com/pub/pilotscope/xstools.tar.gz .
|
||||
|
||||
The above hints are based on my experience with Foundation 1.5 on NT
|
||||
(gack) and Alliance 2.1i on Solaris. Your mileage may vary. Good luck!
|
||||
|
||||
- Larry Doolittle <[email protected]> August 19, 1999
|
||||
updated February 1, 2000
|
||||
@@ -1,7 +1,9 @@
|
||||
|
||||
THE VVP TARGET
|
||||
The VVP Target
|
||||
==============
|
||||
|
||||
SYMBOL NAME CONVENTIONS
|
||||
Symbol Name Conventions
|
||||
-----------------------
|
||||
|
||||
There are some naming conventions that the vvp target uses for
|
||||
generating symbol names.
|
||||
@@ -18,7 +20,8 @@ this case the symbol is attached to a functor that is the output of
|
||||
the logic device.
|
||||
|
||||
|
||||
GENERAL FUNCTOR WEB STRUCTURE
|
||||
General Functor Web Structure
|
||||
-----------------------------
|
||||
|
||||
The net of gates, signals and resolvers is formed from the input
|
||||
design. The basic structure is wrapped around the nexus, which is
|
||||
@@ -0,0 +1,9 @@
|
||||
|
||||
VPI in Icarus Verilog
|
||||
=====================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
vpi
|
||||
va_math
|
||||
@@ -1,17 +1,14 @@
|
||||
|
||||
The following is from the README.va_math that was included with the
|
||||
initial contribution of the va_math module. I've removed the parts
|
||||
that are obviously not applicable, i.e. how to compile the library, to
|
||||
this bundled version of the library.
|
||||
Verilog-A math library
|
||||
======================
|
||||
|
||||
--------
|
||||
License.
|
||||
--------
|
||||
|
||||
Verilog-A math library built for Icarus Verilog
|
||||
http://www.icarus.com/eda/verilog/
|
||||
https://github.com/steveicarus/iverilog/
|
||||
|
||||
Copyright (C) 2007-2010 Cary R. ([email protected])
|
||||
Copyright (C) 2007-2024 Cary R. ([email protected])
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
@@ -27,15 +24,13 @@ License.
|
||||
with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
|
||||
|
||||
------------------------------------------
|
||||
Standard Verilog-A Mathematical Functions.
|
||||
------------------------------------------
|
||||
|
||||
The va_math VPI module implements all the standard math functions provided
|
||||
by Verilog-A as Verilog-D system functions. The names are the same except
|
||||
like all Verilog-D system functions the name must be prefixed with a '$'.
|
||||
For reference the functions are:
|
||||
For reference the functions are::
|
||||
|
||||
$ln(x) -- Natural logarithm
|
||||
$log10(x) -- Decimal logarithm
|
||||
@@ -68,8 +63,6 @@ any other limits placed on the arguments. Most libraries return +-Inf or
|
||||
NaN for results that cannot be represented with real numbers. All functions
|
||||
return a real result.
|
||||
|
||||
|
||||
------------------------------------------
|
||||
Standard Verilog-A Mathematical Constants.
|
||||
------------------------------------------
|
||||
|
||||
@@ -77,7 +70,7 @@ The Verilog-A mathematical constants can be accessed by including the
|
||||
"constants.vams" header file. It is located in the standard include
|
||||
directory. Recent version of Icarus Verilog (0.9.devel) automatically
|
||||
add this directory to the end of the list used to find include files.
|
||||
For reference the mathematical constants are:
|
||||
For reference the mathematical constants are::
|
||||
|
||||
`M_PI -- Pi
|
||||
`M_TWO_PI -- 2*Pi
|
||||
@@ -94,22 +87,14 @@ For reference the mathematical constants are:
|
||||
`M_SQRT2 -- sqrt(2)
|
||||
`M_SQRT1_2 -- 1/sqrt(2)
|
||||
|
||||
|
||||
------------------
|
||||
Using the Library.
|
||||
------------------
|
||||
|
||||
Just add "-m va_math" to your iverilog command line/command file and
|
||||
`include the "constants.vams" file as needed.
|
||||
\`include the "constants.vams" file as needed.
|
||||
|
||||
------
|
||||
Thanks
|
||||
------
|
||||
|
||||
I would like to thank Larry Doolittle for his suggestions and
|
||||
Stephen Williams for developing Icarus Verilog.
|
||||
|
||||
|
||||
--------
|
||||
The End.
|
||||
--------
|
||||
@@ -1,5 +1,6 @@
|
||||
|
||||
HOW IT WORKS
|
||||
VPI Modules in Icarus Verilog
|
||||
================================
|
||||
|
||||
The VPI interface for Icarus Verilog works by creating from a
|
||||
collection of PLI applications a single vpi module. The vpi module
|
||||
@@ -28,16 +29,18 @@ include implementations of the standard system tasks/functions. The
|
||||
additional special module names "vhdl_sys.vpi" and "vhdl_textio.vpi"
|
||||
include implementations of private functions used to support VHDL.
|
||||
|
||||
COMPILING A VPI MODULE
|
||||
Compiling A VPI Module
|
||||
----------------------
|
||||
|
||||
See the iverilog-vpi documentation.
|
||||
See the documentation under: :doc:`Using VPI <../../../usage/vpi>`
|
||||
|
||||
TRACING VPI USE
|
||||
Tracing VPI Use
|
||||
---------------
|
||||
|
||||
The vvp command includes the ability to trace VPI calls. This is
|
||||
useful if you are trying to debug a problem with your code. To
|
||||
activate tracing simply set the VPI_TRACE environment variable, with
|
||||
the path to a file where trace text gets written. For example:
|
||||
the path to a file where trace text gets written. For example::
|
||||
|
||||
setenv VPI_TRACE /tmp/foo.txt
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
|
||||
DEBUG AIDS FOR VVP
|
||||
Debug Aids For VVP
|
||||
==================
|
||||
|
||||
Debugging vvp can be fiendishly difficult, so there are some built in
|
||||
debugging aids. These are enabled by setting the environment variable
|
||||
@@ -9,7 +10,7 @@ tools can be enabled as described below.
|
||||
* .resolv
|
||||
|
||||
The .resolv can print debug information along with a label by
|
||||
specifying the debug output label on the .resolv line:
|
||||
specifying the debug output label on the .resolv line::
|
||||
|
||||
.resolv tri$<label>
|
||||
|
||||
@@ -0,0 +1,13 @@
|
||||
|
||||
VVP - Verilog Virtual Processor
|
||||
===============================
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
vvp
|
||||
opcodes
|
||||
vpi
|
||||
vthread
|
||||
debug
|
||||
|
||||
@@ -1,11 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2020 Stephen Williams ([email protected])
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
EXECUTABLE INSTRUCTION OPCODES
|
||||
Executable Instruction Opcodes
|
||||
==============================
|
||||
|
||||
Instruction opcodes all start with a % character and have 0 or more
|
||||
operands. In no case are there more than 3 operands. This chapter
|
||||
@@ -32,7 +26,8 @@ experience of implementing it for strings, I'll want to change other
|
||||
types around to using this method as well. Keep this in mind whenever
|
||||
considering adding new instructions to vvp.
|
||||
|
||||
FLAGS
|
||||
Flags
|
||||
-----
|
||||
|
||||
There are up to 16 bits in each thread that are available for
|
||||
flags. These are used as destinations for operations that return
|
||||
@@ -302,7 +297,7 @@ The results of the comparison go into flags 4, 5, 6 and 7:
|
||||
The eeq bit is set to 1 if all the bits in the vectors are exactly the
|
||||
same, or 0 otherwise. The eq bit is true if the values are logically
|
||||
the same. That is, x and z are considered equal. In other words the eq
|
||||
bit is the same as ``=='' and the eeq bit ``===''.
|
||||
bit is the same as `==` and the eeq bit `===`.
|
||||
|
||||
The lt bit is 1 if the left vector is less than the right vector, or 0
|
||||
if greater than or equal to the right vector. It is the equivalent of
|
||||
@@ -341,11 +336,6 @@ values from the real-value stack and writes the comparison result to
|
||||
bits 4/5. The expressions (a < b) and (a==b) are calculated, with (b)
|
||||
popped from the stack first, then (a).
|
||||
|
||||
* %cmp/ws <bit-l>, <bit-r>
|
||||
* %cmp/wu <bit-l>, <bit-r>
|
||||
|
||||
[compare signed/unsigned integer words.]
|
||||
|
||||
* %cmp/z
|
||||
* %cmp/x
|
||||
|
||||
@@ -469,6 +459,17 @@ This instruction terminates threads that are part of a specific
|
||||
scope. The label identifies the scope in question, and the threads are
|
||||
the threads that are currently within that scope.
|
||||
|
||||
* %disable/flow <scope-label>
|
||||
|
||||
This instruction is similar to `%disable` except that it will only disable a
|
||||
single thread of the specified scope. The disabled thread will be the thread
|
||||
closest to the current thread in the thread hierarchy. This can either be thread
|
||||
itself or one of its parents.
|
||||
|
||||
It is used to implement flow control statements called from within a thread that
|
||||
only affect the thread or its parents. E.g. SystemVerilog `return`, `continue`
|
||||
or `break`.
|
||||
|
||||
* %disable/fork
|
||||
|
||||
This instruction terminates all the detached children for the current
|
||||
@@ -517,6 +518,7 @@ that this information has been cleared. You can get an assert if
|
||||
this information is not managed correctly.
|
||||
|
||||
* %event <functor-label>
|
||||
* %event/nb <functor-label>
|
||||
|
||||
This instruction is used to send a pulse to an event object. The
|
||||
<functor-label> is an event variable. This instruction simply writes
|
||||
@@ -527,7 +529,9 @@ an arbitrary value to the event to trigger the event.
|
||||
This command emits the provided file and line information along with
|
||||
the description when it is executed. The output is sent to stderr and
|
||||
the format of the output is:
|
||||
|
||||
<file>:<line>: <description>
|
||||
|
||||
<file> is the unsigned numeric file index.
|
||||
<line> is the unsigned line number.
|
||||
<description> is a string, if string is 0 then the following default
|
||||
@@ -794,8 +798,6 @@ The /s form does signed %.
|
||||
|
||||
This opcode is the real-valued modulus of the two real values.
|
||||
|
||||
* %mov/wu <dst>, <src>
|
||||
|
||||
* %mul
|
||||
* %muli <vala>, <valb>, <wid>
|
||||
|
||||
@@ -810,6 +812,10 @@ result is pushed back on the vec4 stack.
|
||||
|
||||
This opcode multiplies two real words together.
|
||||
|
||||
* %neg/wr
|
||||
|
||||
This opcode negates the real value on top of the real stack.
|
||||
|
||||
* %nand
|
||||
|
||||
Perform the bitwise NAND of two vec4 vectors, and push the result. Each
|
||||
@@ -1333,22 +1339,23 @@ table for the xor is:
|
||||
1 xor 1 --> 0
|
||||
otherwise x
|
||||
|
||||
::
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2017 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
/*
|
||||
* Copyright (c) 2001-2024 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
@@ -1,10 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Stephen Williams ([email protected])
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
VPI WITHIN VVP
|
||||
VPI Within VVP
|
||||
==============
|
||||
|
||||
System tasks and functions in Verilog are implemented in Icarus
|
||||
Verilog by C routines written with VPI. This implies that the vvp
|
||||
@@ -19,7 +15,8 @@ vvp only implements the ones it needs. The VPI web is added into the
|
||||
design using special pseudo-ops that create the needed objects.
|
||||
|
||||
|
||||
LOADING VPI MODULES
|
||||
Loading VPI Modules
|
||||
-------------------
|
||||
|
||||
The vvp runtime loads VPI modules at runtime before the parser reads
|
||||
in the source files. This gives the modules a chance to register tasks
|
||||
@@ -38,7 +35,8 @@ the system tasks and functions. The %vpi_call instruction, once compiled,
|
||||
carries the vpiHandle of the system task.
|
||||
|
||||
|
||||
SYSTEM TASK CALLS
|
||||
System Task Calls
|
||||
-----------------
|
||||
|
||||
A system task call invokes a VPI routine, and makes available to that
|
||||
routine the arguments to the system task. The called routine gets
|
||||
@@ -61,7 +59,8 @@ instruction then only needs to be a %vpi_call with the single parameter
|
||||
that is the vpiHandle for the call.
|
||||
|
||||
|
||||
SYSTEM FUNCTION CALLS
|
||||
System Function Calls
|
||||
---------------------
|
||||
|
||||
System function calls are similar to system tasks. The only
|
||||
differences are that all the arguments are input only, and there is a
|
||||
@@ -75,7 +74,8 @@ writing a wrapper thread that calls the function when inputs change,
|
||||
and that writes the output into the containing expression.
|
||||
|
||||
|
||||
SYSTEM TASK/FUNCTION ARGUMENTS
|
||||
System Task/Function Arguments
|
||||
------------------------------
|
||||
|
||||
The arguments to each system task or call are not stored in the
|
||||
instruction op-code, but in the vpiSysTfCall object that the compiler
|
||||
@@ -91,7 +91,8 @@ all this is done, an array of vpiHandles is passed to code to create a
|
||||
vpiSysTfCall object that has all that is needed to make the call.
|
||||
|
||||
|
||||
SCOPES
|
||||
Scopes
|
||||
------
|
||||
|
||||
VPI can access scopes as objects of type vpiScope. Scopes have names
|
||||
and can also contain other sub-scopes, all of which the VPI function
|
||||
@@ -99,7 +100,7 @@ can access by the vpiInternalScope reference. Therefore, the run-time
|
||||
needs to form a tree of scopes into which other scoped VPI objects are
|
||||
placed.
|
||||
|
||||
A scope is created with a .scope directive, like so:
|
||||
A scope is created with a .scope directive, like so::
|
||||
|
||||
<label> .scope "name" [, <parent>];
|
||||
.timescale <units>;
|
||||
@@ -122,7 +123,7 @@ Objects that place themselves in a scope place themselves in the
|
||||
current scope. The current scope is the one that was last mentioned by
|
||||
a .scope directive. If the wrong scope is current, the label on a
|
||||
scope directive can be used to resume a scope. The syntax works like
|
||||
this:
|
||||
this::
|
||||
|
||||
.scope <symbol>;
|
||||
|
||||
@@ -131,7 +132,8 @@ and is used to identify the scope to be resumed. A scope resume
|
||||
directive cannot have a label.
|
||||
|
||||
|
||||
VARIABLES
|
||||
Variables
|
||||
---------
|
||||
|
||||
Reg vectors (scalars are vectors of length 1) are created by .var
|
||||
statements in the source. The .var statement includes the declared
|
||||
@@ -145,21 +147,23 @@ The VPI interface to variable (vpiReg objects) uses the MSB and LSB
|
||||
values that the user defined to describe the dimensions of the
|
||||
object.
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
::
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2024 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
@@ -1,13 +1,8 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Stephen Williams ([email protected])
|
||||
*
|
||||
*/
|
||||
|
||||
Thread Details
|
||||
==============
|
||||
|
||||
|
||||
THREAD DETAILS
|
||||
|
||||
Thread objects in vvp are created by ``.thread'' statements in the
|
||||
Thread objects in vvp are created by `.thread` statements in the
|
||||
input source file.
|
||||
|
||||
A thread object includes a program counter and private bit
|
||||
@@ -47,21 +42,23 @@ that use these registers document which register is used, and what the
|
||||
numeric value is used for. Registers 0-3 are often given fixed
|
||||
meanings to instructions that need an integer value.
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
::
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2024 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
@@ -1,9 +1,6 @@
|
||||
/*
|
||||
* Copyright (c) 2001-2017 Stephen Williams ([email protected])
|
||||
*
|
||||
*/
|
||||
|
||||
VVP SIMULATION ENGINE
|
||||
VVP Simulation Engine
|
||||
=====================
|
||||
|
||||
The VVP simulator takes as input source code not unlike assembly
|
||||
language for a conventional processor. It is intended to be machine
|
||||
@@ -12,7 +9,8 @@ compiler, so the syntax, though readable, is not necessarily
|
||||
convenient for humans.
|
||||
|
||||
|
||||
GENERAL FORMAT
|
||||
General Format
|
||||
--------------
|
||||
|
||||
The source file is a collection of statements. Each statement may have
|
||||
a label, an opcode, and operands that depend on the opcode. For some
|
||||
@@ -21,7 +19,7 @@ required.
|
||||
|
||||
Every statement is terminated by a semicolon. The semicolon is also
|
||||
the start of a comment line, so you can put comment text after the
|
||||
semicolon that terminates a statement. Like so:
|
||||
semicolon that terminates a statement. Like so::
|
||||
|
||||
Label .functor and, 0x5a, x, y ; This is a comment.
|
||||
|
||||
@@ -31,7 +29,8 @@ Statements may span multiple lines, as long as there is no text (other
|
||||
then the first character of a label) in the first column of the
|
||||
continuation line.
|
||||
|
||||
HEADER SYNTAX
|
||||
Header Syntax
|
||||
-------------
|
||||
|
||||
Before any other non-commentary code starts, the source may contain
|
||||
some header statements. These are used for passing parameters or
|
||||
@@ -57,9 +56,10 @@ expressed as a power of 10. For example, +0 is 1 second, and -9 is 1
|
||||
nanosecond. If the record is left out, then the precision is taken to
|
||||
be +0.
|
||||
|
||||
LABELS AND SYMBOLS
|
||||
Labels and Symbols
|
||||
------------------
|
||||
|
||||
Labels and symbols consist of the characters:
|
||||
Labels and symbols consist of the characters::
|
||||
|
||||
a-z
|
||||
A-Z
|
||||
@@ -88,14 +88,16 @@ There are some special symbols that in certain contexts have special
|
||||
meanings. As inputs to functors, the symbols "C<0>", "C<1>", "C<x>"
|
||||
and "C<z>" represent a constant driver of the given value.
|
||||
|
||||
NUMBERS:
|
||||
Numbers
|
||||
-------
|
||||
|
||||
decimal number tokens are limited to 64bits, and are unsigned. Some
|
||||
contexts may constrain the number size further.
|
||||
|
||||
SCOPE STATEMENTS:
|
||||
Scope Statements
|
||||
----------------
|
||||
|
||||
The syntax of a scope statement is:
|
||||
The syntax of a scope statement is::
|
||||
|
||||
<label> .scope <type>, <name> <type-name> <file> <lineno> ;
|
||||
|
||||
@@ -125,29 +127,28 @@ The <is-cell> flag is only useful for module instances. It is true
|
||||
|
||||
The short form of the scope statement is only used for root scopes.
|
||||
|
||||
PARAMETER STATEMENTS:
|
||||
Parameter Statements
|
||||
--------------------
|
||||
|
||||
Parameters are named constants within a scope. These parameters have a
|
||||
type and value, and also a label so that they can be referenced as VPI
|
||||
objects.
|
||||
|
||||
The syntax of a parameter is:
|
||||
The syntax of a parameter is::
|
||||
|
||||
<label> .param/str <name>, <value>;
|
||||
<label> .param/b <name>, <value> [<msb>,<lsb>];
|
||||
<label> .param/l <name>, <value> [<msb>,<lsb>];
|
||||
<label> .param/r <name>, <value>;
|
||||
<label> .param/str <name> <local-flag> <file-idx> <lineno>, <value>;
|
||||
<label> .param/l <name> <local-flag> <file-idx> <lineno>, <value>;
|
||||
<label> .param/r <name> <local-flag> <file-idx> <lineno>, <value>;
|
||||
|
||||
The <name> is a string that names the parameter. The name is placed in
|
||||
the current scope as a vpiParameter object. The .param suffix
|
||||
specifies the parameter type.
|
||||
specifies the parameter type::
|
||||
|
||||
.param/str -- The parameter has a string value
|
||||
.param/l -- The parameter has a logic vector value
|
||||
.param/b -- The parameter has a boolean vector value
|
||||
.param/r -- The parameter has a real value
|
||||
|
||||
The value, then, is appropriate for the data type. For example:
|
||||
The value, then, is appropriate for the data type. For example::
|
||||
|
||||
P_123 .param/str "hello", "Hello, World.";
|
||||
|
||||
@@ -155,14 +156,15 @@ The boolean and logic values can also be signed or not. If signed, the
|
||||
value is preceded by a '+' character. (Note that the value is 2s
|
||||
complement, so the '+' says only that it is signed, not positive.)
|
||||
|
||||
FUNCTOR STATEMENTS:
|
||||
Functor Statements
|
||||
------------------
|
||||
|
||||
A functor statement is a statement that uses the ``.functor''
|
||||
A functor statement is a statement that uses the `.functor`
|
||||
opcode. Functors are the basic structural units of a simulation, and
|
||||
include a type (in the form of a truth table) and up to four inputs. A
|
||||
label is required for functors.
|
||||
|
||||
The general syntax of a functor is:
|
||||
The general syntax of a functor is::
|
||||
|
||||
<label> .functor <type>, symbol_list ;
|
||||
<label> .functor <type> [<drive0> <drive1>], symbol_list ;
|
||||
@@ -189,17 +191,20 @@ combining up to four inputs down to one output.
|
||||
|
||||
- MUXZ
|
||||
|
||||
::
|
||||
|
||||
Q | A B S n/a
|
||||
--+-------------
|
||||
A | * * 0
|
||||
B | * * 1
|
||||
|
||||
|
||||
DFF AND LATCH STATEMENTS:
|
||||
DFF and Latch Statements
|
||||
------------------------
|
||||
|
||||
The Verilog language itself does not have a DFF primitive, but post
|
||||
synthesis readily creates DFF devices that are best simulated with a
|
||||
common device. Thus, there is the DFF statement to create DFF devices:
|
||||
common device. Thus, there is the DFF statement to create DFF devices::
|
||||
|
||||
<label> .dff/p <width> <d>, <clk>, <ce>;
|
||||
<label> .dff/n <width> <d>, <clk>, <ce>;
|
||||
@@ -220,7 +225,7 @@ propagate, and disables the clock until the aynchronous input is
|
||||
deasserted. Thus, they implement DFF with asynchronous clr or set.
|
||||
|
||||
Similarly, synthesis creates D-type latches, so there is the LATCH
|
||||
statement to support this:
|
||||
statement to support this::
|
||||
|
||||
<label> .latch <width> <d>, <en>;
|
||||
|
||||
@@ -229,7 +234,8 @@ type of datum at all. The device will transfer the input to the output
|
||||
whenever <en> is a logic 1.
|
||||
|
||||
|
||||
UDP STATEMENTS:
|
||||
UDP Statements
|
||||
--------------
|
||||
|
||||
A UDP statement either defines a User Defined Primitive, or
|
||||
instantiates a previously defined UDP by creating a UDP functor. A
|
||||
@@ -256,6 +262,8 @@ UDPs may also have "-": no change.
|
||||
|
||||
An input or current output state can be
|
||||
|
||||
::
|
||||
|
||||
"1": 1
|
||||
"0": 0
|
||||
"x": x
|
||||
@@ -267,6 +275,8 @@ An input or current output state can be
|
||||
For Sequential UDPs, at most one input state specification may be
|
||||
replaced by an edge specification. Valid edges are:
|
||||
|
||||
::
|
||||
|
||||
"*": (??) "_": (?0) "+": (?1) "%": (?x)
|
||||
"P": (0?) "r": (01) "Q": (0x)
|
||||
"N": (1?) "f": (10) "M": (1x)
|
||||
@@ -275,13 +285,13 @@ replaced by an edge specification. Valid edges are:
|
||||
"n": (1?) | (?0)
|
||||
"p": (0?) | (?1)
|
||||
|
||||
A combinatorial UDP is defined like this:
|
||||
A combinatorial UDP is defined like this::
|
||||
|
||||
<type> .udp/comb "<name>", <number>, "<row0>", "<row1>", ... ;
|
||||
|
||||
<type> is a label that identifies the UDP. <number> is the number of
|
||||
inputs. "<name>" is there for public identification. Sequential UDPs
|
||||
need an additional initialization value:
|
||||
need an additional initialization value::
|
||||
|
||||
<type> .udp/sequ "<name>", <number>, <init>, "<row0>", "<row1>", ... ;
|
||||
|
||||
@@ -289,7 +299,7 @@ need an additional initialization value:
|
||||
provide initial values for individual instances. <init> must be a
|
||||
number 0, 1, or 2 (for 1'bx).
|
||||
|
||||
A UDP functor instance is created so:
|
||||
A UDP functor instance is created so::
|
||||
|
||||
<label> .udp <type>, <symbol_list> ;
|
||||
|
||||
@@ -298,11 +308,12 @@ defined earlier, and <symbol_list> is a list of symbols, one for each
|
||||
input of the UDP.
|
||||
|
||||
|
||||
VARIABLE STATEMENTS:
|
||||
Variable Statements
|
||||
-------------------
|
||||
|
||||
A variable is a bit vector that can be written by behavioral code (so
|
||||
has no structural input) and propagates its output to a functor. The
|
||||
general syntax of a variable is:
|
||||
general syntax of a variable is::
|
||||
|
||||
<label> .var "name", <msb> <lsb>; Unsigned logic variable
|
||||
<label> .var/s "name", <msb> <lsb>; Signed logic variable
|
||||
@@ -338,12 +349,13 @@ Behavioral code may also invoke %force/v statements that write to port-2
|
||||
to invoke force mode. This overrides continuous assign mode until a
|
||||
long(2) is written to port-3 to disable force mode.
|
||||
|
||||
NET STATEMENTS:
|
||||
Net Statements
|
||||
--------------
|
||||
|
||||
A net is similar to a variable, except that a thread cannot write to
|
||||
it (unless it uses a force) and it is given a different VPI type
|
||||
code. The syntax of a .net statement is also similar to but not
|
||||
exactly the same as the .var statement:
|
||||
exactly the same as the .var statement::
|
||||
|
||||
<label> .net "name", <msb>, <lsb>, <symbol>;
|
||||
<label> .net/s "name", <msb>, <lsb>, <symbol>;
|
||||
@@ -377,11 +389,12 @@ The .alias statements do not create new nodes, but instead create net
|
||||
names that are aliases of an existing node. This handles special cases
|
||||
where a net has different names, possibly in different scopes.
|
||||
|
||||
CAST STATEMENTS:
|
||||
Cast Statements
|
||||
---------------
|
||||
|
||||
Sometimes nets need to be cast from a real valued net to a bit based
|
||||
net or from a bit based net to a real valued net. These statements
|
||||
are used to perform that operation:
|
||||
are used to perform that operation::
|
||||
|
||||
<label> .cast/int <width>, <symbol>;
|
||||
<label> .cast/2 <width>, <symbol>;
|
||||
@@ -396,7 +409,8 @@ For .cast/real the output <label> is a real valued net. The input
|
||||
<symbol> is expected to put bit based values and for .cast/real.s
|
||||
the bits will be interpreted as a signed value.
|
||||
|
||||
DELAY STATEMENTS:
|
||||
Delay Statements
|
||||
----------------
|
||||
|
||||
Delay nodes are structural net delay nodes that carry and manage
|
||||
propagation delays. Delay nodes can have fixed delays or variable
|
||||
@@ -405,6 +419,8 @@ delayed. The delay amount is given on the node line. Variable delay
|
||||
nodes have three extra inputs to receive the rise, fall and decay
|
||||
times that are used for delay.
|
||||
|
||||
::
|
||||
|
||||
.delay <width> ( <rise>, <fall>, <decay> ) <input> ;
|
||||
.delay <width> <input>, <rise>, <fall>, <decay> ;
|
||||
|
||||
@@ -414,20 +430,24 @@ inputs, with the first being the value to delay, and the remaining to
|
||||
be the delay values to use. <width> specifies the bit width of the
|
||||
input net, with a width of 0 used to identify a real valued net.
|
||||
|
||||
MODULE PATH DELAY STATEMENTS:
|
||||
Module Path Delay Statements
|
||||
----------------------------
|
||||
|
||||
A module path delay takes data from its input, then a list of module
|
||||
path delays. The <src> for each possible delay set is a trigger that
|
||||
activates the delay.
|
||||
|
||||
::
|
||||
|
||||
.modpath <width> <input> , [ <src> (<delays> [? <condition>]) ] ;
|
||||
|
||||
<width> specifies the bit width of the input net.
|
||||
|
||||
ARRAY INDEX STATEMENTS:
|
||||
Array Index Statements
|
||||
----------------------
|
||||
|
||||
Variables can be collected into arrays. The words of the array are
|
||||
declared separately, this statement collects them together:
|
||||
declared separately, this statement collects them together::
|
||||
|
||||
<label> .array "name", <last> <first> ;
|
||||
|
||||
@@ -438,15 +458,18 @@ The syntax below is different, in that it creates an alias for an
|
||||
existing array. The dimensions and storage are taken from the .array
|
||||
at <src>.
|
||||
|
||||
::
|
||||
|
||||
<label> .array "name", <src> ;
|
||||
|
||||
|
||||
EVENT STATEMENTS
|
||||
Event Statements
|
||||
----------------
|
||||
|
||||
Threads need to interact with the functors of a netlist synchronously,
|
||||
as well as asynchronously. There are cases where the web of functors
|
||||
needs to wake up a waiting thread. The web of functors signals threads
|
||||
through .event objects, that are declared like so:
|
||||
through .event objects, that are declared like so::
|
||||
|
||||
<label> .event <type>, <symbols_list>;
|
||||
<label> .event "name";
|
||||
@@ -458,9 +481,9 @@ itself in the notification list of the event and suspends. The
|
||||
<symbols_list> is a set of inputs that can trigger the event.
|
||||
|
||||
The <type> describes the conditions needed to trigger the event. It
|
||||
may be posedge, negedge or edge. If the type is instead a "name"
|
||||
string, then this is a named event which receives events by the %set
|
||||
instruction instead of from the output of a functor.
|
||||
may be posedge, negedge, edge or anyedge. If the type is instead a
|
||||
"name" string, then this is a named event which receives events by
|
||||
the %set instruction instead of from the output of a functor.
|
||||
|
||||
If the event has inputs (a requirement unless it is a named event)
|
||||
then it has up to 4 symbols that address functors. The event then
|
||||
@@ -472,7 +495,7 @@ events of the same edge in an event OR expression, the compiler may
|
||||
combine up to 4 into a single event.
|
||||
|
||||
If many more events need to be combined together (for example due to
|
||||
an event or expression in the Verilog) then this form can be used:
|
||||
an event or expression in the Verilog) then this form can be used::
|
||||
|
||||
<label> .event/or <symbols_list>;
|
||||
|
||||
@@ -481,13 +504,16 @@ to trigger this event. Only one of the input events needs to trigger
|
||||
to make this one go.
|
||||
|
||||
|
||||
RESOLVER STATEMENTS:
|
||||
Resolver Statements
|
||||
-------------------
|
||||
|
||||
Resolver statements are strength-aware functors with 4 inputs, but
|
||||
their job typically is to calculate a resolved output using strength
|
||||
resolution. The type of the functor is used to select a specific
|
||||
resolution function.
|
||||
|
||||
::
|
||||
|
||||
<label> .resolv tri, <symbols_list>;
|
||||
<label> .resolv tri0, <symbols_list>;
|
||||
<label> .resolv tri1, <symbols_list>;
|
||||
@@ -496,13 +522,16 @@ The output from the resolver is vvp_vector8_t value. That is, the
|
||||
result is a vector with strength included.
|
||||
|
||||
|
||||
PART SELECT STATEMENTS:
|
||||
Part Select Statements
|
||||
----------------------
|
||||
|
||||
Part select statements are functors with three inputs. They take in at
|
||||
port-0 a vector, and output a selected (likely smaller) part of that
|
||||
vector. The other inputs specify what those parts are, as a canonical
|
||||
bit number, and a width. Normally, those bits are constant values.
|
||||
|
||||
::
|
||||
|
||||
<label> .part <symbol>, <base>, <wid>;
|
||||
<label> .part/pv <symbol>, <base>, <wid>, <vector_wid>;
|
||||
<label> .part/v <symbol>, <symbol>, <wid>;
|
||||
@@ -522,13 +551,16 @@ The .part/v variation takes a vector (or long) input on port-1 as the
|
||||
base of the part select. Thus, the part select can move around. The
|
||||
.part/v.s variation treats the vector as a signed value.
|
||||
|
||||
PART CONCATENATION STATEMENTS:
|
||||
Part Concatenation Statements
|
||||
-----------------------------
|
||||
|
||||
The opposite of the part select statement is the part concatenation
|
||||
statement. The .concat statement is a functor node that takes at input
|
||||
vector values and produces a single vector output that is the
|
||||
concatenation of all the inputs.
|
||||
|
||||
::
|
||||
|
||||
<label> .concat [W X Y Z], <symbols_list> ;
|
||||
|
||||
The "[" and "]" tokens surround a set of 4 numbers that are the
|
||||
@@ -543,11 +575,12 @@ propagated, the bits are placed in the correct place in the output
|
||||
vector value, and a new output value is propagated.
|
||||
|
||||
|
||||
REPEAT VECTOR STATEMENTS:
|
||||
Repeat Vector Statements
|
||||
------------------------
|
||||
|
||||
The repeat vector statement is similar to the concatenation statement,
|
||||
expect that the input is repeated a constant number of times. The
|
||||
format of the repeat vector statement is:
|
||||
format of the repeat vector statement is::
|
||||
|
||||
<label> .repeat <wid>, <rept count>, <symbol> ;
|
||||
|
||||
@@ -556,15 +589,16 @@ the *output* vector. The <rept count> is the number of time the input
|
||||
vector value is repeated to make the output width. The input width is
|
||||
implicit from these numbers. The <symbol> is then the input source.
|
||||
|
||||
SUBSTITUTION STATEMENTS:
|
||||
Substitution Statements
|
||||
-----------------------
|
||||
|
||||
The substitution statement doesn't have a direct analog in Verilog, it
|
||||
only turns up in synthesis. It is a shorthand for forms like this:
|
||||
only turns up in synthesis. It is a shorthand for forms like this::
|
||||
|
||||
foo = <a>;
|
||||
foo[n] = <s>;
|
||||
|
||||
The format of the substitute statement is:
|
||||
The format of the substitute statement is::
|
||||
|
||||
<label> .substitute <wid>, <soff> <swid>, <symbol>, <symbol> ;
|
||||
|
||||
@@ -572,11 +606,14 @@ The first <symbol> must have the width <wid>, and is passed through,
|
||||
except for the bits within [<soff> +: <swid>]. The second <symbol>
|
||||
collects a vector that goes into that part.
|
||||
|
||||
REDUCTION LOGIC
|
||||
Reduction Logic
|
||||
---------------
|
||||
|
||||
The reduction logic statements take in a single vector, and propagate
|
||||
a single bit.
|
||||
|
||||
::
|
||||
|
||||
<label> .reduce/and <symbol> ;
|
||||
<label> .reduce/or <symbol> ;
|
||||
<label> .reduce/xor <symbol> ;
|
||||
@@ -588,22 +625,28 @@ the device has a single input, which is a vector of any width. The
|
||||
device performs the logic on all the bits of the vector (a la Verilog)
|
||||
and produces and propagates a single bit width vector.
|
||||
|
||||
EXPANSION LOGIC
|
||||
Expansion Logic
|
||||
---------------
|
||||
|
||||
Sign extension nodes are the opposite of reduction logic, in that they
|
||||
take a narrow vector, or single bit, and pad it out to a wider
|
||||
vector.
|
||||
|
||||
::
|
||||
|
||||
<label> .expand/s <wid>, <symbol> ;
|
||||
|
||||
The .expand/s node takes an input symbol and sign-extends it to the
|
||||
given width.
|
||||
|
||||
FORCE STATEMENTS (old method - remove me):
|
||||
Force Statements (old method - remove me)
|
||||
-----------------------------------------
|
||||
|
||||
A force statement creates functors that represent a Verilog force
|
||||
statement.
|
||||
|
||||
::
|
||||
|
||||
<label> .force <signal>, <symbol_list>;
|
||||
|
||||
The symbol <signal> represents the signal which is to be forced. The
|
||||
@@ -612,7 +655,7 @@ forced on the <signal>. The <label> identifies the force functors.
|
||||
There will be as many force functors as there are symbols in the
|
||||
<symbol_list>.
|
||||
|
||||
To activate and deactivate a force on a single bit, use:
|
||||
To activate and deactivate a force on a single bit, use::
|
||||
|
||||
%force <label>, <width>;
|
||||
%release <signal>;
|
||||
@@ -621,13 +664,14 @@ To activate and deactivate a force on a single bit, use:
|
||||
<signal> is the label of the functor that drives the signal that is
|
||||
being forced.
|
||||
|
||||
FORCE STATEMENTS (new method - implement me):
|
||||
Force Statements (new method - implement me)
|
||||
--------------------------------------------
|
||||
|
||||
A %force instruction, as described in the .var section, forces a
|
||||
constant value onto a .var or .net, and the matching %release releases
|
||||
that value. However, there are times when the value of a functor
|
||||
(i.e. another .net) needs to be forced onto a .var or .net. For this
|
||||
task, the %force/link instruction exists:
|
||||
task, the %force/link instruction exists::
|
||||
|
||||
%force/link <dst>, <src> ;
|
||||
%release/link <dst> ;
|
||||
@@ -640,20 +684,23 @@ node. The matching %release/link instruction removes the link (a
|
||||
releases the last %force/link, no matter where the link is from. A new
|
||||
%force/link will remove a previous link.
|
||||
|
||||
The instructions:
|
||||
The instructions::
|
||||
|
||||
%cassign/link <dst>, <src> ;
|
||||
%deassign/link <dst> ;
|
||||
|
||||
are the same concept, but for the continuous assign port.
|
||||
|
||||
STRUCTURAL ARITHMETIC STATEMENTS:
|
||||
Structural Arithmetic Statements
|
||||
--------------------------------
|
||||
|
||||
The various Verilog arithmetic operators (+-*/%) are available to
|
||||
The various Verilog arithmetic operators (`+-*/%`) are available to
|
||||
structural contexts as two-input functors that take in vectors. All of
|
||||
these operators take two inputs and generate a fixed width output. The
|
||||
input vectors will be padded if needed to get the desired output width.
|
||||
|
||||
::
|
||||
|
||||
<label> .arith/sub <wid>, <A>, <B>;
|
||||
<label> .arith/sum <wid>, <A>, <B>;
|
||||
<label> .arith/mult <wid>, <A>, <B>;
|
||||
@@ -669,12 +716,13 @@ output. I have not decided how to handle this.
|
||||
These devices support .s and .r suffixes. The .s means the node is a
|
||||
signed vector device, the .r a real valued device.
|
||||
|
||||
STRUCTURAL COMPARE STATEMENTS:
|
||||
Structural Compare Statements
|
||||
-----------------------------
|
||||
|
||||
The arithmetic statements handle various arithmetic operators that
|
||||
have wide outputs, but the comparators have single bit output, so they
|
||||
are implemented a bit differently. The syntax, however, is very
|
||||
similar:
|
||||
similar::
|
||||
|
||||
<label> .cmp/eeq <wid>, <A>, <B>;
|
||||
<label> .cmp/nee <wid>, <A>, <B>;
|
||||
@@ -693,10 +741,11 @@ versions do unsigned comparison, but the ".s" versions to signed
|
||||
comparisons. (Equality doesn't need to care about sign.)
|
||||
|
||||
|
||||
STRUCTURAL SHIFTER STATEMENTS:
|
||||
Structural Shifter Statements
|
||||
-----------------------------
|
||||
|
||||
Variable shifts in structural context are implemented with .shift
|
||||
statements:
|
||||
statements::
|
||||
|
||||
<label> .shift/l <wid>, <data symbol>, <shift symbol>;
|
||||
<label> .shift/r <wid>, <data symbol>, <shift symbol>;
|
||||
@@ -708,15 +757,18 @@ data to be shifted and must have exactly the width of the output. The
|
||||
input to port 1 is the amount to shift.
|
||||
|
||||
|
||||
STRUCTURAL FUNCTION CALLS:
|
||||
Structural Function Calls
|
||||
-------------------------
|
||||
|
||||
The .ufunc statements define a call to a user defined function.
|
||||
|
||||
::
|
||||
|
||||
<label> .ufunc/real <flabel>, <wid>,
|
||||
<isymbols> ( <psymbols> ) <ssymbol>;
|
||||
[<isymbols> ( <psymbols> )] <ssymbol>;
|
||||
|
||||
<label> .ufunc/vec4 <flabel>, <wid>,
|
||||
<isymbols> ( <psymbols> ) <ssymbol>;
|
||||
[<isymbols> ( <psymbols> )] <ssymbol>;
|
||||
|
||||
<label> .ufunc/e <flabel>, <wid>, <trigger>,
|
||||
<isymbols> ( <psymbols> ) <ssymbol>;
|
||||
@@ -744,12 +796,15 @@ before calling the function.
|
||||
|
||||
The <ssymbol> is the function scope name.
|
||||
|
||||
THREAD STATEMENTS:
|
||||
Thread Statements
|
||||
-----------------
|
||||
|
||||
Thread statements create the initial threads for a simulation. These
|
||||
represent the initial and always blocks, and possibly other causes to
|
||||
create threads at startup.
|
||||
|
||||
::
|
||||
|
||||
.thread <symbol> [, <flag>]
|
||||
|
||||
This statement creates a thread with a starting address at the
|
||||
@@ -758,7 +813,7 @@ created for the .thread statement, and it starts at the <symbol>
|
||||
addressed instruction.
|
||||
|
||||
The <flag> modifies the creation/execution behavior of the
|
||||
thread. Supported flags are:
|
||||
thread. Supported flags are::
|
||||
|
||||
$push -- Cause the thread to be pushed in the scheduler. This
|
||||
only effects startup (time 0) by arranging for pushed
|
||||
@@ -768,7 +823,7 @@ thread. Supported flags are:
|
||||
* Threads in general
|
||||
|
||||
Thread statements create the initial threads of a design. These
|
||||
include the ``initial'' and ``always'' statements of the original
|
||||
include the `initial` and `always` statements of the original
|
||||
Verilog, and possibly some other synthetic threads for various
|
||||
purposes. It is also possible to create transient threads from
|
||||
behavioral code. These are needed to support such constructs as
|
||||
@@ -817,7 +872,7 @@ words have a distinct address space from the bits.
|
||||
|
||||
* Threads and scopes
|
||||
|
||||
The Verilog ``disable'' statement deserves some special mention
|
||||
The Verilog `disable` statement deserves some special mention
|
||||
because of how it interacts with threads. In particular, threads
|
||||
throughout the design can affect (end) other threads in the design
|
||||
using the disable statement.
|
||||
@@ -840,10 +895,11 @@ by the fork atomically joins that scope. Once the transient thread
|
||||
joins the scope, it stays there until it ends. Threads never change
|
||||
scopes, not even transient threads.
|
||||
|
||||
VPI TASK/FUNCTION CALLS
|
||||
Vpi Task/Function Calls
|
||||
-----------------------
|
||||
|
||||
Threads call vpi tasks with the %vpi_call or %vpi_func
|
||||
instructions. The formats are:
|
||||
instructions. The formats are::
|
||||
|
||||
%vpi_call <file-index> <lineno> <name>, <args>... ;
|
||||
%vpi_call/w <file-index> <lineno> <name>, <args>... ;
|
||||
@@ -872,7 +928,7 @@ value returned by a system function called as a task.
|
||||
* The &A<> argument
|
||||
|
||||
The &A<> argument is a reference to the word of a variable array. The
|
||||
syntax is:
|
||||
syntax is::
|
||||
|
||||
&A '<' <symbol> , <number> '>'
|
||||
&A '<' <symbol> , <base_symbol> '>'
|
||||
@@ -886,7 +942,7 @@ starting at <base>). The base value may be signed or unsigned.
|
||||
|
||||
* The &PV<> argument
|
||||
|
||||
The &PV<> argument is a reference to part of a signal. The syntax is:
|
||||
The &PV<> argument is a reference to part of a signal. The syntax is::
|
||||
|
||||
&PV '<' <symbol> , <base> , <width> '>'
|
||||
&PV '<' <symbol> , <base_symbol> , <width> '>'
|
||||
@@ -899,7 +955,8 @@ or &A<>/&PV<> select. The third form retrieves the <base> from thread
|
||||
space using <twid> bits starting at <tbase>. The base value may be
|
||||
signed or unsigned.
|
||||
|
||||
TRUTH TABLES
|
||||
Truth Tables
|
||||
------------
|
||||
|
||||
The logic that a functor represents is expressed as a truth table. The
|
||||
functor has four inputs and one output. Each input and output has one
|
||||
@@ -912,7 +969,7 @@ implement the logic.
|
||||
|
||||
To implement the truth table, we need to assign 2-bit encodings for
|
||||
the 4-value signals. I choose, pseudo-randomly, the following
|
||||
encoding:
|
||||
encoding::
|
||||
|
||||
1'b0 : 00
|
||||
1'b1 : 01
|
||||
@@ -921,11 +978,12 @@ encoding:
|
||||
|
||||
The table is an array of 64 bytes, each byte holding 4 2-bit
|
||||
outputs. Construct a 6-bit byte address with inputs 1, 2 and 3 like
|
||||
so:
|
||||
so::
|
||||
|
||||
332211
|
||||
|
||||
The input 0 2-bits can then be used to select which of the 4 2-bit
|
||||
pairs in the 8-bit byte are the output:
|
||||
pairs in the 8-bit byte are the output::
|
||||
|
||||
MSB -> zzxx1100 <- LSB
|
||||
|
||||
@@ -936,7 +994,8 @@ none needs to be given by the programmer. It is sufficient to name the
|
||||
type to get that truth table.
|
||||
|
||||
|
||||
EXECUTABLE INSTRUCTIONS
|
||||
Executable Instructions
|
||||
-----------------------
|
||||
|
||||
Threads run executable code, much like a processor executes machine
|
||||
code. VVP has a variety of opcodes for executable instructions. All of
|
||||
@@ -949,7 +1008,8 @@ The opcodes.txt file has a more detailed description of all the
|
||||
various instructions.
|
||||
|
||||
|
||||
THE RELATIONSHIP BETWEEN FUNCTORS, THREADS AND EVENTS
|
||||
The Relationship Between Functors, Threads And Events
|
||||
-----------------------------------------------------
|
||||
|
||||
Given the above summary of the major components of vvp, some
|
||||
description of their relationship is warranted. Functors provide a
|
||||
@@ -968,7 +1028,7 @@ it is connected to, and those functors in turn create new events if
|
||||
needed.
|
||||
|
||||
Assignment events (the second of three types of events) are created
|
||||
by non-blocking assignments in behavioral code. When the ``<='' is
|
||||
by non-blocking assignments in behavioral code. When the `<=` is
|
||||
executed (a %assign in vvp) an assign event is created, which includes
|
||||
the vvp_ipoint_t pointer to the functor input to receive the value,
|
||||
as well as the value. These are distinct from propagation events because:
|
||||
@@ -993,7 +1053,7 @@ the right kind of code to cause things to happen in the design. If the
|
||||
event is a propagate or assignment event, the network of functors is
|
||||
tickled; if the event is a thread schedule, then a thread is run. The
|
||||
implementation of the event queue is not important, but currently is
|
||||
implemented as a ``skip list''. That is, it is a sorted singly linked
|
||||
implemented as a `skip list`. That is, it is a sorted singly linked
|
||||
list with skip pointers that skip over delta-time events.
|
||||
|
||||
The functor net and the threads are distinct. They communicate through
|
||||
@@ -1002,7 +1062,8 @@ is concerned, the functor net is a blob of structure that it pokes and
|
||||
prods via certain functor access instructions.
|
||||
|
||||
|
||||
VVP COMPILATION AND EXECUTION
|
||||
VVP Compilation And Execution
|
||||
-----------------------------
|
||||
|
||||
The vvp program operates in a few steps:
|
||||
|
||||
@@ -1025,7 +1086,7 @@ The vvp program operates in a few steps:
|
||||
|
||||
|
||||
The initialization step is performed by the compile_init() function in
|
||||
compile.cc. This function in turn calls all the *_init() functions in
|
||||
compile.cc. This function in turn calls all the \*_init() functions in
|
||||
other parts of the source that need initialization for compile. All
|
||||
the various sub-init functions are called <foo>_init().
|
||||
|
||||
@@ -1046,7 +1107,8 @@ the schedule_simulate() function. This does any final setup and starts
|
||||
the simulation running and the event queue running.
|
||||
|
||||
|
||||
HOW TO GET FROM THERE TO HERE
|
||||
How To Get From There To Here
|
||||
-----------------------------
|
||||
|
||||
The vvp simulation engine is designed to be able to take as input a
|
||||
compiled form of Verilog. That implies that there is a compiler that
|
||||
@@ -1057,22 +1119,22 @@ compiles Verilog into a form that the vvp engine can read.
|
||||
|
||||
Gates like AND, OR and NAND are implemented simply and obviously by
|
||||
functor statements. Any logic up to 4 inputs can be implemented with a
|
||||
single functor. For example:
|
||||
single functor. For example::
|
||||
|
||||
and gate (out, i1, i2, i3);
|
||||
|
||||
becomes:
|
||||
becomes::
|
||||
|
||||
gate .functor and, i1, i2, i3;
|
||||
|
||||
Notice the first parameter of the .functor is the type. The type
|
||||
includes a truth table that describes the output with a given
|
||||
input. If the gate is wider than four inputs, then cascade
|
||||
functors. For example:
|
||||
functors. For example::
|
||||
|
||||
and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);
|
||||
|
||||
becomes:
|
||||
becomes::
|
||||
|
||||
gate.0 .functor and, i1, i2, i3, i4;
|
||||
gate.1 .functor and, i5, i6, i7, i8;
|
||||
@@ -1081,16 +1143,16 @@ becomes:
|
||||
|
||||
* reg and other variables
|
||||
|
||||
Reg and integer are cases of what Verilog calls ``variables.''
|
||||
Reg and integer are cases of what Verilog calls `variables`.
|
||||
Variables are, simply put, things that behavioral code can assign
|
||||
to. These are not the same as ``nets,'' which include wires and the
|
||||
to. These are not the same as `nets`, which include wires and the
|
||||
like.
|
||||
|
||||
Each bit of a variable is created by a ``.var'' statement. For example:
|
||||
Each bit of a variable is created by a `.var` statement. For example::
|
||||
|
||||
reg a;
|
||||
|
||||
becomes:
|
||||
becomes::
|
||||
|
||||
a .var "a", 0, 0;
|
||||
|
||||
@@ -1099,16 +1161,17 @@ becomes:
|
||||
|
||||
Events in general are implemented as functors, but named events in
|
||||
particular have no inputs and only the event output. The way to
|
||||
generate code for these is like so:
|
||||
generate code for these is like so::
|
||||
|
||||
a .event "name";
|
||||
|
||||
This creates a functor and makes it into a mode-2 functor. Then the
|
||||
trigger statement, "-> a", cause a ``%set a, 0;'' statement be
|
||||
trigger statement, "-> a", cause a `%set a, 0;` statement be
|
||||
generated. This is sufficient to trigger the event.
|
||||
|
||||
|
||||
AUTOMATICALLY ALLOCATED SCOPES
|
||||
Automatically Allocated Scopes
|
||||
------------------------------
|
||||
|
||||
If a .scope statement has a <type> of autofunction or autotask, the
|
||||
scope is flagged as being an automatically allocated scope. The functor
|
||||
@@ -1161,21 +1224,23 @@ variable or event, the associated functor indirects through the
|
||||
current read or write context of the running thread, using its
|
||||
stored context index.
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2009 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
::
|
||||
|
||||
/*
|
||||
* Copyright (c) 2001-2024 Stephen Williams ([email protected])
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
@@ -0,0 +1,15 @@
|
||||
|
||||
Icarus Verilog Developer Support
|
||||
================================
|
||||
|
||||
This section contains documents to help support developers who contribute to
|
||||
Icarus Verilog.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
getting_started
|
||||
regression_tests
|
||||
version_stamps
|
||||
guide/index
|
||||
glossary
|
||||
@@ -0,0 +1,129 @@
|
||||
|
||||
The Regression Test Suite
|
||||
=========================
|
||||
|
||||
Icarus Verilog development includes a regression test suite that is included
|
||||
along with the source. The "ivtest" directory contains the regression test
|
||||
suite, and this suite is used by the github actions as continuous integration
|
||||
to make sure the code is always going forward.
|
||||
|
||||
NOTE: There are scripts written in perl to run the regression tests, but they
|
||||
are being gradually replaced with a newer set of scripts. It is the newer
|
||||
method that is described here.
|
||||
|
||||
Test Descriptions
|
||||
-----------------
|
||||
|
||||
Regression tests are listed in the regress-vvp.list file. Each line lists the
|
||||
name of the test and the path to the dest description. The list file is
|
||||
therefore pretty simple, and all the description of the test is in the
|
||||
description file:
|
||||
|
||||
.. code-block:: console
|
||||
|
||||
macro_str_esc vvp_tests/macro_str_esc.json
|
||||
|
||||
The "name" is a simple name, and the test-description-file is the path (relative
|
||||
the ivtest directory) to the description file. A simple test description file
|
||||
is a JSON file, like this:
|
||||
|
||||
.. code-block:: java
|
||||
|
||||
{
|
||||
"type" : "normal",
|
||||
"source" : "macro_str_esc.v",
|
||||
"gold" : "macro_str_esc"
|
||||
}
|
||||
|
||||
This description file contains all the information that the vvp_reg.py script
|
||||
needs to run the regression test. The sections below describe the keys and
|
||||
values in the description file dictionary.
|
||||
|
||||
source (required)
|
||||
^^^^^^^^^^^^^^^^^
|
||||
This specifies the name of the source file. The file is actually to be found
|
||||
in the ivltests/ directory.
|
||||
|
||||
|
||||
type (required)
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
This describes the kind of test to run. The valid values are:
|
||||
|
||||
* **normal** - Compile the source using the iverilog compiler vvp target, and if
|
||||
that succeeds execute it using the vvp command. If there is no gold file
|
||||
specified, then look for an output line with the "PASSED" string.
|
||||
|
||||
* **NI** - Mark the test as not implemented. The test will be skipped without
|
||||
running or reporting an error.
|
||||
|
||||
* **CE** - Compile, but expect the compiler to fail. This means the compiler
|
||||
command process must return an error exit.
|
||||
|
||||
* **EF** - Compile and run, but expect the run time to fail. This means the
|
||||
run time program must return an error exit.
|
||||
|
||||
* **TE** - This is specific to testing the vlog95 conversion and indicates the
|
||||
translated code failed to compile.
|
||||
|
||||
gold (optional)
|
||||
^^^^^^^^^^^^^^^
|
||||
|
||||
If this is specified, it replaces the "Passed" condition with a comparison of
|
||||
the output with a gold file. The argument is the name of the gold file set,
|
||||
which will be found in the "gold/" directory. The name here is actually the
|
||||
basename of the gold files, with separate actual gold files for the iverilog
|
||||
and vvp stderr and stdout. For example, if a "normal" test includes a gold
|
||||
file, then the program is compiled and run, and the outputs are compared with
|
||||
the gold file to make sure it ran properly.
|
||||
|
||||
The way the regression suite works, there are 4 log files created for each
|
||||
test:
|
||||
|
||||
* foo-iverilog-stdout.log
|
||||
* foo-iverilog-stderr.log
|
||||
* foo-vvp-stdout.log
|
||||
* foo-vvp-stderr.log
|
||||
|
||||
The "gold" value is the name of the gold file set. If the gold value is "foo",
|
||||
Then the actual gold files are called:
|
||||
|
||||
* gold/foo-iverilog-stdout.gold
|
||||
* gold/foo-iverilog-stderr.gold
|
||||
* gold/foo-vvp-stdout.gold
|
||||
* gold/foo/vvp-stderr.gold
|
||||
|
||||
If any of those files is empty, then the gold file doesn't need to be
|
||||
present at all. The log files and the gold files are compared byte for
|
||||
byte, so if the output you are getting is correct, then copy the log to
|
||||
the corresponding gold, and you're done.
|
||||
|
||||
If the run type is "CE" or "RE", then the gold files still work, and can
|
||||
be used to check that the error message is correct. If the gold file setting
|
||||
is present, the error return is required, and also the gold files must match.
|
||||
|
||||
iverilog-args (optional)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If this is specified, it is a list of strings that are passed as arguments to
|
||||
the iverilog command line.
|
||||
|
||||
vvp-args (optional)
|
||||
^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If this is specified, it is a list of strings that are passed as arguments to
|
||||
the vvp command. These arguments go before the vvp input file that is to be
|
||||
run.
|
||||
|
||||
vvp-args-extended (optional)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
If this is specified, it is a lost of strings that are passed as arguments to
|
||||
the vvp command. These are extended arguments, and are placed after the vvp
|
||||
input file that is being run. This is where you place things like plusargs.
|
||||
|
||||
strict, force-sv or vlog95 (optional)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
Any of these can be used to create overrides for the type, gold or
|
||||
iverilog-args when the given test type is run.
|
||||
@@ -0,0 +1,32 @@
|
||||
|
||||
Files With Version Information
|
||||
==============================
|
||||
|
||||
These are the only files that have version information in them:
|
||||
|
||||
* version_base.h -- This should be the 1 source for version info.
|
||||
* version_tag.h -- Generated automatically with git tag information.
|
||||
* verilog.spec -- Used to stamp RPM packages
|
||||
|
||||
When versions are changed, the above files need to be edited to account for
|
||||
the new version information. The following used to have version information in
|
||||
them, but now their version information is generated:
|
||||
|
||||
The version_tag.h file is generated from git tag information using
|
||||
the "make version" target, or automatically if the version_tag.h
|
||||
file doesn't exist at all. This implies that a "make version" is
|
||||
something worth doing when you do a "git pull" or create commits.
|
||||
|
||||
The files below are now edited by the Makefile:
|
||||
|
||||
* iverilog-vpi.man -- The .TH tag has a version string
|
||||
* driver/iverilog.man -- The .TH tag has a version string
|
||||
* driver-vpi/res.rc -- Used to build Windows version stamp
|
||||
* vvp/vvp.man -- The .TH tag has a version string
|
||||
|
||||
This now includes version_base.h to get the version:
|
||||
|
||||
* vpi/vams_simparam.c -- Hard coded result to simulatorVersion query
|
||||
|
||||
The test suite no longer has version specific files since it tracks along with
|
||||
the code/branch.
|
||||
@@ -0,0 +1,26 @@
|
||||
.. Icarus Verilog documentation master file, created by
|
||||
sphinx-quickstart on Sun Apr 10 16:28:38 2022.
|
||||
You can adapt this file completely to your liking, but it should at least
|
||||
contain the root `toctree` directive.
|
||||
|
||||
Icarus Verilog
|
||||
==============
|
||||
|
||||
Welcome to the documentation for Icarus Verilog.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Contents:
|
||||
|
||||
releases/index
|
||||
usage/index
|
||||
targets/index
|
||||
developer/index
|
||||
|
||||
|
||||
Indices and tables
|
||||
==================
|
||||
|
||||
* :ref:`genindex`
|
||||
* :ref:`modindex`
|
||||
* :ref:`search`
|
||||
@@ -0,0 +1,10 @@
|
||||
Icarus Verilog Release Notes
|
||||
============================
|
||||
|
||||
This section contains the release notes for all releases after and including
|
||||
V13.0. Older release notes can be found here: `<https://iverilog.fandom.com/wiki/User_Guide>`__
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
v13-0-release-note
|
||||
@@ -0,0 +1,98 @@
|
||||
🎉 Release V13.0
|
||||
================
|
||||
|
||||
The Icarus Verilog development team is pleased to announce **Release V13** of Icarus Verilog.
|
||||
|
||||
Release V13 builds on the V12 series with a focus on correctness, runtime stability, improved
|
||||
diagnostics, and incremental standard conformance improvements.
|
||||
|
||||
----
|
||||
|
||||
🐞 Bug Fix Summary
|
||||
------------------
|
||||
|
||||
Release V13 resolves numerous issues reported against V12, including:
|
||||
|
||||
* Incorrect signed constant handling.
|
||||
* Generate block naming collisions.
|
||||
* Elaboration-time assertion failures.
|
||||
* Runtime crashes in malformed corner cases.
|
||||
* Memory management issues during elaboration and simulation.
|
||||
|
||||
|
||||
----
|
||||
|
||||
🔄 Major Changes in V13
|
||||
=======================
|
||||
|
||||
🧠 Language & Elaboration Fixes
|
||||
-------------------------------
|
||||
|
||||
Release V13 includes multiple fixes to elaboration and expression handling:
|
||||
|
||||
* Resolved generate block scope resolution issues affecting nested and conditional generate constructs.
|
||||
* Corrected signed arithmetic corner cases, including shift and width propagation behavior.
|
||||
* Fixed constant expression evaluation inconsistencies during parameter elaboration.
|
||||
* Improved handling of packed and unpacked arrays in assignments and port binding corner cases.
|
||||
* Addressed elaboration-time assertion failures triggered by malformed or ambiguous constructs.
|
||||
* Corrected several source-location reporting issues for elaboration errors.
|
||||
|
||||
These changes improve standards conformance and eliminate behavioral inconsistencies observed in the V12 series.
|
||||
|
||||
----
|
||||
|
||||
⚙️ Simulator (vvp) Improvements
|
||||
-------------------------------
|
||||
|
||||
The `vvp` runtime engine has received internal stability and correctness updates:
|
||||
|
||||
* Improved event scheduling behavior in zero-delay and non-blocking assignment scenarios.
|
||||
* Fixed race-condition corner cases uncovered by expanded regression testing.
|
||||
* Eliminated memory leaks affecting long-running or large simulations.
|
||||
* Resolved crash conditions caused by invalid internal state transitions.
|
||||
* Improved robustness of `$dumpvars` handling in large hierarchical designs.
|
||||
* General runtime consistency and determinism improvements.
|
||||
|
||||
`vvp` continues to enforce version matching between the runtime and generated bytecode. Designs
|
||||
must be recompiled after upgrading.
|
||||
|
||||
----
|
||||
|
||||
🔌 VPI Updates
|
||||
--------------
|
||||
|
||||
Fixes improve VPI reliability and conformance:
|
||||
|
||||
* Corrected hierarchical object lookup behavior in specific corner cases.
|
||||
* Improved stability of callback registration during startup and shutdown.
|
||||
* Fixed invalid handle dereference scenarios that could result in segmentation faults.
|
||||
* Addressed inconsistencies in VPI object property reporting.
|
||||
|
||||
----
|
||||
|
||||
🛠 Diagnostics & Toolchain
|
||||
--------------------------
|
||||
|
||||
* Improved clarity and consistency of error and warning messages.
|
||||
* Better reporting of width mismatches and implicit net declarations.
|
||||
* More accurate diagnostic source locations.
|
||||
* Build system updates for compatibility with modern compiler toolchains.
|
||||
* Regression suite expansion and CI validation improvements.
|
||||
|
||||
----
|
||||
|
||||
📦 Upgrade Notes
|
||||
----------------
|
||||
|
||||
* Recompile all designs when upgrading from V12 or any other prior version.
|
||||
* Review warnings carefully; improved diagnostics may expose previously silent issues.
|
||||
* The only known breaking change is that wires must now be declared before use; which is required in the standard (see `gh1287 <https://github.com/steveicarus/iverilog/issues/1287>`__).
|
||||
|
||||
----
|
||||
|
||||
🙏 Acknowledgments
|
||||
------------------
|
||||
|
||||
We thank all contributors who reported issues, submitted patches, expanded regression coverage, and
|
||||
improved documentation. Release 13 reflects continued community effort toward improving correctness,
|
||||
stability, and maintainability.
|
||||
@@ -0,0 +1,23 @@
|
||||
|
||||
The Icarus Verilog Targets
|
||||
==========================
|
||||
|
||||
Icarus Verilog elaborates the design, then sends to the design to code
|
||||
generates (targets) for processing. New code generators can be added by
|
||||
external packages, but these are the code generators that are bundled with
|
||||
Icarus Verilog. The code generator is selected by the "-t" command line flag.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
tgt-vvp
|
||||
tgt-stub
|
||||
tgt-null
|
||||
tgt-vhdl
|
||||
tgt-vlog95
|
||||
tgt-pcb
|
||||
tgt-fpga
|
||||
tgt-pal
|
||||
tgt-sizer
|
||||
tgt-verilog
|
||||
tgt-blif
|
||||
@@ -1,6 +1,6 @@
|
||||
|
||||
BLIF TARGET
|
||||
-----------
|
||||
The BLIF Code Generator (-tblif)
|
||||
================================
|
||||
|
||||
The BLIF code generator supports emitting the design to a blif format
|
||||
file as accepted by:
|
||||
@@ -17,9 +17,9 @@ USAGE
|
||||
-----
|
||||
|
||||
This code generator is intended to process structural Verilog source
|
||||
code. To convert a design to blif, use this command:
|
||||
code. To convert a design to blif, use this command::
|
||||
|
||||
iverilog -tblif -o<path>.blif <source files>...
|
||||
% iverilog -tblif -o<path>.blif <source files>...
|
||||
|
||||
The source files can be Verilog, SystemVerilog, VHDL, whatever Icarus
|
||||
Verilog supports, so long as it elaborates down to the limited subset
|
||||
@@ -1,7 +1,9 @@
|
||||
|
||||
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
|
||||
The FPGA Code Generator (-tfpga)
|
||||
================================
|
||||
|
||||
Copyright 2001 Stephen Williams
|
||||
.. warning::
|
||||
This code generator is currently not included in Icarus Verilog.
|
||||
|
||||
The FPGA code generator supports a variety of FPGA devices, writing
|
||||
XNF or EDIF depending on the target. You can select the architecture
|
||||
@@ -10,6 +12,7 @@ select library primitives, and the detailed part name is written into
|
||||
the generated file for the use of downstream tools.
|
||||
|
||||
INVOKING THE FPGA TARGET
|
||||
------------------------
|
||||
|
||||
The code generator is invoked with the -tfpga flag to iverilog. It
|
||||
understands the part= and the arch= parameters, which can be set with
|
||||
@@ -61,6 +64,7 @@ Virtex-II and Virtex-II Pro devices. It uses the VIRTEX2 library, but
|
||||
is very similar to the Virtex target.
|
||||
|
||||
XNF ROOT PORTS
|
||||
--------------
|
||||
|
||||
NOTE: As parts are moved over to EDIF format, XNF support will be
|
||||
phased out. Current Xilinx implementation tools will accept EDIF
|
||||
@@ -76,6 +80,8 @@ signal. If the signal is one bit wide, then the pin name is exactly
|
||||
the module port name. If the port is a vector, then the pin number is
|
||||
given as a vector. For example, the module:
|
||||
|
||||
.. code-block::
|
||||
|
||||
module main(out, in);
|
||||
output out;
|
||||
input [2:0] in;
|
||||
@@ -84,6 +90,8 @@ given as a vector. For example, the module:
|
||||
|
||||
leads to these SIG, records:
|
||||
|
||||
.. code-block::
|
||||
|
||||
SIG, main/out, PIN=out
|
||||
SIG, main/in<2>, PIN=in2
|
||||
SIG, main/in<1>, PIN=in1
|
||||
@@ -91,6 +99,7 @@ leads to these SIG, records:
|
||||
|
||||
|
||||
EDIF ROOT PORTS
|
||||
---------------
|
||||
|
||||
The EDIF format is more explicit about the interface into an EDIF
|
||||
file. The code generator uses that control to generate an explicit
|
||||
@@ -108,6 +117,7 @@ However, since the ports are single bit ports, the name of vectors
|
||||
includes the string "[0]" where the number is the bit number. For
|
||||
example, the module:
|
||||
|
||||
.. code-block::
|
||||
|
||||
module main(out, in);
|
||||
output out;
|
||||
@@ -117,6 +127,8 @@ example, the module:
|
||||
|
||||
creates these ports:
|
||||
|
||||
.. code-block::
|
||||
|
||||
out OUTPUT
|
||||
in[0] INPUT
|
||||
in[1] INPUT
|
||||
@@ -128,6 +140,7 @@ when presenting the vector to the user.
|
||||
|
||||
|
||||
PADS AND PIN ASSIGNMENT
|
||||
-----------------------
|
||||
|
||||
The ports of a root module may be assigned to specific pins, or to a
|
||||
generic pad. If a signal (that is a port) has a PAD attribute, then
|
||||
@@ -135,14 +148,14 @@ the value of that attribute is a list of locations, one for each bit
|
||||
of the signal, that specifies the pin for each bit of the signal. For
|
||||
example:
|
||||
|
||||
.. code-block::
|
||||
|
||||
module main( (* PAD = "P10" *) output out,
|
||||
(* PAD = "P20,P21,P22" *) input [2:0] in);
|
||||
|
||||
[...]
|
||||
|
||||
endmodule
|
||||
|
||||
In this example, port ``out'' is assigned to pin 10, and port ``in''
|
||||
In this example, port `out` is assigned to pin 10, and port `in`
|
||||
is assigned to pins 20-22. If the architecture supports it, a pin
|
||||
number of 0 means let the back end tools choose a pin. The format of
|
||||
the pin number depends on the architecture family being targeted, so
|
||||
@@ -156,6 +169,7 @@ driver to the port. An error.
|
||||
|
||||
|
||||
SPECIAL DEVICES
|
||||
---------------
|
||||
|
||||
The code generator supports the "cellref" attribute attached to logic
|
||||
devices to cause specific device types be generated, instead of the
|
||||
@@ -176,12 +190,12 @@ device pins are connected.
|
||||
|
||||
|
||||
COMPILING WITH XILINX FOUNDATION
|
||||
--------------------------------
|
||||
|
||||
Compile a single-file design with command line tools like so:
|
||||
|
||||
% iverilog -parch=virtex -o foo.edf foo.vl
|
||||
% edif2ngd foo.edf foo.ngo
|
||||
% ngdbuild -p v50-pq240 foo.ngo foo.ngd
|
||||
% map -o map.ncd foo.ngd
|
||||
% par -w map.ncd foo.ncd
|
||||
Compile a single-file design with command line tools like so::
|
||||
|
||||
% iverilog -parch=virtex -o foo.edf foo.vl
|
||||
% edif2ngd foo.edf foo.ngo
|
||||
% ngdbuild -p v50-pq240 foo.ngo foo.ngd
|
||||
% map -o map.ncd foo.ngd
|
||||
% par -w map.ncd foo.ncd
|
||||
@@ -0,0 +1,7 @@
|
||||
|
||||
The null Code Generator (-tnull)
|
||||
================================
|
||||
|
||||
The null target generates no code. Invoking this code generator causes no code
|
||||
generation to happen.
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
|
||||
The PAL Code Generator (-tpal)
|
||||
==============================
|
||||
|
||||
.. warning::
|
||||
This code generator is currently not included in Icarus Verilog.
|
||||
|
||||
The PAL target generates JEDEC output for a Programmable Array Logic.
|
||||
@@ -0,0 +1,61 @@
|
||||
|
||||
The PCB Code Generator (-tpcb)
|
||||
==============================
|
||||
|
||||
The PCB target code generator is designed to allow a user to enter a netlist
|
||||
in Verilog format, then generate input files for the GNU PCB layout program.
|
||||
|
||||
Invocation
|
||||
----------
|
||||
|
||||
The PCB target code generation is invoked with the -tpcb flag to the iverilog
|
||||
command. The default output file, "a.out", contains the generated .PCB
|
||||
file. Use the "-o" flag to set the output file name explicitly. The default
|
||||
output file contains only the elements. To generate a "netlist" file, add the
|
||||
flag "-pnetlist=<path>" command line flag.
|
||||
|
||||
Altogether, this example generates the foo.net and foo.pcb files from the
|
||||
foo.v source file::
|
||||
|
||||
% iverilog -tpcb -ofoo.pcb -pnetlist=foo.net foo.v
|
||||
|
||||
Flags
|
||||
-----
|
||||
|
||||
* -o <path>
|
||||
|
||||
Set the output (pcb) file path
|
||||
|
||||
* -pnetlist=path
|
||||
|
||||
Write a netlist file to the given path.
|
||||
|
||||
Attributes Summary
|
||||
------------------
|
||||
|
||||
Attributes are attached to various constructs using the Verilog "(\* \*)"
|
||||
attribute syntax.
|
||||
|
||||
* ivl_black_box
|
||||
|
||||
Attached to a module declaration or module instantiation, this indicates
|
||||
that the module is a black box. The code generator will create an element
|
||||
for black box instances.
|
||||
|
||||
Parameters Summary
|
||||
------------------
|
||||
|
||||
Within modules, The PCB code generator uses certain parameters to control
|
||||
details. Parameters may have defaults, and can be overridden using the usual
|
||||
Verilog parameter override syntax. Parameters have preferred types.
|
||||
|
||||
* description (string, default="")
|
||||
|
||||
The "description" is a text string that describes the black box. This string
|
||||
is written into the description field of the PCB Element.
|
||||
|
||||
* value (string, default="")
|
||||
|
||||
The "value" is a text tring that describes some value for the black
|
||||
box. Like the description, the code generator does not interpret this value,
|
||||
other then to write it to the appropriate field in the PCB Element."
|
||||
@@ -0,0 +1,49 @@
|
||||
|
||||
The sizer Code Analyzer (-tsizer)
|
||||
=================================
|
||||
|
||||
The sizer target does not generate any code. Instead it will print statistics about the Verilog code.
|
||||
|
||||
It is important to synthesize the Verilog code before invoking the sizer. This can be done with the `-S` flag passed to iverilog. Note, that behavioral code can not be synthesized and will generate a warning when passed to the sizer.
|
||||
|
||||
Example command::
|
||||
|
||||
% iverilog -o sizer.txt -tsizer -S -s top input.v
|
||||
|
||||
With this example code:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module top (
|
||||
input clock,
|
||||
input reset,
|
||||
output blink
|
||||
);
|
||||
reg out;
|
||||
|
||||
always @(posedge clock) begin
|
||||
if (reset) begin
|
||||
out = 1'b0;
|
||||
end else begin
|
||||
out <= !out;
|
||||
end
|
||||
end
|
||||
|
||||
assign blink = out;
|
||||
|
||||
endmodule
|
||||
|
||||
The resulting `sizer.txt` will contain::
|
||||
|
||||
**** module/scope: top
|
||||
Flip-Flops : 1
|
||||
Logic Gates : 3
|
||||
MUX[2]: 1 slices
|
||||
LOG[13]: 1 unaccounted
|
||||
LOG[14]: 1 unaccounted
|
||||
**** TOTALS
|
||||
Flip-Flops : 1
|
||||
Logic Gates : 3
|
||||
MUX[2]: 1 slices
|
||||
LOG[13]: 1 unaccounted
|
||||
LOG[14]: 1 unaccounted
|
||||
@@ -0,0 +1,30 @@
|
||||
|
||||
The stub Code Generator (-tstub)
|
||||
================================
|
||||
|
||||
The stub code generator is a debugging aid for the Icarus Verilog compiler
|
||||
itself. It outputs a text dump of the elaborated design as it is passed to
|
||||
code generators.
|
||||
|
||||
Example command::
|
||||
|
||||
% iverilog -o stub.txt -tstub -s top input.v
|
||||
|
||||
With this example code:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module top;
|
||||
initial $display("Hello World!");
|
||||
endmodule
|
||||
|
||||
The resulting `stub.txt` will contain::
|
||||
|
||||
root module = top
|
||||
scope: top (0 parameters, 0 signals, 0 logic) module top time units = 1e0
|
||||
time precision = 1e0
|
||||
end scope top
|
||||
# There are 0 constants detected
|
||||
initial
|
||||
Call $display(1 parameters); /* hello_world.v:2 */
|
||||
<string="Hello World!", width=96, type=bool>
|
||||
@@ -0,0 +1,6 @@
|
||||
|
||||
The Verilog Code Generator (-tverilog)
|
||||
======================================
|
||||
|
||||
.. warning::
|
||||
This code generator is currently not included in Icarus Verilog.
|
||||
@@ -0,0 +1,82 @@
|
||||
|
||||
The VHDL Code Generator (-tvhdl)
|
||||
================================
|
||||
|
||||
Icarus Verilog contains a code generator to emit VHDL from the Verilog
|
||||
netlist. This allows Icarus Verilog to function as a Verilog to VHDL
|
||||
translator.
|
||||
|
||||
Invocation
|
||||
----------
|
||||
|
||||
To translate a Verilog program to VHDL, invoke "iverilog" with the -tvhdl
|
||||
flag::
|
||||
|
||||
% iverilog -t vhdl -o my_design.vhd my_design.v
|
||||
|
||||
The generated VHDL will be placed in a single file (a.out by default), even if
|
||||
the Verilog is spread over multiple files.
|
||||
|
||||
Flags
|
||||
-----
|
||||
|
||||
* -pdebug=1
|
||||
|
||||
Print progress messages as the code generator visits each part of the
|
||||
design.
|
||||
|
||||
* -pdepth=N
|
||||
|
||||
Only output VHDL entities for modules found at depth < N in the
|
||||
hierarchy. N=0, the default, outputs all entities. For example, -pdepth=1
|
||||
outputs only the top-level entity.
|
||||
|
||||
Supported Constructs
|
||||
--------------------
|
||||
|
||||
TODO
|
||||
|
||||
Limitations
|
||||
-----------
|
||||
|
||||
Signal Values and Resolution
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
There are several cases where the behaviour of the translated VHDL deviates
|
||||
from the source Verilog:
|
||||
|
||||
* The result of division by zero is x in Verilog but raises an exception in
|
||||
VHDL.
|
||||
|
||||
* Similarly, the result of reading past the end of an array in Verilog is x,
|
||||
whereas VHDL raises an exception.
|
||||
|
||||
* Any signal that is driven by two or more processes will have the value
|
||||
'U'. This is the result of the signal resolution function in the
|
||||
std_logic_1164 package.
|
||||
|
||||
Constructs Not Supported
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The following Verilog constructs cannot be translated to VHDL:
|
||||
|
||||
* fork and join
|
||||
|
||||
* force and release
|
||||
|
||||
* disable
|
||||
|
||||
* real-valued variables
|
||||
|
||||
* switches
|
||||
|
||||
* hierarchical dereferencing
|
||||
|
||||
Other Limitations
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
* The test expressions in case statements must be constant.
|
||||
|
||||
* Translation of a parameter to a corresponding VHDL generic
|
||||
declaration. Instead the default parameter value is used.
|
||||
|
||||
@@ -0,0 +1,101 @@
|
||||
|
||||
The Verilog '95 Code Generator (-tvlog95)
|
||||
=========================================
|
||||
|
||||
Icarus Verilog contains a code generator to emit 1995 compliant Verilog from
|
||||
the input Verilog netlist. This allows Icarus Verilog to function as a Verilog
|
||||
> 1995 to Verilog 1995 translator. The main goal of the project was to convert
|
||||
@*, ANSI style arguments and other constructs to something allowed in 1995
|
||||
Verilog.
|
||||
|
||||
Invocation
|
||||
----------
|
||||
|
||||
To translate a Verilog program to 1995 compliant Verilog, invoke "iverilog"
|
||||
with the -tvlog95 flag::
|
||||
|
||||
% iverilog -tvlog95 -o my_design_95.v my_design.v
|
||||
|
||||
The generated Verilog will be placed in a single file (a.out by default), even
|
||||
if the input Verilog is spread over multiple files.
|
||||
|
||||
Generator Flags
|
||||
---------------
|
||||
|
||||
* -pspacing=N
|
||||
|
||||
Set the indent spacing (the default is 2).
|
||||
|
||||
* -pallowsigned=1
|
||||
|
||||
Allow emitting the various signed constructs as an extension to 1995 Verilog
|
||||
(off by default).
|
||||
|
||||
* -pfileline=1
|
||||
|
||||
Emit the original file and line information as a comment for each generated
|
||||
line (off by default).
|
||||
|
||||
Structures that cannot be converted to 1995 compatible Verilog
|
||||
--------------------------------------------------------------
|
||||
|
||||
The following Verilog constructs are not translatable to 1995 compatible Verilog:
|
||||
|
||||
* Automatic tasks or functions.
|
||||
|
||||
* The power operator (**). Expressions of the form (2**N)**<variable> (where N
|
||||
is a constant) can be converter to a shift.
|
||||
|
||||
* Some System Verilog constructs (e.g. final blocks, ++/-- operators,
|
||||
etc.). 2-state variables are converted to 4-state variables.
|
||||
|
||||
Icarus extensions that cannot be translated:
|
||||
|
||||
* Integer constants greater than 32 bits.
|
||||
|
||||
* Real valued nets.
|
||||
|
||||
* Real modulus.
|
||||
|
||||
* Most Verilog-A constructs.
|
||||
|
||||
|
||||
Known Issues and Limitations
|
||||
----------------------------
|
||||
|
||||
Some things are just not finished and should generate an appropriate
|
||||
warning. Here is a list of the major things that still need to be looked at.
|
||||
|
||||
* There are still a few module instantiation port issues (pr1723367 and
|
||||
partselsynth).
|
||||
|
||||
* inout ports are not converted (tran-VP).
|
||||
|
||||
* Variable selects of a non-zero based vector in a continuous assignment are
|
||||
not converted.
|
||||
|
||||
* There is no support for translating a zero repeat in a continuous
|
||||
assignment. It is currently just dropped.
|
||||
|
||||
* A pull device connected to a signal select is not translated correctly (this
|
||||
may be fixed).
|
||||
|
||||
* L-value indexed part selects with a constant undefined base in a continuous
|
||||
assignment are not translated.
|
||||
|
||||
* Logic gates are not arrayed exactly the same as the input and the instance
|
||||
name is not always the same.
|
||||
|
||||
* The signed support does not generate $signed() or $unsigned() function calls
|
||||
in a continuous assignment expression.
|
||||
|
||||
* The special power operator cases are not converted in a continuous
|
||||
assignment.
|
||||
|
||||
* Currently a signed constant that sets the MSB in an unsigned context will be
|
||||
displayed as a negative value (e.g. bit = 1 translates to bit = -1).
|
||||
|
||||
* Can net arrays, etc. be unrolled?
|
||||
|
||||
* Can generate blocks be converted?
|
||||
|
||||
@@ -0,0 +1,63 @@
|
||||
|
||||
The vvp Code Generator (-tvvp)
|
||||
==============================
|
||||
|
||||
The vvp target generates code for the "vvp" run time. This is the most
|
||||
commonly used target for Icarus Verilog, as it is the main simulation engine.
|
||||
|
||||
Example command::
|
||||
|
||||
% iverilog -o top.vvp -s top hello_world.v
|
||||
|
||||
Equivalent command::
|
||||
|
||||
% iverilog -o top.vvp -tvvp -s top hello_world.v
|
||||
|
||||
With this example code in `hello_world.v`:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module top;
|
||||
initial $display("Hello World!");
|
||||
endmodule
|
||||
|
||||
The resulting `top.vvp` will contain something similar to::
|
||||
|
||||
#! /usr/local/bin/vvp
|
||||
:ivl_version "13.0 (devel)" "(s20221226-119-g8cb2e1a05-dirty)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/local/lib/ivl/system.vpi";
|
||||
:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/local/lib/ivl/va_math.vpi";
|
||||
S_0x563c3c5d1540 .scope module, "top" "top" 2 1;
|
||||
.timescale 0 0;
|
||||
.scope S_0x563c3c5d1540;
|
||||
T_0 ;
|
||||
%vpi_call 2 2 "$display", "Hello World!" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"hello_world.v";
|
||||
|
||||
The first line contains the shebang. If this file is executed, the shebang tells the shell to use vvp for the execution of this file.
|
||||
|
||||
To run the simulation, execute::
|
||||
|
||||
% ./top.vvp
|
||||
|
||||
Or you can call vvp directly::
|
||||
|
||||
% vvp top.vvp
|
||||
|
||||
Next are some directives. The first one, `:ivl_version` specifies which version of iverilog this file was created with. Next is the delay selection with "min:typical:max" values and the time precision, which we did not set specifically, so the default value is used. The next lines tell vvp which VPI modules to load and in which order. The next lines tell vvp which VPI modules to load and in what order. Next, a new scope is created with the `.scope` directive and the timescale is set with `.timescale`. A thread `T_0` is created that contains two instructions: `%vpi_call` executes the VPI function `$display` with the specified arguments, and `%end` terminates the simulation.
|
||||
|
||||
Opcodes
|
||||
-------
|
||||
|
||||
The various available opcodes can be seen in :doc:`Opcodes <../developer/guide/vvp/opcodes>`
|
||||
@@ -0,0 +1,198 @@
|
||||
|
||||
Command File Format
|
||||
===================
|
||||
|
||||
The basic format of a command file is one source file or compiler argument per
|
||||
line. Command files may also have comments of various form, and options for
|
||||
controlling the compiler.
|
||||
|
||||
Comments
|
||||
--------
|
||||
|
||||
Lines that start with a "#" character are comments. All text after the "#"
|
||||
character, is ignored.
|
||||
|
||||
The "//" character sequence also starts a comment that continues to the end of
|
||||
the line.
|
||||
|
||||
The "/\*" and "\*/" character sequences surround multi-line comments. All the
|
||||
text between the comment start and comment end sequences is ignored, even when
|
||||
that text spans multiple lines. This style of comment does not nest, so a "/\*"
|
||||
sequence within a multi-line comment is probably an error.
|
||||
|
||||
Plus-args
|
||||
---------
|
||||
|
||||
Outside of comments, lines that start with a "+" character are compiler
|
||||
arguments. These are called plusargs but they are not the same as extended
|
||||
arguments passed to the "vvp" command. The supported plusargs are definitively
|
||||
listed in the iverilog manual page.
|
||||
|
||||
The plusargs lines are generally "+<name>+..." where the name is the name of
|
||||
an switch, and the arguments are separated by "+" characters, as in::
|
||||
|
||||
+libext+.v+.V+.ver
|
||||
|
||||
With plusargs lines, the "+" character separates tokens, and not white space,
|
||||
so arguments, which may include file paths, may include spaces. A plusarg line
|
||||
is terminated by the line end.
|
||||
|
||||
The line in the command file may also be a "-y" argument. This works exactly
|
||||
the same as the::
|
||||
|
||||
-y <path>
|
||||
|
||||
argument to the compiler; it declares a library directory. The "-y" syntax is
|
||||
also a shorthand for the "+libdir" plusarg, which is a more general form::
|
||||
|
||||
+libdir+<path>...
|
||||
|
||||
File Names
|
||||
----------
|
||||
|
||||
Any lines that are not comments, compiler arguments or plusargs are taken by
|
||||
the compiler to be a source file. The path can contain any characters (other
|
||||
then comment sequences) including blanks, although leading and trailing white
|
||||
space characters are stripped. The restriction of one file name per line is in
|
||||
support of operating systems that can name files any which way. It is not
|
||||
appropriate to expect white spaces to separate file names.
|
||||
|
||||
Variable Substitution
|
||||
---------------------
|
||||
|
||||
The syntax "$(name)" is a variable reference, and may be used anywhere within
|
||||
filenames or directory names. The contents of the variable are read from the
|
||||
environment and substituted in place of the variable reference. In Windows,
|
||||
these environment variables are the very same variables that are set through
|
||||
the Control Panel->System dialog box, and in UNIX these variables are
|
||||
environment variables as exported by your shell.
|
||||
|
||||
Variables are useful for giving command files some installation
|
||||
independence. For example, one can import a vendor library with the line::
|
||||
|
||||
-y $(VENDOR)/verilog/library
|
||||
|
||||
in the command file, and the next programmer will be able to use this command
|
||||
file without editing it to point to the location of VENDOR on his
|
||||
machine. Note the use of forward slashes as a directory separator. This works
|
||||
even under Windows, so always use forward slashes in file paths and Windows
|
||||
and UNIX users will be able to share command files.
|
||||
|
||||
An Example
|
||||
----------
|
||||
|
||||
This sample::
|
||||
|
||||
# This is a comment in a command file.
|
||||
# The -y statement declares a library
|
||||
# search directory
|
||||
-y $(PROJ_LIBRARY)/prims
|
||||
#
|
||||
# This plusarg tells the compiler that
|
||||
# files in libraries may have .v or .vl
|
||||
# extensions.
|
||||
+libext+.v+.vl
|
||||
#
|
||||
main.v // This is a source file
|
||||
#
|
||||
# This is a file name with blanks.
|
||||
C:/Project Directory/file name.vl
|
||||
|
||||
is a command file that demonstrates the major syntactic elements of command
|
||||
files. It demonstrates the use of comments, variables, plusargs and file
|
||||
names. It contains a lot of information about the hypothetical project, and
|
||||
suggests that command files can be used to describe the project as a whole
|
||||
fairly concisely.
|
||||
|
||||
The syntax of command files is rich enough that they can be used to document
|
||||
and control the assembly and compilation of large Verilog programs. It is not
|
||||
unusual to have command files that are hundreds of lines long, although
|
||||
judicious use of libraries can lead to very short command files even for large
|
||||
designs. It is also practical to have different command files that pull
|
||||
together combinations of sources and compiler arguments to make different
|
||||
designs from the same Verilog source files.
|
||||
|
||||
Summary
|
||||
-------
|
||||
|
||||
Given the above description of the command file format, the following is a
|
||||
list of the special records with their meaning.
|
||||
|
||||
* +libdir+*dir-path*
|
||||
|
||||
Specify directories to be searched for library modules. The *dir-path* can
|
||||
have multiple directories, separated by "+" characters.
|
||||
|
||||
* +libdir-nocase+dir-path
|
||||
|
||||
This is the same as "+libdir+", but when searching "nocase" libraries for
|
||||
module files, case will not be taken as significant. This is useful when the
|
||||
library is on a case insensitive file system.
|
||||
|
||||
* +libext+*suffix-string*
|
||||
|
||||
Declare the suffix strings to use when searching library directories for
|
||||
Verilog files. The compiler may test a list of suffix strings to support a
|
||||
variety of naming conventions.
|
||||
|
||||
* -y dir-path
|
||||
|
||||
This is like "+libdir+" but each line takes only one path. Like "+libdir+"
|
||||
there can be multiple "-y" records to declare multiple library
|
||||
directories. This is similar to the "-y" flag on the iverilog command line.
|
||||
|
||||
* -v *file-name* or -l *file-name*
|
||||
|
||||
This declares a library file. A library file is just like any other Verilog
|
||||
source file, except that modules declared within it are not implicitly
|
||||
possible root modules.
|
||||
|
||||
NOTE: The "-l" alias is new as of 2 October 2016. It will become available
|
||||
in releases and snapshots made after that date.
|
||||
|
||||
* +incdir+*include-dir-path*
|
||||
|
||||
Declare a directory or list of directories to search for files included by
|
||||
the "include" compiler directive. The directories are searched in
|
||||
order. This is similar to the "-I" flag on the iverilog command line.
|
||||
|
||||
* +define+*name=value*
|
||||
|
||||
Define the preprocessor symbol "name" to have the string value "value". If
|
||||
the value (and the "=") are omitted, then it is assumed to be the string
|
||||
"1". This is similar to the "-D" on the iverilog command line.
|
||||
|
||||
* +timescale+*units/precision*
|
||||
|
||||
Define the default timescale. This is the timescale that is used if there is
|
||||
no other timescale directive in the Verilog source. The compiler default
|
||||
default is "+timescale+1s/1s", which this command file setting can
|
||||
change. The format of the units/precision is the same as that for the
|
||||
timescale directive in the verilog source.
|
||||
|
||||
* +toupper-filename
|
||||
|
||||
This token causes file names after this in the command file to be translated
|
||||
to uppercase. this helps with situations where a directory has passed
|
||||
through a DOS machine (or a FAT file system) and in the process the file
|
||||
names become munged. This is not meant to be used in general, but only in
|
||||
emergencies.
|
||||
|
||||
* +tolower-filename
|
||||
|
||||
The is the lowercase version of "+toupper-filename".
|
||||
|
||||
* +parameter+*name=value*
|
||||
|
||||
This token causes the compiler to override a parameter value for a top-level
|
||||
module. For example, if the module main has the parameter WIDTH, set the
|
||||
width like this "+parameter+main.WIDTH=5". Note the use of the complete
|
||||
hierarchical name. This currently only works for parameters defined in root
|
||||
(top level) modules and a defparam may override the command file value.
|
||||
|
||||
* +vhdl-work+*path*
|
||||
|
||||
When compiling VHDL, this token allows control over the directory to use for
|
||||
holding working package declarations. For example, "+vhdl-work+workdir" will
|
||||
cause the directory "workdir" to be used as a directory for holding working
|
||||
working copies of package headers.
|
||||
@@ -0,0 +1,476 @@
|
||||
|
||||
|
||||
iverilog Command Line Flags
|
||||
===========================
|
||||
|
||||
The iverilog command is the compiler/driver that takes the Verilog input and
|
||||
generates the output format, whether the simulation file or synthesis
|
||||
results. This information is at least summarized in the iverilog man page
|
||||
distributed in typical installations, but here we try to include more detail.
|
||||
|
||||
General
|
||||
-------
|
||||
|
||||
These flags affect the general behavior of the compiler.
|
||||
|
||||
* -c <cmdfile>
|
||||
|
||||
This flag selects the command file to use. The command file is an
|
||||
alternative to writing a long command line with a lot of file names and
|
||||
compiler flags. See the Command File Format page for more information.
|
||||
|
||||
* -d <flag>
|
||||
|
||||
Enable compiler debug output. These are aids for debugging Icarus Verilog,
|
||||
and this flag is not commonly used.
|
||||
The flag is one of these debug classes:
|
||||
|
||||
* scope
|
||||
* eval_tree
|
||||
* elaborate
|
||||
* synth2
|
||||
|
||||
* -g <generation flag>
|
||||
the generation is the compiler language, and specifies the language and
|
||||
extensions to use during the compile. The language level can be selected
|
||||
by a major level selector, and by controlling various features. Various
|
||||
"-g" flags can be compined. For example, to get Verilog 2001 without
|
||||
specify supoprt, use "-g2001 -gno-specify".
|
||||
|
||||
The supported flags are:
|
||||
|
||||
* 1995
|
||||
|
||||
This flag enables the IEEE1364-1995 standard.
|
||||
|
||||
* 2001
|
||||
|
||||
This flag enables the IEEE1364-2001 standard.
|
||||
|
||||
* 2001-noconfig
|
||||
|
||||
This flag enables the IEEE1364-2001 standard with config file support
|
||||
disabled. This eliminates the config file keywords from the language and
|
||||
so helps some programs written to older 2001 support compile.
|
||||
|
||||
* 2005
|
||||
This flag enables the IEEE1364-2005 standard. This is default enabled
|
||||
after v0.9.
|
||||
|
||||
* 2009
|
||||
This flag enables the IEEE1800-2009 standard, which includes
|
||||
SystemVerilog. The SystemVerilog support is not present in v0.9 and
|
||||
earlier. It is new to git master as of November 2009. Actual SystemVerilog
|
||||
support is ongoing.
|
||||
|
||||
* 2012
|
||||
|
||||
This flag enables the IEEE1800-2012 standard, which includes
|
||||
SystemVerilog.
|
||||
|
||||
* 2017
|
||||
|
||||
This flag enables the IEEE1800-2017 standard, which includes
|
||||
SystemVerilog.
|
||||
|
||||
* 2023
|
||||
|
||||
This flag enables the IEEE1800-2023 standard, which includes
|
||||
SystemVerilog.
|
||||
|
||||
* verilog-ams
|
||||
|
||||
This flag enables Verilog-AMS features that are supported by Icarus
|
||||
Verilog. (This is new as of 5 May 2008.)
|
||||
|
||||
* assertions/supported-assertions/no-assertions
|
||||
|
||||
Enable or disable SystemVerilog assertions. When enabled, assertion
|
||||
statements are elaborated. When disabled, assertion statements are parsed
|
||||
but ignored. The supported-assertions option only enables assertions that
|
||||
are currently supported by the compiler.
|
||||
|
||||
* specify/no-specify
|
||||
|
||||
Enable or disable support for specify block timing controls. When
|
||||
disabled, specify blocks are parsed but ignored. When enabled, specify
|
||||
blocks cause timing path and timing checks to be active.
|
||||
|
||||
* std-include/no-std-include
|
||||
|
||||
Enable or disable the search of a standard installation include directory
|
||||
after all other explicit include directories. This standard include
|
||||
directory is a convenient place to install standard header files that a
|
||||
Verilog program may include.
|
||||
|
||||
* relative-include/no-relative-include
|
||||
|
||||
Enable or disable adding the local files directory to the beginning of the
|
||||
include file search path. This allows files to be included relative to the
|
||||
current file.
|
||||
|
||||
* xtypes/no-xtypes
|
||||
|
||||
Enable or disable support for extended types. Enabling types allows for
|
||||
new types and type syntax that are Icarus Verilog extensions.
|
||||
|
||||
* io-range-error/no-io-range-error
|
||||
|
||||
When enabled the range for a port and any associated net declaration must
|
||||
match exactly. When disabled a scalar port is allowed to have a net
|
||||
declaration with a range (obsolete usage). A warning message will be
|
||||
printed for this combination. All other permutations are still considered
|
||||
an error.
|
||||
|
||||
* strict-ca-eval/no-strict-ca-eval
|
||||
|
||||
The standard requires that if any input to a continuous assignment
|
||||
expression changes value, the entire expression is re-evaluated. By
|
||||
default, parts of the expression that do not depend on the changed input
|
||||
value(s) are not re-evaluated. If an expression contains a call to a
|
||||
function that doesn't depend solely on its input values or that has side
|
||||
effects, the resulting behavior will differ from that required by the
|
||||
standard. Enabling strict-ca-eval will force standard compliant behavior
|
||||
(with some loss in performance).
|
||||
|
||||
* strict-expr-width/no-strict-expr-width
|
||||
|
||||
Enable or disable strict compliance with the standard rules for
|
||||
determining expression bit lengths. When disabled, the RHS of a parameter
|
||||
assignment is evaluated as a lossless expression, as is any expression
|
||||
containing an unsized constant number, and unsized constant numbers are
|
||||
not truncated to integer width.
|
||||
|
||||
* strict-declaration/no-strict-declaration
|
||||
|
||||
* strict-net-var-declaration/no-strict-net-var-declaration
|
||||
|
||||
* strict-parameter-declaration/no-strict-parameter-declaration
|
||||
|
||||
The standards require that nets, variables, and parameters must be
|
||||
declared lexically before they are used. Using -gno-strict-declaration
|
||||
will allow using a data object before declaration, with a warning. The
|
||||
warning can be suppressed with -Wno-declaration-after-use. The option
|
||||
can be applied for nets and variables and for parameters separately.
|
||||
|
||||
* shared-loop-index/no-shared-loop-index
|
||||
|
||||
Enable or disable the exclusion of for-loop control variables from
|
||||
implicit event_expression lists. When enabled, if a for-loop control
|
||||
variable (loop index) is only used inside the for-loop statement, the
|
||||
compiler will not include it in an implicit event_expression list it
|
||||
calculates for that statement or any enclosing statement. This allows the
|
||||
same control variable to be used in multiple processes without risk of
|
||||
entering an infinite loop caused by each process triggering all other
|
||||
processes that use the same variable. For strict compliance with the
|
||||
standards, this behaviour should be disabled.
|
||||
|
||||
* -i
|
||||
|
||||
Ignore missing modules. Normally it is an error if a module instantiation
|
||||
refers to an undefined module. This option causes the compiler to skip over
|
||||
that instantiation. It will also stop the compiler returning an error if
|
||||
there are no top level modules. This allows the compiler to be used to check
|
||||
incomplete designs for errors.
|
||||
|
||||
NOTE: The "-i" flag was added in v11.0.
|
||||
|
||||
* -L <path>
|
||||
|
||||
Add the specified directory to the path list used to locate VPI modules. The
|
||||
default path includes only the install directory for the system.vpi module,
|
||||
but this flag can add other directories. Multiple paths are allowed, and the
|
||||
paths will be searched in order.
|
||||
|
||||
NOTE: The "-L" flag was added in v11.0.
|
||||
|
||||
* -l <path>
|
||||
|
||||
Add the specified file to the list of source files to be compiled, but mark
|
||||
it as a library file. All modules contained within that file will be treated
|
||||
as library modules, and only elaborated if they are instantiated by other
|
||||
modules in the design.
|
||||
|
||||
NOTE: The "-l" flag is new as of 2 October 2016. It will become available in
|
||||
releases and snapshots made after that date.
|
||||
|
||||
* -M<mode>=<path>
|
||||
|
||||
Write into the file specified by path a list of files that contribute to the
|
||||
compilation of the design.
|
||||
|
||||
If _mode_ is *all* or *prefix*, this includes files that are included by
|
||||
include directives and files that are automatically loaded by library
|
||||
support as well as the files explicitly specified by the user.
|
||||
|
||||
If _mode_ is *include*, only files that are included by include directives
|
||||
are listed.
|
||||
|
||||
If _mode_ is *module*, only files that are specified by the user or that are
|
||||
automatically loaded by library support are listed. The output is one file
|
||||
name per line, with no leading or trailing space.
|
||||
|
||||
If _mode_ is *prefix*, files that are included by include directives are
|
||||
prefixed by "I " and other files are prefixed by "M ".
|
||||
|
||||
* -m<module>
|
||||
|
||||
Add this module to the list of VPI modules to be loaded by the
|
||||
simulation. Many modules can be specified, and all will be loaded, in the
|
||||
order specified. The system module is implicit and always included (and
|
||||
loaded last).
|
||||
|
||||
If the specified name includes at least one directory character, it is
|
||||
assumed to be prefixed by the path to the module, otherwise the module is
|
||||
searched for in the paths specified by preceding -L options, and if not
|
||||
found there, in the iverilog base directory.
|
||||
|
||||
NOTE: The "-m" flag was added in v11.0.
|
||||
|
||||
* -o <path>
|
||||
|
||||
Specify the output file. The <path> is the name of the file to hold the
|
||||
output. The default is "a.out".
|
||||
|
||||
* -S
|
||||
|
||||
Activate synthesis. This flag tells the compiler to do what synthesis it can
|
||||
do before calling the code generator. This flag is rarely used explicitly,
|
||||
and certain code generators will implicitly enable this flag.
|
||||
|
||||
* -u
|
||||
|
||||
Treat each source file as a separate compilation unit (as defined in
|
||||
SystemVerilog). If compiling for an IEEE1364 generation, this will just
|
||||
reset all compiler directives (including macro definitions) before each new
|
||||
file is processed.
|
||||
|
||||
NOTE: The "-u" flag was added in v11.0.
|
||||
|
||||
* -v
|
||||
|
||||
Be verbose. Print copyright information, progress messages, and some timing
|
||||
information about various compilation phases.
|
||||
|
||||
(New in snapshots after 2014-12-16) If the selected target is vvp, the -v
|
||||
switch is appended to the shebang line in the compiler output file, so
|
||||
directly executing the compiler output file will turn on verbose messages in
|
||||
vvp. This extra verbosity can be avoided by using the vvp command to
|
||||
indirectly execute the compiler output file.
|
||||
|
||||
* -V
|
||||
|
||||
Print the version information. This skips all compilation. Just print the
|
||||
version information, including version details for the various components of
|
||||
the compiler.
|
||||
|
||||
* -R
|
||||
|
||||
Print the runtime paths of the compiler. This can be useful to find, e.g.,
|
||||
the include path of vpi_user.h.
|
||||
|
||||
* -W<warning class>
|
||||
|
||||
Enable/disable warnings. All the warning types (other then "all") can be
|
||||
prefixed with no- to disable that warning.
|
||||
|
||||
* all
|
||||
|
||||
This enables almost all of the available warnings. More specifically, it
|
||||
enables these warnings::
|
||||
|
||||
-Wanachronisms
|
||||
-Wimplicit
|
||||
-Wimplicit-dimensions
|
||||
-Wdeclaration-after-use
|
||||
-Wmacro-replacement
|
||||
-Wportbind
|
||||
-Wselect-range
|
||||
-Wtimescale
|
||||
-Wsensitivity-entire-array
|
||||
|
||||
* anachronisms
|
||||
|
||||
This enables warnings for use of features that have been deprecated or
|
||||
removed in the selected generation of the Verilog language.
|
||||
|
||||
* implicit
|
||||
|
||||
This enables warnings for creation of implicit declarations. For example,
|
||||
if a scalar wire X is used but not declared in the Verilog source, this
|
||||
will print a warning at its first use.
|
||||
|
||||
* implicit-dimensions
|
||||
|
||||
This enables warnings for the case where a port declaration or a var/net
|
||||
declaration for the same name is missing dimensions. Normally, Verilog
|
||||
allows you to do this (the undecorated declaration gets its dimensions
|
||||
form the decorated declaration) but this is no longer common, and some
|
||||
other tools (notable Xilix synthesizers) do not handle this correctly.
|
||||
|
||||
This flag is supported in release 10.1 or master branch snapshots after
|
||||
2016-02-06.
|
||||
|
||||
* declaration-after-use
|
||||
|
||||
This enables warnings for declarations after use, when those are not
|
||||
flagged as errors (enabled by default). Use no-declaration-after-use
|
||||
to disable this.
|
||||
|
||||
This flag was added in version 14.0 or later (and is in the master branch
|
||||
as of 2026-03-21).
|
||||
|
||||
* macro-redefinition
|
||||
|
||||
This enables warnings when a macro is redefined, even if the macro text
|
||||
remains the same.
|
||||
|
||||
NOTE: The "macro-redefinition" flag was added in v11.0.
|
||||
|
||||
* macro-replacement
|
||||
|
||||
This enables warnings when a macro is redefined and the macro text
|
||||
changes. Use no-macro-redefinition to disable this,
|
||||
|
||||
NOTE: The "macro-replacement" flag was added in v11.0.
|
||||
|
||||
* portbind
|
||||
|
||||
This enables warnings for ports of module instantiations that are not
|
||||
connected properly, but probably should be. Dangling input ports, for
|
||||
example, will generate a warning.
|
||||
|
||||
* select-range
|
||||
|
||||
This enables warnings for constant out-of-bound selects. This includes
|
||||
partial or fully out-of-bound select as well as a select containing a 'bx
|
||||
or 'bz in the index.
|
||||
|
||||
* timescale
|
||||
|
||||
This enables warnings for inconsistent use of the timescale directive. It
|
||||
detects if some modules have no timescale, or if modules inherit timescale
|
||||
from another file. Both probably mean that timescales are inconsistent,
|
||||
and simulation timing can be confusing and dependent on compilation order.
|
||||
|
||||
* infloop
|
||||
|
||||
This enables warnings for always statements that may have runtime infinite
|
||||
loops (i.e. has paths with zero or no delay). This class of warnings is
|
||||
not included in -Wall and hence does not have a no- variant. A fatal error
|
||||
message will always be printed when the compiler can determine that there
|
||||
will definitely be an infinite loop (all paths have no or zero delay).
|
||||
|
||||
When you suspect an always statement is producing a runtine infinite loop,
|
||||
use this flag to find the always statements that need to have their logic
|
||||
verified. it is expected that many of the warnings will be false
|
||||
positives, since the code treats the value of all variables and signals as
|
||||
indeterninite.
|
||||
|
||||
* sensitivity-entire-vector
|
||||
|
||||
This enables warnings for when a part select with an "always @*" statement
|
||||
results in the entire vector being added to the implicit sensitivity
|
||||
list. Although this behavior is prescribed by the IEEE standard, it is not
|
||||
what might be expected and can have performance implications if the vector
|
||||
is large.
|
||||
|
||||
* sensitivity-entire-array
|
||||
|
||||
This enables warnings for when a word select with an "always @*" statement
|
||||
results in the entire array being added to the implicit sensitivity
|
||||
list. Although this behavior is prescribed by the IEEE standard, it is not
|
||||
what might be expected and can have performance implications if the array
|
||||
is large.
|
||||
|
||||
* floating-nets
|
||||
|
||||
This enables warnings for nets that are present but have no drivers.
|
||||
|
||||
This flag was added in version 11.0 or later (and is in the master branch
|
||||
as of 2015-10-01).
|
||||
|
||||
* -y<libdir>
|
||||
|
||||
Append the directory to the library module search path. When the compiler
|
||||
finds an undefined module, it looks in these directories for files with the
|
||||
right name.
|
||||
|
||||
* -Y<suf>
|
||||
|
||||
Appends suf to the list of file extensions that are used to resolve an
|
||||
undefined module to a file name. Should be specified before any -y flag. For
|
||||
example, this command::
|
||||
|
||||
% iverilog -Y .sv -y sources src.v
|
||||
|
||||
will try to resolve any undefined module m by looking into the directory
|
||||
sources and checking if there exist files named m.v or m.sv.
|
||||
|
||||
|
||||
Preprocessor Flags
|
||||
------------------
|
||||
|
||||
These flags control the behavior of the preprocessor. They are similar to
|
||||
flags for the typical "C" compiler, so C programmers will find them familiar.
|
||||
|
||||
* -E
|
||||
|
||||
This flag is special in that it tells the compiler to only run the
|
||||
preprocessor. This is useful for example as a way to resolve preprocessing
|
||||
for other tools. For example, this command::
|
||||
|
||||
% iverilog -E -ofoo.v -DKEY=10 src1.v src2.v
|
||||
|
||||
runs the preprocessor on the source files src1.v and src2.v and produces the
|
||||
single output file foo.v that has all the preprocessing (including header
|
||||
includes and ifdefs) processed.
|
||||
|
||||
* -D<macro>
|
||||
|
||||
Assign a value to the macro name. The format of this flag is one of::
|
||||
|
||||
-Dkey=value
|
||||
-Dkey
|
||||
|
||||
The key is defined to have the given value. If no value is given, then it is
|
||||
assumed to be "1". The above examples are the same as these defines in
|
||||
Verilog source::
|
||||
|
||||
`define key value
|
||||
`define key
|
||||
|
||||
* -I<path>
|
||||
|
||||
Append directory <path> to list of directories searched for Verilog include
|
||||
files. The -I switch may be used many times to specify several directories
|
||||
to search, the directories are searched in the order they appear on the
|
||||
command line.
|
||||
|
||||
Elaboration Flags
|
||||
-----------------
|
||||
|
||||
These are flags that pass information to the elaboration steps.
|
||||
|
||||
* -P<symbol>=<value>
|
||||
|
||||
Define a parameter using the defparam behavior to override a parameter
|
||||
values. This can only be used for parameters of root module instances.
|
||||
|
||||
* -s <topmodule>
|
||||
|
||||
Specify the top level module to elaborate. Icarus Verilog will by default
|
||||
choose modules that are not instantiated in any other modules, but sometimes
|
||||
that is not sufficient, or instantiates too many modules. If the user
|
||||
specifies one or more root modules with "-s" flags, then they will be used
|
||||
as root modules instead.
|
||||
|
||||
* -Tmin, -Ttyp, -Tmax
|
||||
|
||||
Select the timings to use. The Verilog language allows many timings to be
|
||||
specified as three numbers, min:typical:max, but for simulation you need to
|
||||
choose which set to use. The "-Tmin" flag tells the compiler to at
|
||||
elaboration time choose "min" times. The default is "-Ttyp".
|
||||
|
||||
Target Flags
|
||||
------------
|
||||
@@ -0,0 +1,167 @@
|
||||
|
||||
Getting Started With Icarus Verilog
|
||||
===================================
|
||||
|
||||
Before getting started with actual examples, here are a few notes on
|
||||
conventions. First, command lines and sequences take the same arguments on all
|
||||
supported operating environments, including Linux, Windows and the various
|
||||
Unix systems. When an example command is shown in a figure, the generic prompt
|
||||
character "% " takes the place of whatever prompt string is appropriate for
|
||||
your system. Under Windows, the commands are invoked in a command window.
|
||||
|
||||
Second, when creating a file to hold Verilog code, it is common to use the
|
||||
".v" or the ".vl" suffix. This is not a requirement imposed by Icarus Verilog,
|
||||
but a useful convention. Some people also use the suffixes ".ver" or even
|
||||
".vlg". Examples in this book will use the ".v" suffix.
|
||||
|
||||
So let us start. Given that you are going to use Icarus Verilog as part of
|
||||
your design process, the first thing to do as a designer is learn how to
|
||||
compile and execute even the most trivial design. For the purposes of
|
||||
simulation, we use as our example the most trivial simulation, a simple Hello,
|
||||
World program.
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module hello;
|
||||
initial
|
||||
begin
|
||||
$display("Hello, World");
|
||||
$finish ;
|
||||
end
|
||||
endmodule
|
||||
|
||||
Use a text editor to place the program in a text file, hello.v, then compile
|
||||
this program with the command::
|
||||
|
||||
% iverilog -o hello hello.v
|
||||
|
||||
The results of this compile are placed into the file "hello", because the "-o"
|
||||
flag tells the compiler where to place the compiled result. Next, execute the
|
||||
compiled program like so::
|
||||
|
||||
% vvp hello
|
||||
Hello, World
|
||||
|
||||
And there it is, the program has been executed. So what happened? The first
|
||||
step, the "iverilog" command, read and interpreted the source file, then
|
||||
generated a compiled result. The compiled form may be selected by command line
|
||||
switches, but the default is the "vvp" format, which is actually run later, as
|
||||
needed. The "vvp" command of the second step interpreted the "hello" file from
|
||||
the first step, causing the program to execute.
|
||||
|
||||
The "iverilog" and "vvp" commands are the most important commands available to
|
||||
users of Icarus Verilog. The "iverilog" command is the compiler, and the "vvp"
|
||||
command is the simulation runtime engine. What sort of output the compiler
|
||||
actually creates is controlled by command line switches, but normally it
|
||||
produces output in the default vvp format, which is in turn executed by the
|
||||
vvp program.
|
||||
|
||||
As designs get larger and more complex, they gain hierarchy in the form of
|
||||
modules that are instantiated within others, and it becomes convenient to
|
||||
organize them into multiple files. A common convention is to write one
|
||||
moderate sized module per file (or group related tiny modules into a single
|
||||
file) then combine the files of the design together during compilation. For
|
||||
example, the counter model in counter.v
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module counter(out, clk, reset);
|
||||
|
||||
parameter WIDTH = 8;
|
||||
|
||||
output [WIDTH-1 : 0] out;
|
||||
input clk, reset;
|
||||
|
||||
reg [WIDTH-1 : 0] out;
|
||||
wire clk, reset;
|
||||
|
||||
always @(posedge clk or posedge reset)
|
||||
if (reset)
|
||||
out <= 0;
|
||||
else
|
||||
out <= out + 1;
|
||||
|
||||
endmodule // counter
|
||||
|
||||
and the test bench in counter_tb.v
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module test;
|
||||
|
||||
/* Make a reset that pulses once. */
|
||||
reg reset = 0;
|
||||
initial begin
|
||||
# 17 reset = 1;
|
||||
# 11 reset = 0;
|
||||
# 29 reset = 1;
|
||||
# 11 reset = 0;
|
||||
# 100 $stop;
|
||||
end
|
||||
|
||||
/* Make a regular pulsing clock. */
|
||||
reg clk = 0;
|
||||
always #5 clk = !clk;
|
||||
|
||||
wire [7:0] value;
|
||||
counter c1 (value, clk, reset);
|
||||
|
||||
initial
|
||||
$monitor("At time %t, value = %h (%0d)",
|
||||
$time, value, value);
|
||||
endmodule // test
|
||||
|
||||
are written into different files.
|
||||
|
||||
The "iverilog" command supports multi-file designs by two methods. The
|
||||
simplest is to list the files on the command line::
|
||||
|
||||
% iverilog -o my_design counter_tb.v counter.v
|
||||
% vvp my_design
|
||||
|
||||
This command compiles the design, which is spread across two input files, and
|
||||
generates the compiled result into the "my_design" file. This works for small
|
||||
to medium sized designs, but gets cumbersome when there are lots of files.
|
||||
|
||||
Another technique is to use a commandfile, which lists the input files in a
|
||||
text file. For example, create a text file called "file_list.txt" with the
|
||||
files listed one per line::
|
||||
|
||||
counter.v
|
||||
counter_tb.v
|
||||
|
||||
Then compile and execute the design with a command like so::
|
||||
|
||||
% iverilog -o my_design -c file_list.txt
|
||||
% vvp my_design
|
||||
|
||||
The command file technique clearly supports much larger designs simply by
|
||||
saving you the trouble of listing all the source files on the command
|
||||
line. Name the files that are part of the design in the command file and use
|
||||
the "-c" flag to tell iverilog to read the command file as a list of Verilog
|
||||
input files.
|
||||
|
||||
As designs get more complicated, they almost certainly contain many Verilog
|
||||
modules that represent the hierarchy of your design. Typically, there is one
|
||||
module that instantiates other modules but is not instantiated by any other
|
||||
modules. This is called a root module. Icarus Verilog chooses as roots (There
|
||||
can be more than one root) all the modules that are not instantiated by other
|
||||
modules. If there are no such modules, the compiler will not be able to choose
|
||||
any root, and the designer must use the "-sroot" switch to identify the root
|
||||
module, like this::
|
||||
|
||||
% iverilog -s main -o hello hello.v
|
||||
|
||||
If there are multiple candidate roots, all of them will be elaborated. The
|
||||
compiler will do this even if there are many root modules that you do not
|
||||
intend to simulate, or that have no effect on the simulation. This can happen,
|
||||
for example, if you include a source file that has multiple modules, but are
|
||||
only really interested in some of them. The "-s" flag identifies a specific
|
||||
root module and also turns off the automatic search for other root
|
||||
modules. You can use this feature to prevent instantiation of unwanted roots.
|
||||
|
||||
As designs get even larger, they become spread across many dozens or even
|
||||
hundreds of files. When designs are that complex, more advanced source code
|
||||
management techniques become necessary. These are described in later chapters,
|
||||
along with other advanced design management techniques supported by Icarus
|
||||
Verilog.
|
||||
@@ -0,0 +1,173 @@
|
||||
|
||||
Icarus Verilog Extensions
|
||||
=========================
|
||||
|
||||
Icarus Verilog supports certain extensions to the baseline IEEE 1364
|
||||
standard. Some of these are picked from extended variants of the
|
||||
language, such as SystemVerilog, and some are expressions of internal
|
||||
behavior of Icarus Verilog, made available as a tool debugging aid.
|
||||
|
||||
Don't use any of these extensions if you want to keep your code portable
|
||||
across other Verilog compilers.
|
||||
|
||||
System Functions
|
||||
----------------
|
||||
|
||||
``$is_signed(<expr>)``
|
||||
^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This function returns 1 if the expression contained is signed, or 0 otherwise.
|
||||
This is mostly of use for compiler regression tests.
|
||||
|
||||
``$bits(<expr>)``, ``$sizeof(<expr>)``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
The ``$bits`` system function returns the size in bits of the expression that
|
||||
is its argument. The result of this function is undefined if the argument
|
||||
doesn't have a self-determined size.
|
||||
|
||||
The ``$sizeof`` system function is deprecated in favour of ``$bits``, which is
|
||||
the same thing, but included in the SystemVerilog definition.
|
||||
|
||||
``$simtime()``
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
This returns as a 64bit value the simulation time, unscaled by the time units
|
||||
of the local scope. This is different from the ``$time`` and ``$stime``
|
||||
functions which return the scaled times. This function is added for regression
|
||||
testing of the compiler and run time, but can be used by applications who
|
||||
really want the simulation time.
|
||||
|
||||
Note that the simulation time can be confusing if there are lots of different
|
||||
```timescales`` within a design. It is not in general possible to predict
|
||||
what the simulation precision will turn out to be.
|
||||
|
||||
``$mti_random()``, ``$mti_dist_uniform``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
These functions are similar to the IEEE 1364 standard ``$random`` functions,
|
||||
but they use the Mersenne Twister (MT19937) algorithm. This is considered an
|
||||
excellent random number generator, but does not generate the same sequence as
|
||||
the standardized ``$random``.
|
||||
|
||||
System Tasks
|
||||
------------
|
||||
|
||||
``$readmempath``
|
||||
^^^^^^^^^^^^^^^^
|
||||
|
||||
The ``$readmemb`` and ``$readmemh`` system tasks read text files that contain
|
||||
data values to populate memories. Normally, those files are found in a current
|
||||
working directory. The ``$readmempath()`` system task can be used to create a
|
||||
search path for those files. For example:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
reg [7:0] mem [0:7];
|
||||
initial begin
|
||||
$readmemh("datafile.txt", mem);
|
||||
end
|
||||
|
||||
This assumes that "datafile.txt" is in the current working directory where
|
||||
the ``vvp`` command is running. But with the ``$readmempath``, one can specify
|
||||
a search path:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
reg [7:0] mem [0:7];
|
||||
initial begin
|
||||
$readmempath(".:alternative:/global/defaults");
|
||||
$readmemh("datafile.txt", mem);
|
||||
end
|
||||
|
||||
In this example, "datafile.txt" is searched for in each of the directories
|
||||
in the above list (separated by ":" characters). The first located instance
|
||||
is the one that is used. So for example, if "./datafile.txt" exists, then it
|
||||
is read instead of "/global/defaults/datafile.txt" even if the latter exists.
|
||||
|
||||
``$finish_and_return(code)``
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This task operates the same as the ``$finish`` system task, but adds the
|
||||
feature of specifying an exit code for the interpreter. This can be useful in
|
||||
automated test environments to indicate whether the simulation finished with
|
||||
or without errors.
|
||||
|
||||
Extended Verilog Data Types
|
||||
---------------------------
|
||||
|
||||
This feature is turned on by the generation flag "-gxtypes" and turned
|
||||
off by the generation flag "-gno-xtypes". It is turned on by default.
|
||||
|
||||
Icarus Verilog adds support for extended data types. This extended
|
||||
type syntax is based on a proposal by Cadence Design Systems,
|
||||
originally as an update to the IEEE 1364 standard. Icarus Verilog
|
||||
currently only takes the new primitive types from the proposal.
|
||||
|
||||
SystemVerilog provides the same functionality using somewhat different
|
||||
syntax. This extension is maintained for backwards compatibility.
|
||||
|
||||
- Types
|
||||
|
||||
Extended data types separates the concept of net/variable from the
|
||||
data type. Both nets and variables can declared with any data
|
||||
type. The primitive types available are::
|
||||
|
||||
logic - The familiar 0, 1, x and z, optionally with strength.
|
||||
bool - Limited to only 0 and 1
|
||||
real - 64-bit real values
|
||||
|
||||
Nets with logic type may have multiple drivers with strength, and the
|
||||
value is resolved the usual way. Only logic values may be driven to
|
||||
logic nets, so bool values driven onto logic nets are implicitly
|
||||
converted to logic.
|
||||
|
||||
Nets with any other type may not have multiple drivers. The compiler
|
||||
should detect the multiple drivers and report an error.
|
||||
|
||||
- Declarations
|
||||
|
||||
The declaration of a net is extended to include the type of the wire,
|
||||
with the syntax::
|
||||
|
||||
wire <type> <wire-assignment-list>... ;
|
||||
|
||||
The <type>, if omitted, is taken to be logic. The "wire" can be any of
|
||||
the net keywords. Wires can be logic, bool, real, or vectors of logic
|
||||
or bool. Some valid examples::
|
||||
|
||||
wire real foo = 1.0;
|
||||
tri logic bus[31:0];
|
||||
wire bool addr[23:0];
|
||||
... and so on.
|
||||
|
||||
The declarations of variables is similar. The "reg" keyword is used to
|
||||
specify that this is a variable. Variables can have the same data
|
||||
types as nets.
|
||||
|
||||
- Ports
|
||||
|
||||
Module and task ports in standard Verilog are restricted to logic
|
||||
types. This extension removes that restriction, allowing any of
|
||||
the above types to pass through the port consistent with the
|
||||
continuous assignment connectivity that is implied by the type.
|
||||
|
||||
- Expressions
|
||||
|
||||
Expressions in the face of real values is covered by the baseline
|
||||
Verilog standard.
|
||||
|
||||
The bool type supports the same operators as the logic type, with the
|
||||
obvious differences imposed by the limited domain.
|
||||
|
||||
Comparison operators (not case compare) return logic if either of
|
||||
their operands is logic. If both are bool or real (including mix of
|
||||
bool and real) then the result is bool. This is because comparison of
|
||||
bools and reals always return exactly true or false.
|
||||
|
||||
Case comparison returns bool. This differs from baseline Verilog,
|
||||
which strictly speaking returns a logic, but only 0 or 1 values.
|
||||
|
||||
Arithmetic operators return real if either of their operands is real,
|
||||
otherwise they return logic if either of their operands is logic. If
|
||||
both operands are bool, they return bool.
|
||||
@@ -0,0 +1,438 @@
|
||||
|
||||
Icarus Verilog Quirks
|
||||
=====================
|
||||
|
||||
This is a list of known quirks that are presented by Icarus Verilog. The idea
|
||||
of this chapter is to call out ways that Icarus Verilog differs from the
|
||||
standard, or from other implementations.
|
||||
|
||||
This is NOT AN EXHAUSTIVE LIST. If something is missing from this list, let us
|
||||
know and we can add documentation.
|
||||
|
||||
Unsized Numeric Constants are Not Limited to 32 Bits
|
||||
----------------------------------------------------
|
||||
|
||||
The Verilog standard allows Verilog implementations to limit the size of
|
||||
unsized constants to a bit width of at least 32. That means that a constant
|
||||
17179869183 (``36'h3_ffff_ffff``) may overflow some compilers. In fact, it
|
||||
is common to limit these values to 32 bits. However, a compiler may just as
|
||||
easily choose another width limit, for example 64 bits. That value is
|
||||
equally good.
|
||||
|
||||
However, it is not required that an implementation truncate at 32 bits, and
|
||||
in fact Icarus Verilog does not truncate at all. It will make the unsized
|
||||
constant as big as it needs to be to hold the value accurately. This is
|
||||
especially useful in situations like this;
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
reg [width-1:0] foo = 17179869183;
|
||||
|
||||
The programmer wants the constant to take on the width of the reg, which in
|
||||
this example is parameterized. Since constant sizes cannot be parameterized,
|
||||
the programmer ideally gives an unsized constant, which the compiler then
|
||||
expands/contracts to match the l-value.
|
||||
|
||||
Also, by choosing to not ever truncate, Icarus Verilog can handle code written
|
||||
for a 64 bit compiler as easily as for a 32 bit compiler. In particular, any
|
||||
constants that the user does not expect to be arbitrarily truncated by their
|
||||
compiler will also not be truncated by Icarus Verilog, no matter what that
|
||||
other compiler chooses as a truncation point.
|
||||
|
||||
Unsized Expressions
|
||||
-------------------
|
||||
|
||||
Icarus Verilog classes any expression containing an unsized numeric constant
|
||||
or unsized parameter value that is not part of a self-determined operand as
|
||||
an unsized expression. When calculating the bit width of an unsized expression,
|
||||
it extends the width of the expression to avoid arithmetic overflow or
|
||||
underflow; in other words, the expression width will be made large enough to
|
||||
represent any possible arithmetic result of the expression. If the expression
|
||||
contains operations that do not follow the normal rules of arithmetic (e.g. an
|
||||
explicit or implicit cast between signed and unsigned values), the expression
|
||||
width will be extended to at least the width of an integer.
|
||||
|
||||
An exception to the above is made if the expression contains a shift or power
|
||||
operator with a right hand operand that is a non-constant unsized expression.
|
||||
In this case any expansion of the expression width due to that operation is
|
||||
limited to the width of an integer, to avoid excessive expression widths
|
||||
(without this, an expression such as ``2**(i-1)``, where ``i`` is an integer,
|
||||
would be expanded to 2\**33 bits).
|
||||
|
||||
The above behaviour is a deviation from the Verilog standard, which states
|
||||
that when calculating an expression width, the width of an unsized constant
|
||||
number is the same as the width of an integer. If you need strict standard
|
||||
compliance (for compatibility with other EDA tools), then the compiler has
|
||||
a command line option, ``-gstrict-expr-width``, which disables the special
|
||||
treatment of unsized expressions. With this option, the compiler will output
|
||||
a warning message if an unsized numeric constant is encountered that cannot
|
||||
be represented in integer-width bits and will truncate the value.
|
||||
|
||||
If you are simulating synthesisable code, it is recommended that the
|
||||
``-gstrict-expr-width`` option is used, as this eliminates a potential
|
||||
source of synthesis vs. simulation mismatches.
|
||||
|
||||
Unsized Parameters
|
||||
------------------
|
||||
|
||||
Icarus Verilog classes any parameter declaration that has no explicit or
|
||||
implicit range specification as an unsized parameter declaration. When
|
||||
calculating the bit width of the final value expression for the parameter,
|
||||
it follows the same rules as it does for unsized expressions, regardless of
|
||||
whether or not the expression contains any unsized numeric constants.
|
||||
|
||||
If the final value expression for an unsized parameter is an unsized
|
||||
expression (i.e. does contain unsized numeric constants), any subsequent use
|
||||
of that parameter will be treated as if it was an unsized numeric constant.
|
||||
If not, it will be treated as if it was a numeric constant of the appropriate
|
||||
size. For example, with the declarations:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
localparam Value1 = 'd3 + 'd2;
|
||||
localparam Value2 = 2'd3 + 2'd2;
|
||||
|
||||
any subsequent use of ``Value1`` will be treated as if the programmer had
|
||||
written ``'d5`` and any subsequent use of ``Value2`` will be treated as if
|
||||
the programmer had written ``3'd5``. In particular, note that ``Value2`` can
|
||||
be used as a concatenation operand, but ``Value1`` cannot.
|
||||
|
||||
The above behaviour is a deviation from the Verilog standard. As for
|
||||
unsized expressions, if you need strict standard compliance. use the
|
||||
``-gstrict-expr-width`` compiler option.
|
||||
|
||||
Unsized Expressions as Arguments to Concatenation
|
||||
-------------------------------------------------
|
||||
|
||||
The Verilog standard clearly states in 4.1.14:
|
||||
|
||||
"Unsized constant numbers shall not be allowed in concatenations. This
|
||||
is because the size of each operand in the concatenation is needed to
|
||||
calculate the complete size of the concatenation."
|
||||
|
||||
So for example the expression ``{1'b0, 16}`` is clearly illegal. It also stands
|
||||
to reason that ``{1'b0, 15+1}`` is illegal, for exactly the same justification.
|
||||
What is the size of the expression (15+1)? Furthermore, it is reasonable to
|
||||
expect that (16) and (15+1) are exactly the same so far as the compiler is
|
||||
concerned.
|
||||
|
||||
Unfortunately, Cadence seems to feel otherwise. In particular, it has been
|
||||
reported that although ``{1'b0, 16}`` causes an error, ``{1'b0, 15+1}`` is
|
||||
accepted. Further testing shows that any expression other than a simple
|
||||
unsized constant is accepted there, even if all the operands of all the
|
||||
operators that make up the expression are unsized integers.
|
||||
|
||||
This is a semantic problem. Icarus Verilog doesn't limit the size of integer
|
||||
constants. This is valid as stated in 2.5.1 Note 3:
|
||||
|
||||
"The number of bits that make up an unsized number (which is a simple
|
||||
decimal number or a number without the size specification) shall be
|
||||
**at least** 32." [emphasis added]
|
||||
|
||||
Icarus Verilog will hold any integer constant, so the size will be as large as
|
||||
it needs to be, whether that is 64 bits, 128 bits, or more. With this in mind,
|
||||
what is the value of these expressions?
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
{'h1_00_00_00_00}
|
||||
{'h1 << 32}
|
||||
{'h0_00_00_00_01 << 32}
|
||||
{'h5_00_00_00_00 + 1}
|
||||
|
||||
These examples show that the standard is justified in requiring that the
|
||||
operands of concatenation have size. The dispute is what it takes to cause
|
||||
an expression to have a size, and what that size is. Verilog-XL claims that
|
||||
(16) does not have a size, but (15+1) does. The size of the expression (15+1)
|
||||
is the size of the adder that is created, but how wide is the adder when
|
||||
adding unsized constants?
|
||||
|
||||
One might note that the quote from section 4.1.14 says "Unsized constant
|
||||
numbers shall not be allowed." It does not say "Unsized expressions...", so
|
||||
arguably accepting (15+1) or even (16+0) as an operand to a concatenation is
|
||||
not a violation of the letter of the law. However, the very next sentence of
|
||||
the quote expresses the intent, and accepting (15+1) as having a more defined
|
||||
size then (16) seems to be a violation of that intent.
|
||||
|
||||
Whatever a compiler decides the size is, the user has no way to predict it,
|
||||
and the compiler should not have the right to treat (15+1) any differently
|
||||
then (16). Therefore, Icarus Verilog takes the position that such expressions
|
||||
are unsized and are not allowed as operands to concatenations. Icarus Verilog
|
||||
will in general assume that operations on unsized numbers produce unsized
|
||||
results. There are exceptions when the operator itself does define a size,
|
||||
such as the comparison operators or the reduction operators. Icarus Verilog
|
||||
will generate appropriate error messages.
|
||||
|
||||
Scope of Macro Defines Doesn't Extend into Libraries
|
||||
----------------------------------------------------
|
||||
|
||||
Icarus Verilog does preprocess modules that are loaded from libraries via the
|
||||
``-y`` mechanism to substitute macros and load includes. However, the only
|
||||
macros defined during compilation of an automatically loaded library module
|
||||
file are those that it defines itself (or includes) or that are defined on the
|
||||
command line or in the command file. Specifically, macros defined in the non-
|
||||
library source files are not remembered when the library module is loaded, and
|
||||
macros defined in a library module do not escape into the rest of the design.
|
||||
This is intentional. If it were otherwise, then compilation results might vary
|
||||
depending on the order that libraries are loaded, and that is unacceptable.
|
||||
|
||||
For example, given sample library module ``a.v``:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
`define MACRO_A 1
|
||||
module a(input x);
|
||||
always @(x) $display("x=",x);
|
||||
endmodule
|
||||
|
||||
and sample library module ``b.v``:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module b(input y);
|
||||
`ifdef MACRO_A
|
||||
always @(y) $display("MACRO_A is defined",,y);
|
||||
`else
|
||||
always @(y) $display("MACRO_A is NOT defined",,y);
|
||||
`endif
|
||||
endmodule
|
||||
|
||||
If a program instantiates both of these modules, there is no way to know
|
||||
which will be loaded first by the compiler, so if the definition of
|
||||
``MACRO_A`` in ``a.v`` were to escape, then there is no way to predict or
|
||||
control whether ``MACRO_A`` is defined when ``b.v`` is processed. So the
|
||||
preprocessor processes automatic library module files as if they are in
|
||||
their own compilation unit, and you can know that ``MACRO_A`` will not be
|
||||
defined in ``b.v`` unless it is defined on the command line (a ``-D`` flag)
|
||||
or in the command file (a ``+define+`` record.)
|
||||
|
||||
Of course if ``a.v`` and ``b.v`` were listed in the command file or on the
|
||||
command line, then the situation is different; the order is clear. The files
|
||||
are processed as if they were concatenated in the order that they are listed
|
||||
on the command line. The non-library modules are all together in a main
|
||||
compilation unit, and they are all processed before any library modules are
|
||||
loaded.
|
||||
|
||||
It is said that some commercial compilers do allow macro definitions to span
|
||||
library modules. That's just plain weird. However, there is a special case
|
||||
that Icarus Verilog does handle. Preprocessor definitions that are made in
|
||||
files explicitly listed on the command line or in the command file, do pass
|
||||
into implicitly loaded library files. For example, given the source file
|
||||
``x.v``:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module main;
|
||||
reg foo;
|
||||
b dut(foo);
|
||||
endmodule
|
||||
`define MACRO_A
|
||||
|
||||
and the library module file ``b.v`` described above, the situation is well
|
||||
defined, assuming the ``x.v`` file is listed on the command line or in the
|
||||
command file. The library module will receive the ``MACRO_A`` definition
|
||||
from the last explicitly loaded source file. The position of the define of
|
||||
``MACRO_A`` in the explicitly loaded source files does not matter, as all
|
||||
explicitly loaded source files are preprocessed before any library files
|
||||
are loaded.
|
||||
|
||||
Continuous Assign L-Values Can Implicit-Define Wires
|
||||
----------------------------------------------------
|
||||
|
||||
The IEEE 1364-2001 standard, Section 3.5, lists the cases where nets may be
|
||||
implicitly created. These include:
|
||||
|
||||
- identifier is a module port
|
||||
- identifier is passed as a port to a primitive or module
|
||||
|
||||
This does not seem to include continuous assignment l-values (or r-values)
|
||||
so the standard does not justify allowing implicit declarations of nets by
|
||||
continuous assignment.
|
||||
|
||||
However, it has been reported that many Verilog compilers, including the big
|
||||
name tools, do allow this. So, Icarus Verilog will allow it as well, as an
|
||||
extension. If ``-gxtypes`` (the default) is used, this extension is enabled.
|
||||
To turn off this behavior, use the ``-gno-xtypes`` flag.
|
||||
|
||||
Dumping Array Words (``$dumpvars``)
|
||||
-----------------------------------
|
||||
|
||||
Icarus has the ability to dump individual array words. They are only dumped
|
||||
when explicitly passed to $dumpvars. They are not dumped by default. For
|
||||
example given the following:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module top;
|
||||
reg [7:0] array [2:0];
|
||||
initial begin
|
||||
$dumpvars(0, array[0], array[1]);
|
||||
...
|
||||
end
|
||||
endmodule
|
||||
|
||||
``array[0]`` and ``array[1]`` will be dumped whenever they change value. They
|
||||
will be displayed as an escaped identifier and GTKWave fully supports this.
|
||||
Note that this is an implicitly created escaped identifier that could conflict
|
||||
with an explicitly created escaped identifier. You can automate adding the
|
||||
array word by adding an index definition
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
integer idx;
|
||||
|
||||
and replacing the previous $dumpvars statement with
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
for (idx = 0; idx < 2; idx = idx + 1) $dumpvars(0, array[idx]);
|
||||
|
||||
This will produce the same results as the previous example, but it is much
|
||||
easier to specify/change which elements are to be dumped. One important note
|
||||
regarding this syntax. Most system tasks/functions keep the variable selection
|
||||
(for this case it is a variable array word selection) context. If ``$dumpvars``
|
||||
did this then all callback created would point to this element and would use
|
||||
the same index which for the example above would have the value 2. This is
|
||||
certainly not what is desired and for this special case when ``$dumpvars``
|
||||
executes it uses the current index value to create a constant array selection
|
||||
and that is monitored instead of the original variable selection.
|
||||
|
||||
Referencing Declarations Within an Unnamed Generate Block
|
||||
---------------------------------------------------------
|
||||
|
||||
The IEEE 1364-2005 standard permits generate blocks to be unnamed, but states:
|
||||
|
||||
"If the generate block selected for instantiation is not named, it still
|
||||
creates a scope; but the declarations within it cannot be referenced using
|
||||
hierarchical names other than from within the hierarchy instantiated by the
|
||||
generate block itself."
|
||||
|
||||
The standard later defines a scheme for automatically naming the unnamed
|
||||
scopes for use with external interfaces.
|
||||
|
||||
Icarus Verilog implements the defined automatic naming scheme, but does not
|
||||
prevent the automatically generated names being used in a hierarchical
|
||||
reference. This behaviour is harmless - the automatically generated names are
|
||||
guaranteed to be unique within the enclosing scope, so there is no possibility
|
||||
of confusion with explicit scope names. However, to maintain code portability,
|
||||
it is recommended that this behavior is not exploited.
|
||||
|
||||
``%g/%G`` Format Specifiers
|
||||
---------------------------
|
||||
|
||||
In the IEEE 1364-2001 standard there is a general statement that the real
|
||||
number format specifiers will use the full formatting capabilities of C.
|
||||
This is then followed by an example that describes ``%10.3g``. The example
|
||||
description would be correct for the ``%e`` format specifier which should
|
||||
always have three fractional digits, but the ``%g`` format specifier does
|
||||
not work that way. For it the ``.3`` specifies that there will be three
|
||||
significant digits. What this means is that ``%g`` will always produce one
|
||||
less significant digit than ``%e`` and will only match the output from ``%f``
|
||||
for certain values. For example:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
module top_level;
|
||||
real rval;
|
||||
initial begin
|
||||
rval = 1234567890;
|
||||
$display("This is g and e: %10.3g, %10.3e.", rval, rval);
|
||||
rval = 0.1234567890;
|
||||
$display("This is g and f: %10.3g, %10.3f.", rval, rval);
|
||||
rval = 1.234567890;
|
||||
$display("This is more g and f: %10.3g, %10.3f.", rval, rval);
|
||||
end
|
||||
endmodule // top_level
|
||||
|
||||
will produce the following output:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
This is g and e: 1.23e+09, 1.235e+09.
|
||||
This is g and f: 0.123, 0.123.
|
||||
This is more g and f: 1.23, 1.235.
|
||||
|
||||
``%t`` Time Format Specifier Can Specify Width
|
||||
----------------------------------------------
|
||||
|
||||
Standard Verilog does not allow width fields in the ``%t`` formats of display
|
||||
strings. For example, this is illegal:
|
||||
|
||||
.. code-block:: verilog
|
||||
|
||||
$display("Time is %0t", $time);
|
||||
|
||||
Standard Verilog instead relies on the ``$timeformat`` to completely specify
|
||||
the format.
|
||||
|
||||
Icarus Verilog allows the programmer to specify the field width. The ``%t``
|
||||
format in Icarus Verilog works exactly as it does in standard Verilog.
|
||||
However, if the programmer chooses to specify a minimum width (i.e., ``%5t``),
|
||||
then for that display Icarus Verilog will override the ``$timeformat`` minimum
|
||||
width and use the explicit minimum width.
|
||||
|
||||
``%v`` Format Specifier Can Display Vectors
|
||||
-------------------------------------------
|
||||
|
||||
The IEEE 1364-2005 standard limits the ``%v`` specifier in display strings to
|
||||
work only with a single bit. Icarus Verilog extends that to support displaying
|
||||
the strength of vectors. The output is a strength specifier for each bit of the
|
||||
vector, with underscore characters separating each bit, e.g. ``St0_St1_Pu1_HiZ``.
|
||||
Most other tools will just print the strength of the least significant bit of
|
||||
a vector, so this may give different output results for code that otherwise
|
||||
works fine.
|
||||
|
||||
Assign/Deassign and Force/Release of Bit/Part Selects
|
||||
-----------------------------------------------------
|
||||
|
||||
Icarus Verilog allows as an extension the assign/deassign and force/release
|
||||
of variable bit and part selects in certain cases. This allows the Verilog
|
||||
test bench writer to assign/deassign for example single bits of a variable
|
||||
(register, etc.). Other tools will report this as an error.
|
||||
|
||||
``repeat`` Statement is Sign Aware
|
||||
----------------------------------
|
||||
|
||||
The standard does not specify what to do for this case, but it does say what
|
||||
a repeat event control should do. In Icarus Verilog the ``repeat`` statement
|
||||
is consistent with the repeat event control definition. If the argument is
|
||||
signed and is a negative value this will be treated the same as an argument
|
||||
value of 0.
|
||||
|
||||
Built-in System Functions May Be Evaluated at Compile Time
|
||||
----------------------------------------------------------
|
||||
|
||||
Certain of the system functions have well-defined meanings, so can
|
||||
theoretically be evaluated at compile-time, instead of using runtime VPI
|
||||
code. Doing so means that VPI cannot override the definitions of functions
|
||||
handled in this manner. On the other hand, this makes them synthesizable,
|
||||
and also allows for more aggressive constant propagation. The functions
|
||||
handled in this manner are:
|
||||
|
||||
- ``$bits``
|
||||
- ``$signed``
|
||||
- ``$sizeof``
|
||||
- ``$unsigned``
|
||||
|
||||
Implementations of these system functions in VPI modules will be ignored.
|
||||
|
||||
``vpiScope`` Iterator on ``vpiScope`` Objects
|
||||
---------------------------------------------
|
||||
|
||||
In the VPI, the normal way to iterate over ``vpiScope`` objects contained
|
||||
within a ``vpiScope`` object, is the ``vpiInternalScope`` iterator. Icarus
|
||||
Verilog adds support for the ``vpiScope`` iterator of a ``vpiScope`` object,
|
||||
that iterates over *everything* that is contained in the current scope. This
|
||||
is useful in cases where one wants to iterate over all the objects in a scope
|
||||
without iterating over all the contained types explicitly.
|
||||
|
||||
Time 0 Race Resolution
|
||||
----------------------
|
||||
|
||||
Combinational logic is routinely modelled using always blocks. However, this
|
||||
can lead to race conditions if the inputs to the combinational block are
|
||||
initialized in initial statements. Icarus Verilog slightly modifies time 0
|
||||
scheduling by arranging for always statements with ANYEDGE sensitivity lists
|
||||
to be scheduled before any other threads. This causes combinational always
|
||||
blocks to be triggered when the values in the sensitivity list are initialized
|
||||
by initial threads.
|
||||
@@ -0,0 +1,25 @@
|
||||
|
||||
Icarus Verilog Usage
|
||||
====================
|
||||
|
||||
This section contains documents to help support Icarus Verilog users.
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 1
|
||||
|
||||
installation
|
||||
getting_started
|
||||
simulation
|
||||
command_line_flags
|
||||
command_files
|
||||
verilog_attributes
|
||||
ivlpp_flags
|
||||
vvp_flags
|
||||
vvp_debug
|
||||
vvp_library
|
||||
vhdlpp_flags
|
||||
waveform_viewer
|
||||
vpi
|
||||
icarus_verilog_extensions
|
||||
icarus_verilog_quirks
|
||||
reporting_issues
|
||||
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