5a6d07ff9f
Emit Verilog stubs for entities
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The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
2011-01-18 17:03:51 -08:00
02820c9e34
Parse create entities with ports
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Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
05122d3e2c
Add VHDLPP support to ivlpp program
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The ivlpp program is a good place to detect that the source file
is VHDL, and pass the source file to the vhdlpp program. Do so
automatically.
2011-01-18 17:03:51 -08:00
04b239a5fb
Flesh out VHDL parser engine.
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Add enough rules to parse a simple VHDL program:
Parse library and use clauses,
Parse entity declarations, and
Parse architecture bodies.
Add some parser infrastructure:
Handle syntax errors with useful error messages,
Include file name and line numbers in parse errors,
Add some parser debug aids.
2011-01-18 17:03:51 -08:00
8cf1fd1820
Introduce shell of vhdlpp program.
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Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00
Stephen Williams