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iverilog
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8 Commits

Author SHA1 Message Date
steve c677afd8e3 More precise handling of verinum bit lengths. 1999-05-13 04:02:09 +00:00
steve a416b1b336 Add implementation of integer to verunum constructor. 1999-05-09 01:38:33 +00:00
steve 63a8b4abe2 Function to calculate wire initial value. 1998-12-20 02:05:41 +00:00
steve d27f260bc1 Check net ranges in declarations. 1998-11-11 00:01:51 +00:00
steve d189165ae9 Oops, forgot return from operator<< 1998-11-09 19:03:26 +00:00
steve ebad845fc3 Add procedural while loops, 
Parse procedural for loops,
 Add procedural wait statements,
 Add constant nodes,
 Add XNOR logic gate,
 Make vvm output look a bit prettier.
 1998-11-09 18:55:33 +00:00
steve 5836c8aa4b Properly dump 0 length numbers. 1998-11-07 17:04:48 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00