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117 Commits

Author SHA1 Message Date
Maciej Suminski 763c6fe3c9 vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA). 
To be done: ROR & ROL.
 2015-02-17 10:15:57 +01:00
Maciej Suminski 49b6ddf93c vhdlpp: Signal/variable assignments can have labels. 2015-02-17 10:15:57 +01:00
Maciej Suminski 12b4914b63 vhdlpp: ExpName resolves enum values. 2015-02-17 10:15:57 +01:00
Maciej Suminski 5b7b980ead vhdlpp: Support for multiple choices in case statements. 2015-02-05 12:00:25 +01:00
Maciej Suminski a1c2a8e605 vhdlpp: Generic syntax errors display messages. 2015-02-05 11:25:03 +01:00
Cary R e896f0c8e6 Remove some compile warnings in the vhdlpp code 2014-10-14 09:03:42 -07:00
Maciej Suminski 9ff9cbf4aa vhdlpp: Smarter determining the direction in for loops. 2014-10-10 18:39:14 +02:00
Maciej Suminski c7beef907d vhdlpp: Support for 'range and 'reverse_range attributes. 2014-10-08 11:18:06 +02:00
Maciej Suminski 9951521212 vhdlpp: Subprogram parameters are taken into account when distinguishing between function calls and vector elements. 2014-09-30 15:59:46 +02:00
Maciej Suminski e352bea476 vhdlpp: Support for variable declarations in subprograms. 
Fixes sorrymsg: "variable_declaration not supported."
 2014-09-30 15:58:13 +02:00
Maciej Suminski a63289c2fc vhdlpp: VTypeArray::range_t handles direction (to/downto). 2014-09-15 12:10:04 +02:00
Maciej Suminski c92dea77fc vhdlpp: Basic support for unbounded array types. 
Once a signal/variable of unbounded array type becomes limited in its size, it
is emitted as a packed array. Therefore currently it works only for
bit/logic/reg/wire types.
 2014-08-15 10:21:45 +02:00
Maciej Suminski 5ed60a151f Added support for real type in vhdlpp. 2014-08-06 15:00:35 +02:00
Martin Whitaker 9e25884f12 Fix for br942 - allow function declaration in VHDL architecture. 2013-12-11 23:00:58 +00:00
Cary R 07cc18284c Fix print token/argument mismatches and other cppcheck fixes 2013-09-09 13:34:38 -07:00
Stephen Williams ca9616dc7b Better simple_expression parse rules. 2013-06-12 14:21:36 -07:00
Stephen Williams 24bd630cb2 Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
Stephen Williams dca6171f5f SV emit function ports in package subprograms. 2013-06-12 14:09:07 -07:00
Stephen Williams e927960121 Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
Stephen Williams d9fea802da Function declarations in packages 
This is still basic. Definitions are still not done.
 2013-06-12 14:09:07 -07:00
Stephen Williams bad8ed39c1 Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
Stephen Williams 5651e6e001 Improve error handling. 2012-11-02 19:30:12 -07:00
Stephen Williams 7fad717a1e Redesign selected_name rule to better handle complex prefixes 
Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
 2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Cary R 1749d10966 Fix some clang/bison compile warnings. 2012-08-06 15:49:11 -07:00
Larry Doolittle befff82655 Spelling fixes 
Comments and debug messages.
 2012-07-27 18:25:32 -07:00
Stephen Williams 4748f0cb5e Handle incomplete type declarations 
Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
 2012-05-22 17:31:27 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments. 
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
 2012-05-22 17:31:26 -07:00
Stephen Williams a5458828cd Some vhdl parser error handling. 2012-05-22 17:31:26 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference. 
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
 2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Stephen Williams 1249b5dd32 Initial support for if_generate syntax. 2012-05-22 17:31:25 -07:00
Stephen Williams 9ed56a6354 Parse record types, and some new aggregate types. 2012-05-22 17:31:25 -07:00
Cary R aedbda5a75 Identifiers need to be deleted with delete[] 
This patch fixes a mismatch in the delete style.
 2011-12-18 16:45:08 -08:00
Stephen Williams 2063c5ee9d Support VHDL user defined array types. 2011-11-05 15:55:17 -07:00
Stephen Williams 98d928f6e0 Add support for VHDL for-generate 2011-10-30 17:10:19 -07:00
Stephen Williams 15da45f7cb VHDL initialization expressions for signals. 2011-10-29 17:06:40 -07:00
Stephen Williams 4f98a6d181 Rewire VHDL addition expression parsing. 
The VHDL LRM addition expression rules are ... different.
 2011-10-23 17:31:58 -07:00
Stephen Williams 2be682f8a5 Support VHDL component instantiations with generics as Verilog parameters. 2011-10-23 17:08:48 -07:00
Stephen Williams d9acfe57b1 Put off array bound evaluation / describe entity generics as parameters 
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.

Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
 2011-10-15 17:41:48 -07:00
Stephen Williams a6f63b8a54 Parse generic clause in entity headers 
The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
 2011-10-15 09:49:24 -07:00
Stephen Williams 6268db6e68 Handle simple type declarations. 2011-10-09 15:25:35 -07:00
Stephen Williams 271aaf6376 Parse enumeration type declarations. 2011-10-01 17:04:04 -07:00
Stephen Williams 8003382b3e Elaborate and emit case statements. 2011-10-01 11:45:28 -07:00
Stephen Williams 88cce86c63 Emit code for the to_unsigned() bulit-in function. 2011-09-18 19:31:28 -07:00
Stephen Williams 677a22d353 Generate code for vhdl for loops. 2011-09-18 15:51:31 -07:00
Stephen Williams 4d445dc269 Fix parse of unnamed processes. 2011-09-18 09:37:11 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls. 
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
 2011-09-11 15:28:58 -07:00
Stephen Williams 6d28c989ce Handle the basics of aggregate expressions 
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
 2011-09-03 17:11:55 -07:00
Stephen Williams 4464c5849b Handle a few built-in functions internally. 
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
 2011-08-28 15:30:45 -07:00