Commit Graph

7283 Commits

Author SHA1 Message Date
Stephen Williams cf0b45702f Merge branch 'master' of github.com:steveicarus/iverilog 2012-04-03 07:57:02 -07:00
Cary R 42239a8498 Add code to test the width of individual structure elements.
This patch adds code to correctly set the type and width of individual
structure elements. Note the sign information is not currently available.
2012-04-02 19:53:47 -07:00
Stephen Williams 09493a198f Merge branch 'master' of github.com:steveicarus/iverilog 2012-04-02 19:22:40 -07:00
Stephen Williams 3657b15428 Merge branch 'x-ms1' 2012-04-02 19:22:31 -07:00
Cary R c222169608 Update vecval size calculation in vvp and vpi code.
The standard specifies that the size of a vecval should be calculated as
(size - 1)/32 + 1. When size is a PLI_INT32 this is needed to prevent an
overflow, but when the size is unsigned this can be simplified to
(size + 31)/32 since the size must fit into an integer, but we have an
extra significant bit in an unsigned so no overflow can happen.

This patch changes the code to use the correct version of the equation
depending on the context.

The previous patch does this in vvp/vpi_priv.cc
2012-04-02 08:18:46 -07:00
Cary R b85e7efca8 For a delayed vpi_put_value() copy any pointer data members.
When vpi_put_value() is asked to delay the assignment any pointer data
needs to be duplicated so that the caller can clean up the locally
allocated memory without causing memory access problems.

Also update word calculation to match the next patch.
2012-04-02 08:18:32 -07:00
Martin Whitaker 327194cd40 Fix for pr3499807.
If a tranif gate has a delay, the vvp code generator needs to generate
a unique label for the island port used for the tranif enable, to
prevent a name collision if the undelayed signal is also connected
to the island.

Also add an assertion in vvp to catch bugs like this.
2012-03-12 09:03:53 -07:00
Stephen Williams 5dbe688296 Allow variable initialization in any scope.
This is a SystemVerilog feature, so only allow it when
compiling SystemVerilog files.
2012-03-11 15:08:42 -07:00
Stephen Williams b0d61813b2 Get the scope of class methods right
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
2012-03-11 13:18:24 -07:00
Stephen Williams b80afdf1f1 SystemVerilog randomize method syntax. 2012-03-10 10:27:02 -08:00
Stephen Williams dbc6f0cff2 Parse SystemVerilog syntax for task calls.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
2012-03-10 09:50:41 -08:00
Stephen Williams da743c3b2c Bunches more SystemVerilog syntax. 2012-03-09 18:54:05 -08:00
Stephen Williams 8c2e4a0892 Support tasks with no behavioral statements (System Verilog) 2012-03-04 20:04:07 -08:00
Stephen Williams 0e01dcf2b9 Miscellaneous SystemVerilog syntax.
... and sorry messages.
2012-03-04 19:33:16 -08:00
Stephen Williams 31d4aa9a77 Handle complexities of class name pre-declarations
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
2012-03-02 21:16:53 -08:00
Stephen Williams f749867369 Rework rules for variable_dimensions, and support more syntax. 2012-03-02 18:34:43 -08:00
Stephen Williams 64ea328823 Parse dynamic array declarations. 2012-03-01 18:48:16 -08:00
Stephen Williams dbc58838d5 Parse class extends syntax and property qualifiers. 2012-03-01 18:17:52 -08:00
Stephen Williams 68eab8c664 Parse function declarations in classes.
Also add support for function end names when parsing SystemVerilog.
2012-02-26 19:16:10 -08:00
Stephen Williams f33086fed4 Parse dynamic_array_new statements. 2012-02-26 18:45:22 -08:00
Stephen Williams ebda9777cc Parse foreach loops. 2012-02-26 11:28:44 -08:00
Stephen Williams 481a9dec69 More rework to canonicalize tf_port_item rules. 2012-02-26 10:57:03 -08:00
Stephen Williams 410350ae5a Rework data_type parsing to bring integer vectors into data_type_t method.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
2012-02-25 22:05:00 -08:00
Stephen Williams dd3a7411cd Parse SystemVerilog ref ports. 2012-02-25 10:19:48 -08:00
Stephen Williams d000147392 Parse for declarations, implement for_step statements.
for-statement declarations still generate a "sorry" message, but
the for_step statements work in general now.
2012-02-25 09:28:20 -08:00
Stephen Williams cad7c74680 System Verilog supports closing names after endtask keyword. 2012-02-24 17:04:49 -08:00
Cary R bae02433b7 Remove some more warnings in pform.cc Ubuntu 11.10 (gcc/clang)
Remove a few more warnings from the gcc and clang compilers on
Ubuntu 11.10.
2012-02-22 17:27:27 -08:00
Cary R 952b84fba3 Fix signed/unsigned compare warning
Fix a signed/unsigned comparison warning on RHEL 5.
2012-02-22 15:11:01 -08:00
Cary R 51ef541969 Fix compile on cygwin and fix a few compile warnings.
This patch fixes a few compile warnings and adds the new packed routines
to the ivl.def file so that this links correctly on cygwin.
2012-02-22 10:20:49 -08:00
Stephen Williams f8e346f108 Implement increment/decrement statements.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
2012-02-19 18:54:58 -08:00
Stephen Williams 6b4251626b Parse array literals / rearrange task declaration rules. 2012-02-19 17:31:15 -08:00
Stephen Williams 8456252c0c More class syntax
Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 10:29:50 -08:00
Stephen Williams 5880a3ad8f Parse program blocks / Fix module end-name syntax. 2012-02-18 10:02:54 -08:00
Larry Doolittle 0aefcf9b48 Trivial fixes to grammar, spelling, whitespace 2012-02-17 16:18:22 -08:00
Stephen Williams 8b9fdbc55b Merge branch 'master' of github.com:steveicarus/iverilog 2012-02-17 08:21:49 -08:00
Stephen Williams fec1c1efde Handle r-value constant slice selects. 2012-02-12 16:19:58 -08:00
Stephen Williams 77f168cf28 Support non-constant indexed part select of packed arrays. 2012-02-12 14:52:47 -08:00
Cary R 391073a750 Update __vpiNamedEvent to remove struct and remove extra class statements
The clang compiler does not like using struct to reference a class object.
This patch removes all the struct keywords for __vpiNamedEvent objects
since they are now a class and can be called without a struct/class
qualifier.

This patch also removes all the extra class qualifiers from the rest of
the source code.
2012-02-12 13:22:32 -08:00
Stephen Williams 5e067bd651 Handle constant indexed part selects. 2012-02-12 12:03:43 -08:00
Stephen Williams c1b73c83f4 Respond better to some error/sorry situations. 2012-02-12 11:16:31 -08:00
Stephen Williams 6eeef8311f Handle indexed bit select of packed arrays.
This handles a few cases where the non-constant bit selects are
in the final index. This doesn't handle all the cases of packed
arrays, but it handles some common cases.
2012-02-12 10:13:20 -08:00
Stephen Williams 4287fc4b50 Handle l-value part select of packed arrays. 2012-02-10 18:48:12 -08:00
Stephen Williams 3e4f8b625f Get packed signals working through to simulation in some situations.
When dynamic indexing of early dimensions is not needed, we can get
pretty far with getting packed arrays to work.
2012-02-10 17:17:59 -08:00
Stephen Williams e5c49022b4 The NetNet class carries multiple packed dimensions. 2012-02-06 17:47:53 -08:00
Stephen Williams ae11010707 Evaluate packed ranges for signals. 2012-02-05 17:41:11 -08:00
Stephen Williams 950e7a632c Parse multi-dimension packed arrays to pform. 2012-02-04 16:19:27 -08:00
Stephen Williams 5d35ad8a0d Support uwire resolved writes to non-overlapping parts
The individual bits of an unresolved wire may be assigned in
different continuous assignments without generating an error.
2012-02-02 16:18:50 -08:00
Stephen Williams 764b38bb3b Use user defined types in the syntax.
Given that the syntax is already parsed and elaborated, it is a
simple matter to bind that typedef'ed type to the instances that
use it.
2012-02-02 16:18:50 -08:00
Stephen Williams 42b3e6f268 Implement simple typedefs, and parse type identifiers.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
2012-02-02 16:18:50 -08:00
Stephen Williams e14628193a Parse simple typedefs
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
2012-02-02 16:18:50 -08:00