Commit Graph

446 Commits

Author SHA1 Message Date
Stephen Williams c0f35cbe62 Disallow modules/gates in program blocks. 2012-05-27 18:26:53 -07:00
Stephen Williams 8154ce2a4a Reword how we enforce program block constraints
Making the scope type NESTED_MODULE was just plain wrong, because
it didn't really encapsulate the meaning of program blocks OR
nested modules. So instead create nested_module() and program_block()
flags and use those to test scope constraints.
2012-05-27 18:26:53 -07:00
Stephen Williams dfe7beec31 Allow modules (and program blocks in particular) to nest.
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
2012-05-27 18:26:53 -07:00
Stephen Williams 580c44c015 Prevent non-blocking assignment in program blocks. 2012-05-27 18:26:53 -07:00
Stephen Williams 0833d9e37a Basic support for program blocks. 2012-05-27 18:26:53 -07:00
Stephen Williams 342646264e Merge branch 'pei1' 2012-05-25 16:32:12 -07:00
Stephen Williams 6e8aef8262 Get unpacked arrays working. 2012-05-25 15:58:29 -07:00
Stephen Williams ceaa60d2f4 Parse (to "sorry") arrays of named types. 2012-05-22 17:31:27 -07:00
Stephen Williams 2443884779 Parse/sorry nets of named type. 2012-05-22 17:31:27 -07:00
Stephen Williams 67af96fee7 Module output ports use data_type_or_implicit
This cleans up the parsing of module output ports, allows for more
complex types on the ports, and fixes some bugs.
2012-05-22 17:31:26 -07:00
Stephen Williams b7b633b613 module output ports use data_type_t types.
This is in place of ad hoc type information passed to the
pform_module_define_port function.
2012-05-22 17:31:26 -07:00
Stephen Williams 7e202bb5ca Fix emit of struct ports/declarations. 2012-05-22 17:31:26 -07:00
Stephen Williams c7366e65cd Rework port input and inout to use data_type_or_implicit rule for types. 2012-05-22 17:31:26 -07:00
Martin Whitaker f7ba954ef7 Fix for pr3527022.
This patch adds support for an explicit range or type in a parameter
declaration that is part of a module parameter port list.
2012-05-18 13:30:28 -07:00
Martin Whitaker 5cbdac2a46 Add missing semi-colons in main compiler parse.y
This fixes some warnings from Bison.
2012-05-17 16:25:28 -07:00
Martin Whitaker 44c5a37ab8 Allow specparam declarations outside specify blocks.
This patch extends the compiler to support all specparam declarations
allowed by the 1364-2005 standard. For compatibility with other
simulators, it allows specparam values to be used in any constant
expression, but outputs a warning message and disables run-time
annotation of a specparam if it is used in an expression that must
be evaluated at compile time.
2012-05-17 16:18:38 -07:00
Stephen Williams 5d05d97eb0 Repair handling of attributes attached to variables. 2012-05-09 10:56:52 -07:00
Stephen Williams fb3969b5b8 Add command line control over anachronism warnings. 2012-04-30 16:30:24 -07:00
Stephen Williams abf8274e4b Fixup parse of attributes attached to statements. 2012-04-27 18:22:25 -07:00
Stephen Williams e55af496e5 Merge branch 'master' of github.com:steveicarus/iverilog 2012-04-10 15:31:32 -07:00
Stephen Williams 13348ba7ac Ranges are ranges, not expression lists.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)

Conflicts:

	PTask.h
	elab_scope.cc
	elab_sig.cc
	parse.y
	pform.cc
	pform.h
	pform_types.h

Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 14:29:28 -07:00
Larry Doolittle bb1036b55c Spelling refresh 2012-04-09 16:19:02 -07:00
Cary R 2b5c82d141 SystemVerilog unbased literals cannot take a size.
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
2012-04-09 16:01:25 -07:00
Stephen Williams b0d61813b2 Get the scope of class methods right
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
2012-03-11 13:18:24 -07:00
Stephen Williams b80afdf1f1 SystemVerilog randomize method syntax. 2012-03-10 10:27:02 -08:00
Stephen Williams dbc6f0cff2 Parse SystemVerilog syntax for task calls.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
2012-03-10 09:50:41 -08:00
Stephen Williams da743c3b2c Bunches more SystemVerilog syntax. 2012-03-09 18:54:05 -08:00
Stephen Williams 8c2e4a0892 Support tasks with no behavioral statements (System Verilog) 2012-03-04 20:04:07 -08:00
Stephen Williams 0e01dcf2b9 Miscellaneous SystemVerilog syntax.
... and sorry messages.
2012-03-04 19:33:16 -08:00
Stephen Williams 31d4aa9a77 Handle complexities of class name pre-declarations
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
2012-03-02 21:16:53 -08:00
Stephen Williams f749867369 Rework rules for variable_dimensions, and support more syntax. 2012-03-02 18:34:43 -08:00
Stephen Williams 64ea328823 Parse dynamic array declarations. 2012-03-01 18:48:16 -08:00
Stephen Williams dbc58838d5 Parse class extends syntax and property qualifiers. 2012-03-01 18:17:52 -08:00
Stephen Williams 68eab8c664 Parse function declarations in classes.
Also add support for function end names when parsing SystemVerilog.
2012-02-26 19:16:10 -08:00
Stephen Williams f33086fed4 Parse dynamic_array_new statements. 2012-02-26 18:45:22 -08:00
Stephen Williams ebda9777cc Parse foreach loops. 2012-02-26 11:28:44 -08:00
Stephen Williams 481a9dec69 More rework to canonicalize tf_port_item rules. 2012-02-26 10:57:03 -08:00
Stephen Williams 410350ae5a Rework data_type parsing to bring integer vectors into data_type_t method.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
2012-02-25 22:05:00 -08:00
Stephen Williams dd3a7411cd Parse SystemVerilog ref ports. 2012-02-25 10:19:48 -08:00
Stephen Williams d000147392 Parse for declarations, implement for_step statements.
for-statement declarations still generate a "sorry" message, but
the for_step statements work in general now.
2012-02-25 09:28:20 -08:00
Stephen Williams cad7c74680 System Verilog supports closing names after endtask keyword. 2012-02-24 17:04:49 -08:00
Stephen Williams f8e346f108 Implement increment/decrement statements.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
2012-02-19 18:54:58 -08:00
Stephen Williams 6b4251626b Parse array literals / rearrange task declaration rules. 2012-02-19 17:31:15 -08:00
Stephen Williams 8456252c0c More class syntax
Part of ongoing parser work to support SystemVerilog classes.
2012-02-19 10:29:50 -08:00
Stephen Williams 5880a3ad8f Parse program blocks / Fix module end-name syntax. 2012-02-18 10:02:54 -08:00
Stephen Williams 950e7a632c Parse multi-dimension packed arrays to pform. 2012-02-04 16:19:27 -08:00
Stephen Williams 764b38bb3b Use user defined types in the syntax.
Given that the syntax is already parsed and elaborated, it is a
simple matter to bind that typedef'ed type to the instances that
use it.
2012-02-02 16:18:50 -08:00
Stephen Williams 42b3e6f268 Implement simple typedefs, and parse type identifiers.
This gets me to the point where the parser stashes a defined type,
and the lexical analyzer uses the type names to differentiate
IDENTIFIER and TYPE_IDENTIFIER.
2012-02-02 16:18:50 -08:00
Stephen Williams e14628193a Parse simple typedefs
Parse typedefs with structs and enums, but give a sorry message,
because they are not yet supported. Rearrange some of the parse
rules for variables in order to increase comonality with the
typedef rules.
2012-02-02 16:18:50 -08:00
Stephen Williams e9e2fb33e9 Handle nets that are packed structures. 2012-02-02 16:18:49 -08:00