Nick Gasson
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b8c1f9ab67
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A system for linking ivl_signal_t to entities
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2008-06-12 20:26:23 +01:00 |
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Nick Gasson
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a7cfdc3a87
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Add VHDL if statement to AST types
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2008-06-11 14:11:37 +01:00 |
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Nick Gasson
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1d28b935e8
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Split vhdl_element.cc into multiple files
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2008-06-08 13:27:48 +01:00 |
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Nick Gasson
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9f035108e1
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Stub code for translating expressions
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2008-06-04 14:59:04 +01:00 |
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Nick Gasson
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4bf2e1669d
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Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
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2008-06-04 13:52:56 +01:00 |
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Nick Gasson
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fe80da362c
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Collect required packages as compilation progresses
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2008-06-03 19:14:47 +01:00 |
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Nick Gasson
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4211e651d0
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Stub file for processing statements
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2008-06-03 18:26:36 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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8189c4ee43
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Generate VHDL entities and architectures for all module scopes
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2008-05-31 15:28:25 +01:00 |
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Nick Gasson
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e38494a10c
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Pretty-print VHDL output
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2008-05-29 16:24:16 +01:00 |
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Nick Gasson
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bfa2bfc8ae
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Makefile and autoconf changes to build VHDL code generator
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2008-05-28 17:17:39 +01:00 |