steve
b2b9097488
Parse more constant expressions.
1999-05-06 04:09:28 +00:00
steve
df0c894cb0
Excesss endl.
1999-05-06 02:29:32 +00:00
steve
10f46dae66
More intelligent selection of module to elaborate.
1999-05-05 03:27:14 +00:00
steve
b44ef063a8
Fix handling of null delay statements.
1999-05-05 03:04:46 +00:00
steve
9e82ed240c
Restore support for wait event control.
1999-05-03 01:51:29 +00:00
steve
9fadd7821d
Enforce module instance names.
1999-05-02 23:25:32 +00:00
steve
5d00f17448
Handle wide events, such as @(a) where a has
...
many bits in it.
Add to vvm the binary ^ and unary & operators.
Dump events a bit more completely.
1999-05-01 20:43:55 +00:00
steve
41f9a84a4b
Handle much more complex event expressions.
1999-05-01 02:57:52 +00:00
steve
046a6ba576
XNF target documentation.
1999-05-01 02:57:11 +00:00
steve
345289f260
Add vvm target documentation
1999-04-29 16:29:04 +00:00
steve
ce49708442
Parse OR of event expressions.
1999-04-29 02:16:26 +00:00
steve
f01cbc6a57
Remember to make the dep directory.
1999-04-26 02:45:08 +00:00
steve
d98eb443b8
Autoconf the vvm directory.
1999-04-26 02:35:43 +00:00
steve
4b73655537
Generate SubSignal refrences in vvm.
1999-04-25 22:52:32 +00:00
steve
471d389c8c
autoconf the makefiles.
1999-04-25 21:54:33 +00:00
steve
09cfbc6240
Core handles subsignal expressions.
1999-04-25 00:44:10 +00:00
steve
32b52cbb97
Make debug output file parameters.
1999-04-23 04:34:32 +00:00
steve
d3350c9b27
Add to vvm proceedural memory references.
1999-04-22 04:56:58 +00:00
steve
5895d3c98d
Add memories to the parse and elaboration phases.
1999-04-19 01:59:36 +00:00
steve
bd40e5dfe1
Support sized decimal numbers,
...
Fix operator precedence order.
1999-03-16 04:44:45 +00:00
steve
51b4f70c8f
Add some logical operators.
1999-03-16 04:43:46 +00:00
steve
b7f833dd71
Support more operators, especially logical.
1999-03-15 02:43:32 +00:00
steve
5ee3a41d2a
Add the AND and OR bitwise operators.
1999-03-15 02:42:44 +00:00
steve
13a6f05463
Prevent the duplicate allocation of ESignal objects.
1999-03-01 03:27:53 +00:00
steve
a2bc27318f
Handle default case.
1999-02-22 03:01:12 +00:00
steve
e2a37a8ccd
Add support for module parameters.
1999-02-21 17:01:57 +00:00
steve
9d0a266705
Mangle that handles device instance numbers.
1999-02-15 05:52:50 +00:00
steve
3f4d5bf376
Fix off-by-one placement of hex bytes in a number.
1999-02-15 05:52:08 +00:00
steve
e5f5f41515
Elaborate gate ranges.
1999-02-15 02:06:15 +00:00
steve
fef81958bc
Do not generate code for signals,
...
instead use the NetESignal node to
generate gate-like signal devices.
1999-02-08 03:55:55 +00:00
steve
30a3953c85
Turn the NetESignal into a NetNode so
...
that it can connect to the netlist.
Implement the case statement.
Convince t-vvm to output code for
the case statement.
1999-02-08 02:49:56 +00:00
steve
8bdd381cdf
Parse and elaborate the Verilog CASE statement.
1999-02-03 04:20:11 +00:00
steve
a7ad8985ac
Carry some line info to the netlist,
...
Dump line numbers for processes.
Elaborate prints errors about port vector
width mismatch
Emit better handles null statements.
1999-02-01 00:26:48 +00:00
steve
8e73ccf8f8
Ignore ivl.
1999-02-01 00:24:43 +00:00
steve
15ff852487
Missing start methods.
1999-01-31 18:15:55 +00:00
steve
fb439c78b9
Add the LineInfo class to carry the source file
...
location of things. PGate, Statement and PProcess.
elaborate handles module parameter mismatches,
missing or incorrect lvalues for procedural
assignment, and errors are propogated to the
top of the elaboration call tree.
Attach line numbers to processes, gates and
assignment statements.
1999-01-25 05:45:56 +00:00
steve
4b92e91a54
change the program name to ivl.
1999-01-25 05:41:56 +00:00
steve
3d2993be0a
Support null target for generating no output.
1999-01-24 01:35:08 +00:00
steve
d1e2b036fc
Add startup after initialization.
1999-01-01 01:46:01 +00:00
steve
a4ce4d97ba
Support the start() method.
1999-01-01 01:44:56 +00:00
steve
1e0660522f
Proberly print vectors in binary.
1999-01-01 01:44:40 +00:00
steve
63a8b4abe2
Function to calculate wire initial value.
1998-12-20 02:05:41 +00:00
steve
2c1df3e6f7
Parse more UDP input edge descriptions.
1998-12-18 05:16:25 +00:00
steve
4e2c0036aa
VVM support for small sequential UDP objects.
1998-12-17 23:54:58 +00:00
steve
10b345bd16
Fully elaborate Sequential UDP behavior.
1998-12-14 02:01:34 +00:00
steve
45f45f73b7
Support the include directive.
1998-12-09 04:02:47 +00:00
steve
ed02ae33c7
Fix 2pin logic gates.
1998-12-09 02:43:19 +00:00
steve
9a73433759
Generate OBUF or IBUF attributes (and the gates
...
to garry them) where a wire is a pad. This involved
figuring out enough of the netlist to know when such
was needed, and to generate new gates and signales
to handle what's missing.
1998-12-07 04:53:16 +00:00
steve
ada45acb0c
Add the nobufz function to eliminate bufz objects,
...
Object links are marked with direction,
constant propagation is more careful will wide links,
Signal folding is aware of attributes, and
the XNF target can dump UDP objects based on LCA
attributes.
1998-12-02 04:37:13 +00:00
steve
e097c999d5
Elaborate UDP devices,
...
Support UDP type attributes, and
pass those attributes to nodes that
are instantiated by elaboration,
Put modules into a map instead of
a simple list.
1998-12-01 00:42:13 +00:00