Commit Graph

7964 Commits

Author SHA1 Message Date
Stephen Williams 7c50c9aedf Scan concat arguments with test_width.
Even though we cannot immediately give a width for a concatenation
that has a repeat expression (the expression must be evaluated first)
we still must scan the test_width of the arguments so that they can
resolve their types.
2008-11-11 21:09:19 -08:00
Martin Whitaker 04377151bc Checks for illegal use of automatically allocated variables.
This patch adds a number of compile and run-time checks for illegal
uses of variables declared in automatic tasks and functions. It
also adds a check for event expressions in automatic tasks that use
features not yet supported in VVP.
2008-11-11 20:45:19 -08:00
Stephen Williams da85c4fe00 Give the branch access expression type some meat.
In the ivl_target API, the IVL_EX_BACCESS expression type gets some meat,
specifically references to the branch it accesses and the the nature to
be accessed on that branch.
2008-11-11 20:41:14 -08:00
Stephen Williams 35a8d42741 Merge implicit branches.
Implicit branches all really are the same branch, so be careful to not
create a new branch if it already exists.
2008-11-10 21:19:30 -08:00
Stephen Williams 00df651c5f Branch references all the way down to the stub generator.
This includes enough API to get the branch nexus bits and signals
and show them in the dump. This also includes creating the reference
ground for branch access functions that use the implicit ground.
2008-11-09 21:42:12 -08:00
Stephen Williams 25201954d3 Bring branches forward as far as the emit method and target_t. 2008-11-09 17:11:04 -08:00
Stephen Williams 0da27a2f45 Collect analog branches into islands.
Discipline islands all along were intended to carry collections of
analog branches, as well as the current switch modeling support.
2008-11-09 15:32:50 -08:00
Stephen Williams 988fc70368 Merge branch 'master' into verilog-ams 2008-11-07 20:14:43 -08:00
Cary R bbdf622ea5 Fix numerous problems with the divide and modulus operators.
This patch fixes a number of problems related to the divide and
modulus operators.

The net version (CA) of modulus did not support a signed version.

Division or modulus of a value wider than the machine word did
not correctly check for division by zero and return 'bx.

Fixed a problem in procedural modulus. The sign of the result is
only dependent on the L-value.

Division or modulus of a signed value that was the same width as
the machine word was creating an incorrect sign mask.

Division of a signed value that would fit into a single machine
word was not checking for division by zero.

Division or modulus of a wide value was always being done as
unsigned.

Added a negative operator for vvp_vector2_t. This made
implementing the signed wide division and modulus easier.
2008-11-07 19:58:00 -08:00
Stephen Williams 4879b98b3a Merge branch 'master' into verilog-ams 2008-11-07 19:49:52 -08:00
Stephen Williams 13aaaab783 Bring analog contribution statements to the ivl_target API.
Add support for analog processes with analog contributation statements
all the way down to the ivl_target code generator API.
2008-11-06 21:31:34 -08:00
Cary R 1e06a2ddef ivlpp - clear lexor dynamic state information for flex >= 2.5.9
For flex version 2.5.9 and later there is a function
"yylex_destroy()" that clears any space dynamically
allocated by the scanner.
2008-11-04 16:01:47 -08:00
Cary R 049290d0fc Fix a memory leak and release all dynamically allocated memory (ivlpp)
This patch fixes a minor memory leak in ivlpp and releases all
dynamically allocated memory before the program exits. Other than
the dynamically allocated push state buffer in flex, ivlpp has no
valgrind memory errors or warnings.
2008-11-04 11:58:49 -08:00
Cary R 4c67bd0b35 Fix memory leak and free temp. file names to make valgrind happy.
There was a memory leak in the preprocess_only code (cmd was not
being freed when the command completed successfully.  Valgrind
was also marking the temporary file names as still reachable, so
they are not memory leaks, but freeing them makes valgrind happier.
2008-11-04 11:41:31 -08:00
Stephen Williams 4f7457fcec Merge branch 'verilog-ams' 2008-11-04 11:37:58 -08:00
Cary R 95ea159e75 Print `include comment after included text.
The inline comment text that appears after an `include directive
should appear after the included text not before.
2008-11-04 11:26:27 -08:00
Stephen Williams 0d88d3a798 Enforce that l-value of contribution is an access function. 2008-11-03 21:58:16 -08:00
Stephen Williams eb240ddb73 Bring discipline natures all the way to the ivl_target API.
The natures of disciplines were already available, this just brings
the information forward to the ivl_target.h API and exposes them via
access functions.
2008-11-03 21:10:10 -08:00
Stephen Williams c73199942b Proper test_width implementation for nature access functions.
Nature access functions have fixed output width and type. Implement
the test_width handling for access functions to reflect this.
2008-11-02 21:46:27 -08:00
Stephen Williams ddb2c60701 Remove svector class from Module.h
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
2008-11-02 20:08:38 -08:00
Stephen Williams 77eb68d314 Minor documentation improvements. 2008-11-02 16:56:25 -08:00
Stephen Williams f4687757f1 Bring signal discipline all the way to the ivl_target API.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
2008-11-02 08:10:41 -08:00
Stephen Williams b20019d8b6 Merge branch 'master' into verilog-ams 2008-11-01 21:09:29 -07:00
Stephen Williams 6cac1d2cab Add support for real/realtime arrays.
Support arrays of realtime variable arrays and net arrays. This
involved a simple fix to the ivl core parser, proper support in
the code generator, and rework the runtime support in vvp.
2008-11-01 20:44:03 -07:00
Larry Doolittle 520d9b9dd0 Touch up new developer quick start
Spelling and other minor touch-up for the new and
much-appreciated developer-quick-start.txt
2008-10-31 20:44:54 -07:00
Stephen Williams 403a1e9415 Add a dup_expr method to NetEUBits.
The NetEUBits needs to create a NetEUBits when the dup_expr method is
called, so it needs its own dup_expr method.
2008-10-30 22:11:05 -07:00
Larry Doolittle 9b640f3114 Shadow reduction part 4
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality.  This patch set covers the tgt-vhdl
directory, and was tested by Nick.
2008-10-30 21:46:44 -07:00
Cary R 7ac35e478b The scope of real values needs to be calculated.
Finding the scope of a real value is no longer simple, so it must
be calculated.
2008-10-30 21:41:36 -07:00
Cary R 2c7fe8aa2a Fixes for real VPI interface, etc.
This patch fixes some problems found when trying to dump words
from a real wire array. There are still a few more things that
look suspicious and need testing.
2008-10-30 21:41:28 -07:00
Stephen Williams 1ec09327e9 Elaborate divide expressions to the proper width.
If the operands of a divide expression are fixed width, pad them out
to the width of the expression so that the calculations come out right.
2008-10-30 21:19:56 -07:00
Nick Gasson ea9bbf804c Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-10-30 20:00:53 +00:00
Stephen Williams 1922a0df9e Fix C++ compiler warning.
classes with virtual methods must have virtual destructors. Otherwise,
destruction may not work corectly.
2008-10-29 21:03:44 -07:00
Martin Whitaker 18edf2f15f Rework of automatic task/function support.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.

This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.

This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
2008-10-29 20:43:00 -07:00
Stephen Williams ea057a7574 Elaborate logical and/or to account for special properties.
The arguments of logical and/or are self determined, and the width is
fixed as 1 bit. Account for this special behavior by creating the
PEBLogic class.
2008-10-29 20:31:26 -07:00
Stephen Williams b7d3276e4d Enforce bit width of operands of comparisons operators.
The comparison operator operands are self determined, but are forced
to be the width of the wider operand. This means that the operands must
be evaluated with their widths truncated. In spite of all this, note
that comparisons expression results are 1 bit wide.
2008-10-29 19:34:44 -07:00
Cary R 22ddb26389 Add support for arrays of real nets.
This patch adds support for arrays of real values nets (wire real).
2008-10-27 21:45:02 -07:00
Stephen Williams 9b89ca49bb Merge branch 'master' of ssh://steve-icarus@icarus.com/~steve-icarus/git/verilog 2008-10-27 21:39:47 -07:00
Stephen Williams 94e7d71b97 Make sure divide expressions are evaluated using the expression width.
The operands of divide need to be at least the width of the expression
when calculating a constant divide. The only matters for the special
case where the result is x, because the verinum implementation of
divide will get the result width from the left expression width.
2008-10-27 21:39:07 -07:00
Stephen Williams 810686d88e Merge branch 'master' into verilog-ams 2008-10-27 09:23:13 -07:00
Stephen Williams 0bd1739225 Merge branch 'vhdl' 2008-10-27 09:19:13 -07:00
Stephen Williams 038b024e71 Merge branch 'master' into verilog-ams 2008-10-26 21:59:53 -07:00
Stephen Williams 27410f5d88 Remove the now obsolete NetNet list in NetScopes.
Now that NetNet objects in NetScopes are kept in a map, remove the
linked list for scanning them. This improves the lookup process from
an O(e**N) process to more like O(log(N)). This matters for very
large designs.
2008-10-26 20:42:11 -07:00
Stephen Williams 0af896a7ff Keep a map of NetNets for fast access.
It turns out that netnets in scopes are accessed a lot, and mapping
them may help with performance.
2008-10-26 16:50:46 -07:00
Stephen Williams 81a0007f22 Add developer quict start.
Some basic documentation to help new developers get oriented.
2008-10-26 16:34:21 -07:00
Stephen Williams 2a5ea9e874 Remove the vpip contents.
These files are (were) related to the old vvm backend that is no longer
in use. Thus, these files are dead code.
2008-10-26 14:29:09 -07:00
Stephen Williams b9272f750d Update the BUG submission guidlines. 2008-10-26 13:43:35 -07:00
Nick Gasson f49a4e4336 Merge branch 'master' of git://icarus.com/~steve-icarus/verilog into vhdl 2008-10-26 12:48:22 +00:00
Cary R 26e1693b2f generate case items can have an optional statement.
generate case supports optional statements by putting
 a ';' in place of the statement. This patch adds
this functionality for all generate case items.
2008-10-25 23:27:00 -07:00
Stephen Williams 68fbb94b3a Basic elaboration of analog contribution statements.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
2008-10-22 21:56:00 -07:00
Stephen Williams 5aa810dde7 Infrastructure for elaborating analog statements.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.

While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
2008-10-21 22:15:49 -07:00