iverilog

Commit Graph

Author	SHA1	Message	Date
mjoekhan	fee8a0d67a	SV: add unconstrained class.randomize() / rand slice Implement obj.randomize() that assigns RNG values to rand/randc integral properties and returns 1, so Accellera UVM can start using unconstrained randomization before a constraint solver lands.	2026-07-21 18:45:57 +05:00
mjoekhan	7379ff6530	SV: add mailbox/semaphore builtins for UVM IPC Implement native SystemVerilog mailbox and semaphore with blocking and nonblocking put/get, so Accellera-style code can use the standard API without depending on the legacy IVL_UVM poor-man's classes.	2026-07-21 18:37:08 +05:00
mjoekhan	9601928032	SV: add interface clocking-block vertical slice for UVM Parse interface-local clocking blocks, treat cb as a transparent hop for member R/W, and elaborate @(bif.cb) as the clocking event so basic driver sync works with #0 skew.	2026-07-21 18:16:16 +05:00
mjoekhan	207f9a9b09	SV: add virtual-interface vertical slice for UVM agents Support virtual interface class properties/TF args, instance bind, member R/W, and @(posedge vif.clk) so basic driver connectivity works.	2026-07-21 17:58:35 +05:00
mjoekhan	bcc026c902	SV: add string-keyed associative array vertical slice Support int aa[string]/int aa[*] with assign, size/num, exists, delete, foreach, and whole-array copy for UVM Tier A table patterns. Runtime uses vvp_aarray_vec4 (std::map); int keys and richer element types deferred.	2026-07-21 17:12:16 +05:00
mjoekhan	9182f4b102	docs: describe Tier A parameterized classes work Document grammar/pform changes, box_default smoke, and C#(byte) TODO on the iverilog-uvm track only.	2026-07-21 16:28:32 +05:00
mjoekhan	372e93db3a	SV: parse ANSI class parameter port lists Allow class C #(type T = int, ...) so parameterized classes with defaults elaborate; add smoke examples and hello_uvm Makefile.	2026-07-21 16:25:09 +05:00
mjoekhan	4fc765f912	UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.	2026-07-21 16:14:00 +05:00

8 Commits