Commit Graph

45 Commits

Author SHA1 Message Date
Lars-Peter Clausen 8f78590bd2 Remove most references to ivl_variable_type_t from the parser
The parser used to have behavior that was dependent on the
`ivl_variable_type_t` of a signal. It also used the `ivl_variable_type_t`
of a signal to decide whether a signal can be re-declared as part of a
non-ANSI port declaration.

Neither of these is done anymore and most of the reference to
`ivl_variable_type_t` can be removed from the parser. The only thing it is
still needed for is to decide whether a vector type is 4-state or 2-state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-09-15 09:36:19 +02:00
Lars-Peter Clausen 6204b78610 Prevent invalid port redeclaration
(System)Verilog allows to declare the port direction separate from the
signal declaration. E.g.

```
output x;
integer x;
```

But this is only allowed if the port declaration
 * does not have an explicit net type
 * does not have an explicit data type
 * is a non-ANSI style declaration

For all other cases of port declarations the signal is considered fully
defined and it is not allowed to have a separate signal declaration.

In addition the declared packed dimensions need to match between the port
and signal declaration.

In the current implementation there are a few cases where this is not
handled correctly.

1) It is possible to declare non-ANSI task ports with the same name over
and over again, if it was declared as a signal before the port.

```
task t;
  string x;
  input logic x;
  output real x;
endtask
```

2) It is possible to re-declare non-ANSI input ports of a module that have
a data type, but no explicit net type.

```
module M;
  input integer x;
  wire integer x;
endmodule
```

3) It is possible to re-declare a ANSI port if it has an implicit data type.

```
module M(output [1:0] x);
  reg [1:0] x;
endmodule
```

4) It is possible to declare a vector signal for a scalar non-ANSI task
port.

```
task t;
input x;
reg [7:0] x;
```

To handle all of these correctly refactor signal declaration and lookup a
bit.

The PWire class that represents a signal already has two flags `port_set_`
and `net_set_`. These flags indicate whether a signal has already been used
in a port or signal declaration. A port declaration that includes an
explicit data type is considered both a port and signal declaration.

Use these flags to decide whether it is possible to extend an existing
declaration. E.g. when creating a port without an explicit data type and a
PWire by that name already exists and the `port_set_` flag is not set
extend the existing PWire. On the other hand if the `port_set_` flag is
already set report an error.

Similar for signals but with the `net_set_` flag.

For port declarations with an explicit data type or ANSI style port
declarations it is always an error if a PWire by that name already exists.

This is for both module and task/function ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-09-14 18:55:19 +02:00
Lars-Peter Clausen f6042033d0 Correctly handle separate port type declaration for `integer` and `time`
When using non-ANSI style port declarations it is possible to declare the
port direction and the data type for the port in separate statements. E.g.

```
input x;
reg x;
```

When using packed array dimensions they must match for both declarations.
E.g.

```
input [3:0] x;
reg [3:0] x;
```

But this only applies for vector types, i.e. the packed dimension is
explicitly declared. It does not apply to the `integer` and `time` types,
which have an implicit packed dimension.

The current implementation requires that even for `integer` and `time`
types the implicit dimension needs to be explicitly declared in the port
direction. E.g. the following will result in a elaboration error
complaining about a packed dimension mismatch.

```
module test;
  output x;
  integer x;
endmodule
```

Currently the parser creates a vector_type_t for `time` and `integer`. This
means that e.g. `time` and `reg [63:0]` are indistinguishable during
elaboration, even though they require different behavior.

To fix let the atom2_type_t handle `integer` and `time`. Since it no longer
exclusively handles 2-state types, rename it to atom_type_t.

This also fixes a problem with the vlog95 target unit tests. The vlog95
target translates

```
module test(output integer x);
endmodule
```

to

```
module test(x);
  output x;
  integer x;
endmodule
```

which then fails when being elaborated again. There were some regression
tests that were failing because of this that will now pass.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-28 10:40:06 +02:00
Lars-Peter Clausen 5cc825f45d Support dynamic arrays and queues of packed arrays
Currently only dynamic arrays and queues of atom2 and vector types are
supported. Add support for packed arrays. Since these three types are
essentially handled the same internally supporting this only requires to
allow to elaborate a packed array base type.

Factor out type elaboration into a helper function that can be shared
between the elaboration of the base type of a dynamic array or queue and
the type for other signals. This gives consistent behavior and will also
make it easier to support additional base types for dynamic arrays or
queues.

Note that it is not yet possible to index elements of packed array dynamic
arrays or queues. But neither is it possible to do a bit select for vector
or atom2 type dynamic arrays or queues yet. Supporting this needs some
additional work.

There is one test that declares a queue of a struct type, but doesn't use
it since it is not supported. With this change a error will generated when
trying to declare a queue of a struct. So update that test to not declare
the variable so it does not fail.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-12 14:07:06 +01:00
Lars-Peter Clausen b207ebd51a Fix part select on variables declared in packages
The logic that decides whether a vector is scalar or not incorrectly flags
all variables that are declared in packages as scalar. As a result it is
not possible to do a part select on a vector declared in a package.

Rather than having an independent scalar flag consider a vector as scalar
if it does not have any packed dimensions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2022-03-05 15:29:34 +01:00
Martin Whitaker ecbbb60fb6 Remove "using namespace std" from compiler header files and fix the fallout. 2021-11-04 16:55:03 +00:00
Martin Whitaker 95147a2cc2 Record data type for all pform "wires" added the new way.
For unpacked arrays, record both the array type and the base type.
This will be needed to elaborate typedefs in the correct scope.
2019-12-22 11:03:50 +00:00
Martin Whitaker b88d91c617 Create new base class for all named items that can be added to a scope.
Provide a helper function to identify the derived classes when reporting
errors.
2019-09-27 22:19:30 +01:00
Cary R d6b6b76015 Update header files to use a more standard name to prevent rereading
This is from github report #16. There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
Stephen Williams 77d24cd095 Elaborate class_new and (null) expressions
This gets the types right for class_new and null expressions, and
elaborate them down to the ivl_target.h API.
2012-12-10 19:13:43 -08:00
Stephen Williams 3d9ed1f0f8 Clean up PWire handling of wire data type. / Reword packed type handling 2012-09-03 16:00:09 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Stephen Williams 14f229de30 Parse support for dynamic arrays.
This includes limited support for dynamic arrays down to the code
generator, and some stubs in the vvp code generator and vvp run time.
2012-07-22 10:52:06 -07:00
Stephen Williams 6e8aef8262 Get unpacked arrays working. 2012-05-25 15:58:29 -07:00
Stephen Williams 13348ba7ac Ranges are ranges, not expression lists.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)

Conflicts:

	PTask.h
	elab_scope.cc
	elab_sig.cc
	parse.y
	pform.cc
	pform.h
	pform_types.h

Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 14:29:28 -07:00
Stephen Williams 950e7a632c Parse multi-dimension packed arrays to pform. 2012-02-04 16:19:27 -08:00
Stephen Williams d362c8dba0 Parse support for struct variables. 2012-02-02 16:18:49 -08:00
Stephen Williams cd6c6c7a70 Get the netenum_t base type data from the pform.
The pform propagates the parsed enum base type information
to the elaborator so that the base type can be fully elaborated.
This is necessary to get the types of the enumeration literals
correct.
2010-11-03 20:11:19 -07:00
Stephen Williams a14fa038b4 Enum names in r-value expressions
When enum names are used as r-values in expressions, use their
values. Treat the enum names similar to (but not exactly as)
localparams so that they fit into the rest of the elaboration
flow naturally.
2010-10-31 11:26:09 -07:00
Cary R b1dd0b1f6d It is an error to select part of a scalar value.
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
2009-04-17 18:18:22 -07:00
Stephen Williams f4687757f1 Bring signal discipline all the way to the ivl_target API.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
2008-11-02 08:10:41 -08:00
Stephen Williams 93b400c4d7 Attach disciplines to wires
Allow discipline declaration of nets that attaches the discipline to
a new wire or a wire that is already declared.
2008-05-11 17:30:33 -07:00
Stephen Williams 8e704cbf93 Rework handling of lexical scope
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.

This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
2008-02-24 19:40:54 -08:00
Cary R b69c4c9a2c Fix range handling/checking and add a flag to allow deprecated port syntax.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.

When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).

The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
2007-08-29 18:10:18 -07:00
steve ddd36ecb6c Rework the heirarchical identifier parse syntax and pform
to handle more general combinations of heirarch and bit selects.
2007-05-24 04:07:11 +00:00
steve b981c81d37 Rework hname_t to use perm_strings. 2007-04-26 03:06:21 +00:00
steve f001d0001a Add support for generate loops w/ wires and gates. 2006-04-10 00:37:42 +00:00
steve 75ad90534b Generalize signals to carry types. 2005-07-07 16:22:49 +00:00
steve 177b6ffb6a Addtrbute keys are perm_strings. 2004-02-20 18:53:33 +00:00
steve e941e7e805 Spelling fixes. 2003-01-30 16:23:07 +00:00
steve 46253ed873 Rework expression parsing and elaboration to
accommodate real/realtime values and expressions.
2003-01-26 21:15:58 +00:00
steve 52bf4e613f conditional ident string using autoconfig. 2002-08-12 01:34:58 +00:00
steve 5eca5d9948 Carry integerness throughout the compilation. 2002-06-21 04:59:35 +00:00
steve e6c0629626 Add language support for Verilog-2001 attribute
syntax. Hook this support into existing $attribute
 handling, and add number and void value types.

 Add to the ivl_target API new functions for access
 of complex attributes attached to gates.
2002-05-23 03:08:50 +00:00
steve ab6c8cb4b8 Parser and pform use hierarchical names as hname_t
objects instead of encoded strings.
2001-12-03 04:47:14 +00:00
steve 65020bc6de Use the iosfwd header if available. 2001-01-16 02:44:17 +00:00
steve 5dbea64759 Add support for signed reg variables,
simulate in t-vvm signed comparisons.
2000-12-11 00:31:43 +00:00
steve 1db70a0c46 Move signal elaboration to a seperate pass. 2000-05-02 16:27:38 +00:00
steve b734ecf02f Macintosh compilers do not support ident. 2000-02-23 02:56:53 +00:00
steve 4cfa3e4047 Support the creation of scopes. 1999-11-27 19:07:57 +00:00
steve 37b60a4c52 Clean up interface of the PWire class,
Properly match wire ranges.
1999-06-17 05:34:42 +00:00
steve f3a91a10b3 Line information with nets. 1999-06-02 15:38:46 +00:00
steve 5895d3c98d Add memories to the parse and elaboration phases. 1999-04-19 01:59:36 +00:00
steve af8d6fbf01 NetAssign handles lvalues as pin links
instead of a signal pointer,
 Wire attributes added,
 Ability to parse UDP descriptions added,
 XNF generates EXT records for signals with
 the PAD attribute.
1998-11-23 00:20:22 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00