Commit Graph

557 Commits

Author SHA1 Message Date
Cary R. 8cf4507fcb
Merge branch 'master' into master 2026-05-22 18:15:37 -07:00
Cary R. 129a5c980f
Merge pull request #1369 from larsclausen/unpacked-array-assign-strength-delay
Preserve delay and strength in unpacked array continuous assignments
2026-05-20 18:49:41 -07:00
Lars-Peter Clausen e35c857a24 Extend non-blocking event control with <= 0 repeat test
Extend the non-blocking event control assignment tests to check that a 0 or
negative repeat value is handled correctly. In this case the assignment
should be executed like a regular non-blocking assignment and the event
control should be ignored.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-19 21:00:56 -07:00
Lars-Peter Clausen 635bdd8eb8 Add regression tests for unpacked array continuous assignment strength and delay
Check that continuous assignments to unpacked net arrays preserve delay and
drive strength on the generated element drivers.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-17 14:46:31 -07:00
Lars-Peter Clausen 28e121c040 Add regression tests for net declaration assignments
Check that SystemVerilog net declarations can mix entries with and
without initialization.

Check that in SystemVerilog it is possible to do assignments within net array
declarations.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-17 11:12:26 -07:00
Cary R ca3a00a51a Update some vlog95 interface configurations 2026-05-16 23:17:11 -07:00
Lars-Peter Clausen 74491cfe9f Add regression tests for single element unpacked array assignments
Check that continuous assignment of an assignment pattern to a single element
unpacked array is accepted. Check that assigning a scalar expression to the
whole unpacked array is rejected for both procedural and continuous
assignments.

Check that a selected element of a single element static unpacked array can be
used in a continuous l-value concatenation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 21:11:30 -07:00
Lars-Peter Clausen 08479888b1 Add regression tests for restricted type parameters
Check that enum, struct, union and class restricted type parameters are
accepted. Check that mismatched default values and overrides are rejected.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 17:29:32 -07:00
Lars-Peter Clausen f8e9384689 Add regression tests for soft packed unions
Check that soft packed unions can have members with different widths.
Check that the `soft` qualifier implies `packed` and that nested soft
packed unions use the same representation recursively.

Also check that member bits are right-justified and that assignments to
narrower members leave the MSBs beyond the member bits unchanged. Check
that soft packed unions reject default member values.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 16:46:57 -07:00
Lars-Peter Clausen 0a6fa449de Add regression tests for `begin_keywords` versions
Check that each valid `begin_keywords` selector is accepted. Only check
that the selector itself is accepted, in these tests there is no check if
the correct keywords are actually accepted or rejected since that would get
pretty exhaustive.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 15:40:37 -07:00
Lars-Peter Clausen eadb1d24ae Add 2017 and 2023 language flag support
Add flags to enable IEEE1800-2017 and IEEE1800-2023 languages generations
and also support them in the `begin_keywords macro. Since neither defines
new keywords they'll use the same keyword mask as 2012.

Update the driver, compiler, documentation and regression test harness so
-g2017 and -g2023 are recognized as language generation flags.

There are no specific features from these versions added yet, this is just
the necessary infrastructure to allow gating new features from those
generations when they are added later.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 15:40:37 -07:00
Cary R. 00325f3efb
Merge pull request #1348 from jotego/interface-ports
Support SystemVerilog interface-typed module ports
2026-05-16 15:33:56 -07:00
Cary R. 1751f4ed0b
Merge pull request #1361 from larsclausen/unpacked-lvalue-concat-error
Reject unpacked l-value concatenation operands
2026-05-16 14:37:36 -07:00
Lars-Peter Clausen 96cea271ba ivtest: Fix VVP regression test metadata
A few JSON regression test entries reference the wrong source or gold
files. There are also two regress-vvp list entries that reference each
other's JSON file.

Use the matching source and gold files for those entries.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 13:43:10 -07:00
Lars-Peter Clausen b8eac7fc19 ivtest: Fix source for sv_mixed_assign2 test
The sv_mixed_assign2 JSON entry accidentally references
sv_mixed_assign1.v. Point it at sv_mixed_assign2.v instead.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-16 12:51:43 -07:00
Lars-Peter Clausen f9ab26b3d9 Add regression tests for unpacked l-value concat errors
Check that class objects, dynamic arrays, queues, strings and static
unpacked arrays can not be used as l-value concatenation operands. Check
procedural and continuous assignment concatenations, including single
operand concatenations.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-15 20:48:19 -07:00
Lars-Peter Clausen e4afd6dc25 Add regression test for `super` access error
Check that access through `super` is rejected when the current class has no
parent class.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-12 20:43:38 -07:00
Lars-Peter Clausen ba3f46722c Add regression tests for edge controls on named event errors
Check that the compiler reports an error for `posedge`, `negedge` and `edge`
event controls on named events. Edge controls can not be used with named
events.

There is already an existing test that checks both `posedge` and `negedge`.
Split it into separate tests so that each invalid event control is checked
independently.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-11 21:10:35 -07:00
Jose Tejada 56afcb6e75 fix(interface): allow forward interface port types 2026-05-11 22:25:32 +02:00
Jose Tejada 377881b723 fix(interface): address port array review feedback 2026-05-11 07:44:43 +02:00
Lars-Peter Clausen ea57b6dd9a Add regression test for real array index error
Check that using a real valued expression as an array index is rejected
during elaboration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-10 22:26:48 -07:00
Jose Tejada 417ab54445 feat(interface): support interface port arrays 2026-05-10 17:30:54 +02:00
Jose Tejada 39072cd452 feat(interface): broaden interface port binding 2026-05-10 16:34:21 +02:00
Jose Tejada c963809709 feat(sv): support interface-typed module ports 2026-05-10 14:45:33 +02:00
Cary R e212ea1a1c package liftime test needs signed for vlog95 testing 2026-05-08 05:54:13 -07:00
Cary R. 3986804264
Merge pull request #1343 from larsclausen/lifetime_package
Allow lifetime specifier for variables declared in packages
2026-05-08 05:21:19 -07:00
Lars-Peter Clausen 81222402c7 Add regression tests for package variable lifetimes
Check that package variables can use explicit static lifetime. Check that
automatic lifetime is rejected for package variables.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-07 22:14:20 -07:00
Cary R f559a05672 Net arrays are not supported for Verilog 95 2026-05-06 21:25:25 -07:00
Lars-Peter Clausen 6ffb4b9a3a Add regression tests for string literals assigned to byte arrays
Check that string literals can be assigned to byte arrays. Check that
invalid target array types are reported as errors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-06 19:20:47 -07:00
Lars-Peter Clausen 8519a30354 Add regression test for unpacked array output port expressions
Check that assignment patterns cannot be connected directly to unpacked
array output ports.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-03 17:31:09 -07:00
Lars-Peter Clausen be3be03fec Add regression test for drive strength net declarations
Check that drive strength can be specified between the net type and the
data type in a net declaration and that vector gate arrays resolve
strengths correctly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2026-05-03 17:30:56 -07:00
Cary R 6c52271afa Reorder check-installed targets 2026-04-30 08:31:50 -07:00
Ralf Habacker c14c73dd9a ivtest: Integration of regression tests into the build system
Replace .github/test.sh with a unified set of targets installed
via `make check-*` in ivtest/, thereby removing CI-specific test
coordination. This avoids duplication in the regression logic and
ensures consistent execution between local and CI environments.
PLI1-dependent tests are now correctly controlled via
`configure --enable-libveriuser`.

Currently, the regression suite still depends on an iverilog package,
which must be installed manually at the location specified with
`configure --prefix=*`. Afterward, the complete regression suite
(VVP, VPI, and Python tests) can be run via `make check-installed`
and individual checks can be run with `check-installed-vpi`,
`check-installed-vvp` and `check-installed-vvp-py`.
2026-04-30 17:04:53 +02:00
mjoekhan 70d1de0dbd ivtest: address review — restore LXT for br_gh710b, tidy br1005 vlog95 list
- br_gh710b: use -lxt again; gold files back to LXT output
- regress-ivl1: drop br1005 comment line
- regress-vlog95: move br1005 CE entry to class section after br1004

Made-with: Cursor
2026-04-30 10:32:30 +05:00
Cary R 6f3beca5fb FST can dump packages 2026-04-29 20:59:19 -07:00
mjoekhan 506b4f2757 ivtest: fix regressions after class queue and darray ordering work
- br1005: remove CE from regress-ivl1; gold is simulation PASSED; add CE
  override in regress-vlog95.list for vlog95_reg.pl
- always_*_warn: gold matches 'ordering/delete' synthesis message
- br_gh710b: drop -lxt (default VCD) so tests pass without libbz2; update gold

Made-with: Cursor
2026-04-29 22:47:31 +05:00
mjoekhan 0696847c4a Merge branch 'master' of https://github.com/muhammadjawadkhan/iverilog 2026-04-29 11:56:39 +05:00
mjoekhan c17472b494 SV: sort(), rsort(), shuffle() for queues and dynamic arrays
Implement ordering methods in elaboration, VVP codegen, runtime opcodes,
and vvp_darray implementations (including class property paths). Add
regressions and class locator checks; document behavior in README.

Made-with: Cursor
2026-04-29 10:15:49 +05:00
mjoekhan e597156d4d SV: implement reverse() for queues and dynamic arrays
Lower a.reverse() and q.reverse() to $ivl_darray_method$reverse with new
VVP opcodes %reverse/obj and %reverse/prop/obj. Implement reverse_elems()
on vvp_darray and queue storage types; dispatch queues via peek<vvp_queue>
before vvp_darray so virtual overrides apply.

Includes regressions for standalone arrays/queues and class properties.
README_sv_queue_locators.txt documents behavior and tests.

Made-with: Cursor
2026-04-29 00:48:56 +05:00
mjoekhan 084db5ef73 tests: extend class locator regressions for sum/product with
Document sum/product with-expression coverage for class property tests.

Made-with: Cursor
2026-04-29 00:29:36 +05:00
mjoekhan 701c5f8a07 SystemVerilog: support product() with expressions on arrays
Enable queue/darray product() with (expr) by lowering to a dedicated _with sfunc, evaluating the expression per item, and reducing through a new %queue/product/obj/v runtime opcode. Add regressions and docs for queue and dynamic-array product_with behavior.

Made-with: Cursor
2026-04-28 23:48:59 +05:00
mjoekhan 03512faee6 SystemVerilog: add integral product() reduction on arrays
Implement queue/darray product() reduction (including class property paths) via new %queue/product/v and %queue/product/prop/v opcodes, with elaboration/codegen support and regressions for queue, dynamic-array, and class-property usage.

Made-with: Cursor
2026-04-28 23:32:45 +05:00
mjoekhan 0568961f6b SystemVerilog: support sum() with expressions on arrays
Enable queue/darray sum() with (expr) by lowering to a dedicated _with sfunc, evaluating the with-expression per item, and reducing appended values via new %queue/sum/obj/v runtime support. Add regressions for queue and dynamic-array sum_with and update locator docs.

Made-with: Cursor
2026-04-28 22:59:54 +05:00
mjoekhan f9e3f9a3e4 SystemVerilog: integral sum() reduction for queues and dynamic arrays
Add $ivl_queue_method$sum elaboration, eval_vec4 lowering (%queue/sum/v and property variant), and VVP runtime that sums words with Verilog-style vec4 addition. Empty arrays yield 0. Regressions: sv_queue_sum, sv_darray_sum; document in README_sv_queue_locators.

Made-with: Cursor
2026-04-28 22:29:40 +05:00
mjoekhan 7fe2ddda0b VVP: array-pattern object values for class queue properties
Support IVL_EX_ARRAY_PATTERN in object evaluation for queue-typed class properties: build an empty queue and append pattern elements, matching darray array-pattern object handling. Fix vec4 stack use so %queue/append_word/v is not double-popped. Update class queue locator regression to use direct c.q = '{...} assignment.

Made-with: Cursor
2026-04-28 22:17:13 +05:00
mjoekhan c189cc2642 SystemVerilog: honor with-clause for class queue min/max
Route class queue-property min/max calls with `with (...)` through predicate-based locator elaboration so filtered extrema behave consistently with queue and darray locator semantics.

Made-with: Cursor
2026-04-28 21:45:35 +05:00
mjoekhan 0cd7205585 SystemVerilog: support locator methods on class queue properties
Enable queue locator elaboration for class properties typed as queues (not only dynamic arrays), and add regression coverage for class queue property find/unique/min/max behavior.

Made-with: Cursor
2026-04-28 21:36:01 +05:00
mjoekhan 7cac25cbd1 SystemVerilog: add unique()/unique_index() with predicates
Enable unique and unique_index locator methods with `with (...)` for queues, dynamic arrays, and class dynamic-array properties, including VVP opcode/runtime support and regression coverage.

Made-with: Cursor
2026-04-28 21:10:11 +05:00
mjoekhan 789bff4861 VVP: support array-pattern objects in dynamic-array property assignment
Handle IVL_EX_ARRAY_PATTERN in object evaluation by constructing a dynamic-array object and filling elements, so direct class property assignments like c.d = '{...}; codegen correctly without requiring a temporary variable.

Made-with: Cursor
2026-04-28 20:51:16 +05:00
mjoekhan 8f18edd20d SystemVerilog: class darray property locator methods and VVP prop fixes
Add class dynamic-array property support for locator methods (find*, unique*, min/max, with predicates) by elaborating dynamic-array property method calls to queue-method sfuns. Extend VVP property paths to treat property values as queue-or-darray sources, not queue-only, and fix object-stack handling in property locator loops so temporary accumulator objects do not hide the class object.

Add regression coverage for class dynamic-array property locators and update locator-method test documentation/listing.

Made-with: Cursor
2026-04-28 20:38:10 +05:00