This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
Up till now only "global" use clauses were parsed
and as a result libraries were loaded.
Since use clauses can appear not only in global context,
parsing of non-global clauses has been introduced and
selected names are now handled (like name1.name2.name3).
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
The bison grammar has been extended in order
to parse configuration statements. Parsing
remains very primitive but principal constructs
can be now recognized.
IEEE 1800-2005/9 says "each fixed-size dimension shall be represented by
an address range, such as [1:1024], or a single positive number to
specify the size of a fixed-size unpacked array, as in C. In other
words, [size] becomes the same as [0:size-1]."
This patch implements that translation in the parser. It issues a
warning when doing so when the generation flag is less than 2005-sv.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
This patch adds code to make sure a double (Verilog real) constant
is printed correctly. It also adds code to trim any leading escaped
NULLs from an expression string.
In VHDL it is allowed to have multiple architectures
per one entity. The proper architecture should be then
chosen in a configuration block. Now, if many architectures
will be found, then there will be a warning message printed.
FIXME notes are added in order not to forget about changes to
be done
This patch uses the new function (ivl_logic_is_cassign) to determine
if a logical was really the base of a continuous assignment. This
allows creating code that more closely matches the original.
This patch adds code that allows the targets to determine if a logical
gate came from a continuous assignment. This helps some of the targets
generate code that more closely matches the input.
It also reworks/simplifies the synthesis of && and || since the
compiler has already converted the two operands to single bit form
and fixes a mismatched delete from a previous patch.
This patch adds support for correctly handling most unconnected ports.
Most important is top level ports that are the root of the conversion.
This patch also adds support for emitting more signed constructs when
they are requested. $signed() and $unsigned() are still not supported
or recognized as an error when not emitting signed constructs.
This patch changes the module elaboration slightly to allow passing
the appropriate information for unconnected and top level ports. This
allows the vlog95 generator to get the basic structure correct.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.
Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.
In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
This patch adds a flag -pallowsigned=1 to the vlog95 converter that
tells it to allow signed signals. There is currently no code to check
for and warn/emit the $signed() and $unsigned() system functions. I
need to determine if >>> emitting should also be controlled by the
allow signed flag.
This patch adds support for emitting escaped identifiers and adds
code to correctly emit most module port expressions/definitions.
There are some minor code optimizations/cleanup included as well.
There was a single message when the expression width was larger
than the port width. This patch makes it a bit more clear by
saying that the expression was pruned.
Currently the compiler coerces input ports to inout ports whenever
there is an internal driver connected to the internal port net.
This generates an error if the port is externally connected to
something other than a structural net. This patch modifies the
compiler to ensure port coercion only occurs in valid cases.
This patch ensures that the result of a shift is an undefined value
if the right operand is an undefined value. It also improves the
code generated for right shifts where the right operand is constant
and optimises away shifts where the right operand is a constant 0.
It also fixes a few places where the expression type (signed/unsigned)
was not being set correctly.
The logic_lpm.c file uses the nexus private data pointer as an
unsigned counter. This patch makes the value unsigned long to
avoid a compilation warning on 64 bit systems.
This patch adds support for emitting fixed CA selects (zero based
variable bit and array selects also work), emitting a for statement
as a single statement and fixes for numerous little bugs. It also
adds the start of emitting module port information.
This patch adds some preliminary module port information to the ivl
interface. This may change as I investigate exactly what is needed.
It also fixes a few minor bugs (a missed local variable and spacing)
This patch adds a trace command to the interactive prompt that can be
used to control statement tracing when the code is instrumented (has
%file_line opcodes).
A valarray of an enum does not initialize to 0 so explicitly specify the
value to fill the array with. This was causing the compiler to incorrectly
report that fixed width elements in a concatenation had no size.
The following was done to remove compiler warning when using the native
compiler on OpenSolaris.
Remove the anonymous unions in tgt-vlog95/stmt.c and tgt-vvp/vvp_process.c.
Use UINT_MAX for the maximum unsigned unsigned instead of -1 in
tgt-vvp/draw_net_input.c.
Even though lex defines yywrap() to have no arguments when %option
noyywrp is used it generates a define that takes an argument that is not
used. The compiler warned about this so remove the option and add a
dummy yywrap function.
Stephen Williams
Pawel Szostek
Larry Doolittle
Martin Whitaker
Jared Casper
Cary R
Nick Gasson