Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
Conflicts:
tgt-vhdl/process.cc
tgt-vhdl/stmt.cc
tgt-vhdl/vhdl_target.h
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
An unsized signed constant that is smaller than integer_width needs
to be resized up to either the integer_width or the expression width
whichever is smaller.
Fix all the Icarus files that can be so that we do not have any
signed/unsigned compare warnings. It also removes const as a
return qualifier for two routines in discipline.h.
This patch mimics what was done for vectors, but is simpler since
arrays don't use the endian information. It also needs to address
the fact that .array/port assumes the expression is unsigned so
any signed expression must be padded to make it larger than the
maximum array word when it is converted to unsigned.
This patch modifies all the variable bit and indexed part selects
to use a common routine. This routine determines the minimum
width needed to calculate the result correctly, pads the expression
if needed and then converts the expression to signed if required to
make the calculation correct.
The Cygwin man command requires that you have a / in the path
if you want to avoid looking at the normal search path. This
patch addes ./ before the manual page file name. Which should
work on any system. It also makes the vvp generation create a
PS file like is done in the other Makefiles.
By default we generate normal manual pages. You can then
create PostScript version and from these you can generate a
PDF version.
While checking for an infinite loop in an always block I missed
the case where an if statement does not have a statement. This
was resulting in a segmentation fault.
This is a fix for pr2555831. A separate entity/architecture pair is
generated for each module that is instantiated with a unique
parameter combination.
If someone accidentally makes a parameter depend on itself
we need to report this not crash. This patch fixes the crash
and prints an appropriate string of messages to figure out
the loop. Icarus currently supports forward references of
parameters so more complicated loops can be created. These
are also caught.
To prevent a force from back propagating we need to keep a BUFZ
that represents a continuous assignment between two nets. This
only effects continuous assignments of the form assign out = in.
In general these are fairly rare so keeping them has minimal
impact on the simulation speed.
Add code to print a warning if the user tries to use the -S flag.
We need this warning since synthesis is not currently being actively
maintained or supported in any branch after V0.8.
For example:
-- Generated from Verilog module child (vhdl_tests/generics.v:30)
-- MY_VALUE = 3
entity child is
To make it clear which values were used for this entity.
This changes the implementation of $display/$write to use VHDL
report statements rather the the std.textio functions. The code
produced is simpler and more like what a real VHDL designed would
write. However it no longer exactly matches the Verilog output as
most VHDL simulators prepend the text with simulation time, entity
name, severity level, etc. There is a corresponding change in
ivtest to support this.
Previous we generated a "wait for 0 ns" statement after
every blocking assignment that wasn't the last statement
in the process. While this implements the Verilog semantics,
it generates excessive waits, and cannot usually be synthesised.
This patch only generates "wait for 0 ns" statements when it
cannot be avoid (e.g. when the target of a blocking assignment
is read in the same process).
An example:
begin
x = 5;
if (x == 2)
y = 7;
end
Becomes:
x <= 5;
wait for 0 ns; -- Required to implement assignment semantics
if x = 2 then
y <= 7; -- No need for wait here, not read
-- wait for 0 ns (previously)
end if;
This patch adds a check in the vvp back end that a uwire has
at most one driver. Previously this was just converted (with
a warning message) to a wire just after elaboration.
This patch adds the ability to call a system function as a task for
the SystemVerilog generation (-g2009). The return value is really
calculated, but it is ignored.
E.g. $signed(x) > y with x, y different sizes should be
resize(signed(x), N) > y
Not
signed(resize(x, N)) > y
As this does not treat the sign bit correctly. Was causing
the signed5 test to fail.
Nick Gasson
Stephen Williams
Cary R
Larry Doolittle