luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
6,076 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

7 Commits

Author SHA1 Message Date
Stephen Williams f61428dc82 Basic elaboration of vhdl component instantiations. 
This gets us as far as emiting a component instantiation. Very little
error checking/elaboration is done, so there is room for improvement,
but this is a working stub.
 2011-03-31 18:50:48 -07:00
Stephen Williams f32ede23b7 Do type mapping in the parser. 
In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.
 2011-02-13 16:54:56 -08:00
Stephen Williams 769159d053 Add parse decorations for expressions. 
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
 2011-02-13 16:47:05 -08:00
Stephen Williams 3ca0a482cf Annotate the parse of simple concurrent statements. 2011-02-13 16:43:45 -08:00
Pawel Szostek 77a346ffb1 Added full number, based number (both int and float), string and character literals handling 2011-02-10 18:34:38 -08:00
Pawel Szostek 0395eadbc8 Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports 
Create entity objects from entity declarations in the source,
and populate them with ports.
 2011-01-18 17:03:51 -08:00