Commit Graph

19 Commits

Author SHA1 Message Date
Stephen Williams d4c5cfc584 Add packages and component declarations within those packages.
This creates the Package class to represent packages, and the
Scope class to represent scopes in general. The library functions
are worked up to support scanning scopes for declarations that are
imported by "use" clauses.
2011-04-13 18:30:00 -07:00
Stephen Williams 799864eabf Add more complete support for vhdl local signals.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.

In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).

I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
2011-03-27 12:01:58 -07:00
Stephen Williams 8580ceea4d Parse component declarations / parse signal declarations.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
2011-03-22 09:18:20 -07:00
Stephen Williams 9330b58a3a Merge branch 'master' into work4
Conflicts:
	vhdlpp/lexor.lex
	vhdlpp/parse.y
	vhdlpp/vhdlint.cc
2011-03-14 17:34:57 -07:00
Cary R 98f5ed2f85 Fix remaining space issues. 2011-03-14 16:26:31 -07:00
Stephen Williams bc5fe9676e Create the shell of a proper type system.
Rather then just relying on comparing type names all throughout
elaboration, create type description data structures and use them
during elaboration to handle proper types.
2011-02-13 16:54:56 -08:00
Stephen Williams 798ead9345 Code generator for architectures.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
2011-02-13 16:48:52 -08:00
Stephen Williams 769159d053 Add parse decorations for expressions.
Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
2011-02-13 16:47:05 -08:00
Stephen Williams 30d689016a Create an Architecture class and bind them to their entities. 2011-02-13 16:43:04 -08:00
Pawel Szostek 77a346ffb1 Added full number, based number (both int and float), string and character literals handling 2011-02-10 18:34:38 -08:00
Cary R 633ee85dc2 vhdlpp: update make clean and vpath, add cppcheck target
This patch updates the make clean target and modifies the vpath search to
match what is done in the main ivl Makefile since this one has the same
issues it does. It also adds a cppcheck target and removes the redundant
libmisc build target since the vpath already handles this.
2011-01-26 18:07:39 -08:00
Cary R a6c02f8cb9 Some vhdlpp git cleanup.
This patch adds vhdlpp/parse.output to .gitignore and moves all the
vhdlpp depend files to the local dep directory.
2011-01-26 18:07:27 -08:00
Cary R 6bf7e88611 Fix build of ivl with files in libmisc and vhdlpp check issues.
This patch fixes the ivl build to find files in libmisc using vpath instead
of a separate target. The existing constructs caused build problems after
running a make clean. It also adds an empty checking target to vhdlpp.
2011-01-24 13:34:47 -08:00
Jared Casper ffca523d39 Fix vhdlpp Makefile for out-of-tree builds.
The INCLUDE_PATH in the vhdlpp Makefile was not including $(srcdir)
and $(srcdir)/.. when building outside of the source tree.
2011-01-24 13:33:41 -08:00
Stephen Williams ab8f623cea Add file/line information to entities and ports
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.

Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
2011-01-18 17:03:51 -08:00
Stephen Williams 5a6d07ff9f Emit Verilog stubs for entities
The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
Stephen Williams 05122d3e2c Add VHDLPP support to ivlpp program
The ivlpp program is a good place to detect that the source file
is VHDL, and pass the source file to the vhdlpp program. Do so
automatically.
2011-01-18 17:03:51 -08:00
Stephen Williams 8cf1fd1820 Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00