d5ffb55bfd
Corrected ambiguous copyright info.
2015-03-27 18:57:40 +01:00
ab9a8ccbf3
vhdlpp: Added fit_type() & probe_type() for ExpFunc.
2015-03-27 18:57:40 +01:00
e33b8b4dde
vhdlpp: VType::get_width() uses information from Scope to determine the type width.
2015-03-06 17:58:04 +01:00
afbda099fb
vhdlpp: Workaround to handle constant arrays of vectors & records.
2015-03-06 17:32:25 +01:00
a42b056b24
vhdlpp: Alternative way of accessing constant arrays of vectors.
2015-03-06 17:32:25 +01:00
763c6fe3c9
vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
...
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
11bb7ac348
vhdlpp: Expression::write_to_stream becomes const.
2015-02-05 11:25:03 +01:00
8a854affa6
vhdlpp: Clone routines for Expression & VType classes.
2015-02-05 11:25:03 +01:00
51ce9f1a60
vhdlpp: Minor correction for casting to integer.
2015-02-05 11:25:03 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
d4dd635bf6
vhdlpp: Added ExpNew class.
2015-02-04 16:57:43 +01:00
777e7e0a3d
vhdlpp: Added ExpFunc::func_ret_type() method.
2015-02-04 16:57:43 +01:00
9b3bd039bb
vhdlpp: Added ExpCast class.
2015-02-04 16:57:42 +01:00
95faed8e9d
vhdlpp: Added basic support for concatenated expressions.
2014-10-15 10:51:21 +02:00
54696e0127
vhdlpp: Elaboration & emit support for aggregate initializer expressions in records.
2014-09-17 11:24:16 +02:00
b1d15436fd
Removed ExpReal::evaluate().Its signature does not match the one meant to be overridden.
2014-08-22 16:55:47 +02:00
9031f392ba
Convert string to bitstring in SigVarBase
...
constructor if applicable (vhdlpp).
2014-08-08 11:20:07 +02:00
5ed60a151f
Added support for real type in vhdlpp.
2014-08-06 15:00:35 +02:00
d6b6b76015
Update header files to use a more standard name to prevent rereading
...
This is from github report #16 . There are likely a few more issues
that need to be addressed though this takes care of the major ones.
2014-07-23 13:42:56 -07:00
8487cb5616
Do a better job of figuring the vtype of an expression.
2013-06-12 14:21:36 -07:00
d630e4dfe9
Elaborate VHDL entity port types/expressions.
...
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
0fcd2d9db6
Handle rising_edge and falling_edge functions.
2013-06-12 14:21:35 -07:00
6394a4d78d
Rework scope types and constants so we can tell imported from local names.
...
The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
2013-06-12 14:09:07 -07:00
5651e6e001
Improve error handling.
2012-11-02 19:30:12 -07:00
85e000ed0c
Handle prefix expressions that include array index expressions.
2012-09-03 16:00:10 -07:00
7fad717a1e
Redesign selected_name rule to better handle complex prefixes
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Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
befff82655
Spelling fixes
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Comments and debug messages.
2012-07-27 18:25:32 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
...
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
71d2401221
Handle VHDL records.
...
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
ae06863db1
Elaborate prefix names which may be structure variables.
2012-05-22 17:31:26 -07:00
021d944a30
Probe type of ExpName with a record prefix.
2012-05-22 17:31:25 -07:00
7eb89c5548
Parse name prefix syntax for record member reference.
...
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
9b816f6478
Add support for nested when/else expressions.
2012-05-22 17:31:25 -07:00
9ed56a6354
Parse record types, and some new aggregate types.
2012-05-22 17:31:25 -07:00
84f14dbc81
Spelling fixes to vhdlpp tree
...
Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
cc508d1626
Support write_to_stream for arithmetic expressions.
2011-11-05 15:55:41 -07:00
eeeadea3ac
Fix recently broken write of vhdl packages to work space.
2011-10-16 12:18:34 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
...
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
88cce86c63
Emit code for the to_unsigned() bulit-in function.
2011-09-18 19:31:28 -07:00
f0e61a1db7
Basic vhdl elaboration for unary not operator.
2011-09-18 15:13:30 -07:00
1d02f89a09
Handle vhdh array aggregate expressions.
...
Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
...
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
6d28c989ce
Handle the basics of aggregate expressions
...
This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
4464c5849b
Handle a few built-in functions internally.
...
The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
7556a37859
Parse function calls, and detect type case expressions.
...
Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
78788d17fe
Translate VHDL string literals to bit vectors
2011-08-20 11:11:47 -07:00
981425fcce
Add semantics check in component instantiation
...
There have been applied rules for port and signal
association in component instatiation statements
described in the VHDL standard.
2011-07-24 10:14:41 -07:00
e2932cb6b5
Add ExpName::elaborate_rval member function
...
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
2011-07-19 21:29:05 -07:00
721f9d5d9b
Add String Expression to the VHDL parser
2011-07-08 18:05:06 -07:00
Maciej Suminski
Cary R
Stephen Williams
Arun Persaud
Larry Doolittle
Pawel Szostek