f32ede23b7
Do type mapping in the parser.
...
In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.
2011-02-13 16:54:56 -08:00
5914617727
Clean up entity interface.
2011-02-13 16:48:52 -08:00
769159d053
Add parse decorations for expressions.
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Elaboration will need a parse tree for expressions. Create one for
the expression types that are currently supported. Also add rules
and the keywords for all the remaining binary logical operators.
2011-02-13 16:47:05 -08:00
3ca0a482cf
Annotate the parse of simple concurrent statements.
2011-02-13 16:43:45 -08:00
30d689016a
Create an Architecture class and bind them to their entities.
2011-02-13 16:43:04 -08:00
Stephen Williams