Commit Graph

10 Commits

Author SHA1 Message Date
Stephen Williams 8580ceea4d Parse component declarations / parse signal declarations.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.

Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
2011-03-22 09:18:20 -07:00
Stephen Williams 89aa08e1aa Add parser support for architecture declaratives and component instantiations
Also include support for "sorry" messages so that we have a place
to hang unsupported but properly parsed constructs.

In the process of doing this, I also encountered and add parser support
for indexed names. And matching "sorry" messages.
2011-03-22 09:18:01 -07:00
Stephen Williams f32ede23b7 Do type mapping in the parser.
In VHDL, types are declared before they are used, so it is possible
to do type binding during parse. This makes the parser a little bit
cleaner.
2011-02-13 16:54:56 -08:00
Stephen Williams bc5fe9676e Create the shell of a proper type system.
Rather then just relying on comparing type names all throughout
elaboration, create type description data structures and use them
during elaboration to handle proper types.
2011-02-13 16:54:56 -08:00
Stephen Williams 798ead9345 Code generator for architectures.
Separate elaboration from code generation in the Entity, and add
to Architectures a code generator to handle some simple cases. At
this point we have the basic structure for the VHDL compiler.
2011-02-13 16:48:52 -08:00
Stephen Williams 5a6d07ff9f Emit Verilog stubs for entities
The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
Stephen Williams 05122d3e2c Add VHDLPP support to ivlpp program
The ivlpp program is a good place to detect that the source file
is VHDL, and pass the source file to the vhdlpp program. Do so
automatically.
2011-01-18 17:03:51 -08:00
Stephen Williams 04b239a5fb Flesh out VHDL parser engine.
Add enough rules to parse a simple VHDL program:
  Parse library and use clauses,
  Parse entity declarations, and
  Parse architecture bodies.

Add some parser infrastructure:
  Handle syntax errors with useful error messages,
  Include file name and line numbers in parse errors,
  Add some parser debug aids.
2011-01-18 17:03:51 -08:00
Stephen Williams 8cf1fd1820 Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00