8df2f0cadf
Fix broken links to SourceForge bug/patch trackers (GitHub issue #207 ).
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Also add link to GitHub issues, as a lot of users report bugs there.
2018-09-28 10:03:06 +01:00
3f24557e90
Add some more always_ff synth checks
2018-09-23 22:32:22 -07:00
e6f957b0b6
Add support for a constant $countbits() function
2018-09-03 15:58:57 -07:00
1da9b2cea0
Add support for constant $countones, $isunknown, $onehot, $onehot0
2018-09-03 08:32:41 -07:00
2b030ce27a
Update the bit vector table name
2018-09-03 08:32:35 -07:00
b35f9e13c7
Move the bit vector functions to the SV table
2018-09-03 08:32:28 -07:00
40558160e7
Add support for bit vector system function in vpi
2018-08-30 22:31:15 -07:00
ff8ccc0b3e
Update fstapi.c to the latest version
2018-07-16 09:03:38 -07:00
11c826216a
Fix for GitHub issue #198 - support octal display for thread variables.
2018-06-12 22:58:07 +01:00
7ad5b59a6f
Fix for GitHub issue #199 : handle signed division overflow.
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When performing a signed division or modulus operation using native
arithmetic, trap the special case that the numerator is the minimum
integer value and the denominator is -1, as this gives an undefined
result in C++.
2018-06-12 21:59:58 +01:00
6e49ab10ec
Further fix for br1029.
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The code in vpi_callback.cc is replicated in vpi_vthr_vector.cc,
so we have to replicate the fix. This should really be factored
out.
2018-05-14 22:14:51 +01:00
87c01c55c0
Don't allow non-vectorable arguments to $signed/$unsigned.
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This led to an assertion failure in many cases (see br1029).
1364-2012 indicates it is illegal.
2018-05-14 22:13:56 +01:00
5a4e99b0e8
Fix br1029 - correct rounding when vpi_get_value converts real to integer string.
2018-05-12 23:49:11 +01:00
6c39348d1a
Merge branch 'master' of github.com:steveicarus/iverilog
2018-04-11 13:40:04 -07:00
6c9b3c39b4
Add the --ccflags option to iverilog-vpi
2018-04-11 13:39:53 -07:00
797fe44011
Merge pull request #186 from anparks/master
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Fixed install step misnomer in README
2018-03-28 12:42:37 -07:00
fdaf923532
Fixed install step misnomer in README
2018-03-28 12:24:47 -07:00
64618af4a9
Merge pull request #123 from dcandrade/master
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Added missing compilation instruction on README
2018-03-26 09:55:34 -07:00
5cfb7d68ae
Add support for rtran switches in vvp.
2018-02-23 22:30:32 +00:00
36eef5154f
Implement supply->strong strength reduction for non-resistive switches.
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As specified in 1364-2005 section 7.11.
2018-02-23 22:07:59 +00:00
69d80839a5
Improved check for missing task/function port direction.
2018-02-21 20:07:13 +00:00
6b1b402a79
Fix for br1027: incorrect inference of task/function port direction.
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In traditional Verilog, each task_port_item must have an explicit port
direction.
In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
2018-02-20 20:59:26 +00:00
f8a2a4816c
Enable parameter/localparameter definitions in the compilation unit scope.
2018-02-18 19:21:18 +00:00
2a21fe77ac
Output an error message when a SV variable declaration reuses a name.
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Assertion failures are not the right way to handle user code errors.
2018-02-18 17:51:56 +00:00
caf83b02c1
Enable variable declarations/initialisations in the compilation unit scope.
2018-02-18 14:09:03 +00:00
0f95770418
Include compilation units in pform dump.
2018-02-18 12:53:29 +00:00
e7a9662b3d
A #0 is not allowed in a final block
2018-01-01 21:35:26 -08:00
24a4ec3bb2
Hide the always_comb/latch TO event by not attaching it to a scope.
2018-01-01 21:19:58 -08:00
ca01385797
The synth check needs to check the task scope
2017-12-28 08:50:32 -08:00
932241ee87
Check system/user tasks for always_comb/ff/latch synth.
2017-12-27 23:08:32 -08:00
7d11fa662e
Fix space issues
2017-12-27 14:51:56 -08:00
2bbd077dc9
Add some synthesis checks for the always_comb/ff/latch blocks
2017-12-27 14:51:17 -08:00
0caa109174
Merge pull request #181 from phire/portinfo_grammar
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vvp grammar: .port_info statements should require/generate semicolons.
2017-12-18 10:04:42 -08:00
d01e5accc0
vpp: Require semicolon after .port_info statements
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Optional until 12.0
2017-12-17 00:06:09 +13:00
7b84b29bbc
tgt-vvp: Output semicolon after .port_info statements
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Backwards compatablity is perserved due to the parser interperting the
unexpected semicolon as an empty statement.
2017-12-16 23:59:48 +13:00
9a8212a54f
Update tp the latest files from GTKWave
2017-12-13 21:56:59 -08:00
f17992bcd0
Report the lines that have delay or event control in an always_comb/ff/latch process
2017-12-06 00:22:43 -08:00
cb0ffd734e
Check to see that always_comb/ff/latch do not have delays/events
2017-12-05 22:10:43 -08:00
39c14edb76
The delay for a join_any and join_none is different than join
2017-12-05 21:49:52 -08:00
c38ca2114b
Note the always_comb/ff/latch have not been looked at for synthesis
2017-12-03 20:17:42 -08:00
db1ea05452
Fix #0 to trigger in the inactive region and add a trigger for always_comb/latch
2017-12-03 20:17:42 -08:00
a5b945f8f5
Initialize the t0 trigger value to false.
2017-12-03 20:17:42 -08:00
e611e8acc0
Add support to convert always_comb/latch to vlog95
2017-12-03 20:17:42 -08:00
575aa9b0fb
Fix spelling in always_comb
2017-12-03 20:17:42 -08:00
84d0df8a8a
Pass to the targets if an implicit T0 trigger event is needed.
2017-12-03 20:17:42 -08:00
585a0232cb
Add preliminary support for always_comb, always_ff and always_latch
2017-11-20 07:50:05 -08:00
c68a7fede3
Fix spacing
2017-11-20 07:30:52 -08:00
3fc9ad2db0
Add support for the wild compare operators ==? and !=?
2017-11-17 19:32:50 -08:00
d23b046203
Update the enumeration methods to set their width test attributes correctly
2017-11-17 13:09:14 -08:00
21418c6a41
Fix a couple memory leaks in $sdf_annotate()
2017-11-16 19:42:07 -08:00
Martin Whitaker
Cary R
Stephen Williams
Aaron Parks
Scott Mansell