05a52e55e9
Create a BUFZ to drive the 0.0 value onto an undriven real wire.
...
This is needed to allow forced values to propagate correctly.
2015-06-26 00:45:00 +01:00
59c211d20c
Fix stub target to handle real valued constants.
2015-06-26 00:41:43 +01:00
dad223316e
Fix propagation of unforced bits when forcing a part select.
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vvp_net_t::force_vec4 propagates all bits of the forced value passed
to it, regardless of the mask value. I can't see any way to fix this
directly, so instead make sure anything that calls force_vec4 sets
the unforced bits of the passed value to the correct value.
2015-06-25 00:13:57 +01:00
df597e19cb
vhdlpp: Removed conversion of '*_edge(sig)' to 'always begin..end @(*edge sig)'.
2015-06-24 23:53:33 +02:00
7597270939
vhdlpp: Fixed $ivlh_rising/falling_edge().
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Conditions to detect rising/falling edges were incorrect.
VHDL standard specifies it has to detect the current value,
rather than compare against the previous one.
2015-06-24 23:53:33 +02:00
5509b3c7a5
vhdlpp: Enums are based on integer type.
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This way than can be used as output ports.
2015-06-24 23:53:33 +02:00
49253c43ba
vhdlpp: Do not emit reg/wire prefix for enums.
2015-06-24 23:53:33 +02:00
311ffb27f2
ivl: Enum output ports are implicit regs when based on 'logic' type.
2015-06-24 23:53:33 +02:00
f0fd73e146
ivl: Array querying functions ($left, $low, etc.) for localparams.
2015-06-24 23:53:33 +02:00
5858e1bbac
vhdlpp: ExpName::probe_type() checks Subprogram parameters.
2015-06-24 23:53:33 +02:00
95044d9ac7
vhdlpp: VType::type_match() checks definitions provided by VTypeDef.
2015-06-24 23:53:33 +02:00
c6f934964f
vhdlpp: NOT is translated to either ~(...) or !(...) depending on the argument type.
2015-06-24 23:53:32 +02:00
6f867d6f01
vhdlpp: Changed 'char' to 'byte'.
2015-06-24 23:53:32 +02:00
e6b57910a4
vhdlpp: ScopeBase::is_enum_name checks enums from standard libraries.
2015-06-24 23:53:32 +02:00
cc9b182eb6
vhdlpp: Procedure calls.
2015-06-24 23:53:32 +02:00
d39f692cfd
vhdlpp: Refactored the way of handling standard types.
2015-06-24 23:53:32 +02:00
b666b9c0bf
vhdlpp: Fixed a few memory leaks.
2015-06-24 23:53:32 +02:00
b3c1fa3e85
vhdlpp: Elaborate prefix & indices for ExpName.
2015-06-24 23:53:32 +02:00
169228ad0f
vhdlpp: Refactored the way of handling standard VHDL library functions.
2015-06-24 23:53:31 +02:00
356a09d295
vhdlpp: VTypeArray::evaluate_ranges uses range boundaries to determine the direction.
2015-06-24 23:53:31 +02:00
47c5ce0ab6
vhdlpp: Subprogram split to SubprogramHeader and SubprogramBody.
2015-06-24 23:53:31 +02:00
3c437874e2
vhdlpp: Allow initializers for variables.
2015-06-24 23:53:31 +02:00
c28000c55f
vhdlpp: Support for selected assignments.
2015-06-24 23:53:31 +02:00
5a0d967682
vhdlpp: More renaming in ExpConditional.
2015-06-24 23:53:31 +02:00
49efe6573c
vhdlpp: Minor ExpConditional refactoring.
...
Merged cond_ and true_clause_ to else_clause_ list to make
code more generic.
2015-06-24 23:53:31 +02:00
ea12c0fe23
vhdlp: Renamed ExpConditional::else_t to ExpConditional::option_t.
2015-06-24 23:53:31 +02:00
44dfc41004
Detect and report excess function arguments.
...
Also enhance a couple of error messages.
2015-06-21 09:07:11 +01:00
bdd0657140
Reject default task/function arguments when parsing traditional Verilog.
2015-06-21 09:05:39 +01:00
1d279798d8
Fix for br982 - detect and report missing output arguments in task calls.
2015-06-20 22:39:55 +01:00
0e66e9781a
Add support for non-constant default subroutine arguments.
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Input ports only at the moment. Output "sorry" message for other
port types.
2015-06-20 21:39:45 +01:00
b23faff27c
Just a few more spelling fixes
...
Includes some user-visible messages
2015-06-17 08:09:34 -07:00
b242663cae
Support negedge flip-flops in synthesis and in vvp.
...
Also extend the support for FF asynchronous set values to vvp and
fix the dff functor in vvp to correctly model asynchronous set/clr
behaviour.
2015-06-13 16:47:57 +01:00
d39c284055
Observe and propagate failures when synthesising lval concatenations.
2015-06-13 16:47:57 +01:00
6a73de0c43
Merge pull request #70 from orsonmmz/time
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Time expressions for vhdlpp
2015-06-08 16:17:40 -07:00
e0cdd71984
Minor cleanup and simplification of aset_value changes.
2015-06-08 21:20:49 +01:00
81e1735959
establish support for aset_value and reorder clauses so vlog95 doesn't fail anymore.
2015-06-08 20:34:50 +01:00
3fb65eb51a
single bit reset
2015-06-08 20:34:43 +01:00
3080f5730d
Better implementation of assignment lval concatenation synthesis.
2015-06-08 20:27:38 +01:00
29ddd5208f
vhdlpp: 'wait on' and 'wait until' statements.
2015-06-08 18:42:52 +02:00
4a31f36646
vhdlpp: Minor code cleaning.
2015-06-08 18:42:52 +02:00
1f1d47887e
vhdlpp: Visitor for Expression class.
2015-06-08 18:42:52 +02:00
80403d2ade
ivl: Disabled reg_flag for time type in SV.
2015-06-08 18:42:52 +02:00
cd3180d1c2
ivl: TIME_LITERAL added as a primary expression.
2015-06-08 18:42:52 +02:00
68f8007fc4
vhdlpp: 'wait for' statement.
2015-06-08 18:42:52 +02:00
d6ff1946f9
vhdlpp: Support for time expressions.
2015-06-08 18:42:52 +02:00
4068c172f4
Fix overzealous detection of duplicate net/variable declarations.
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As reported by Larry Doolittle on iverilog-devel.
2015-06-07 08:48:33 +01:00
9ac9f1c9f2
Merge branch 'master' of github.com:steveicarus/iverilog
2015-06-04 15:11:29 -07:00
2739f83702
Spelling fixes in C and C++ comments
2015-06-04 15:00:29 -07:00
7af3280215
Update cppcheck suppression file in VPI
2015-06-04 09:50:08 -07:00
05d591ccd6
Fix broken write to log files.
2015-06-03 14:32:04 -07:00
Martin Whitaker
Maciej Suminski
Larry Doolittle
Stephen Williams
Johann Klammer
Cary R