Add support for detecting when to add a $signed() or $unsigned() to
create a self-determined context. This makes the test in the test suite
pass, but there could still be issues
Since parameters are now passed by reference use that information to print
the parameter name in a select vs trying to figure it out by searching the
scope looking for a parameter with the same file, line and value information.
Only print the $signed() may need to be removed messages for a select
expression that will actually be cast to signed.
Use the actual parameter information to warn that -pallowsigned=1 is needed
for a parameter when the LSB > MSB.
The actual signal code is trivial, but the emit expression code needed
to be enhanced to pass a flag that says if one of the arguments in a
binary (except the shifts) or ternary (excluding the condition) context
is unsigned. This information is used to prevent emitting an explicit
$unsigned() for a signal that is used in this context since it will be
implicitly cast to unsigned.
This patch adds support for finding and adding $signed() and $unsigned()
to procedural expressions for the binary, unary and concatenation
operators. Selects have partial support. The select implementation
uncovered limitations in the compiler that need to be fixed before they
will work 100%. Most of the limitations currently generate a message
about the issue.
The changes in COPYING are mostly cosmetic and use <year> vs 19xx, etc.
Also update the tgt-vlog95/Makefile.in copyright to match the formatting
in the FSF version.
If a logical pull device is converted into a CA then it is an assignment
with strength, so just emit the appropriate constant to get the correct
functionality (e.g. 1'b1 for a pull up and 1'b0 for a pull down).
Also add missing file/line information.
This patch finishes the code needed to translate a SystemVerilog package to a
module with a special name. It also adds code to report that class scopes are
not supported and treats both a class and package as a top level scope.
There are limitations with this since the compiler does not pass all
the information that was present in the original source, but it is enough
to get a valid simulation result. It is not enough for timing analysis!
specparams are also incorrectly translated to parameters so they show up
in the wrong place.
If modules instantiations were always handled correctly this would not be
needed, but for now looking for the nexus driver outside the scope is
needed to make some of the tests work.
In SystemVerilog a task or function can initialize a variable in a task or
function. In Icarus this is done by creating an initial block that does
the assignment. We can translate this by emitting the initial block in the
enclosing module scope. This is not 100% correct since SystemVerilog
requires the initialization to be done before the other initial/always
blocks are processed. For SystemVerilog the current Icarus behavior is
incorrect, but even if it had a new process type that ran before the other
ones the best I can do for vlog95 is emit it before the normal module
processes which currently works.
In the starting comment say if the conversion was done with signed support.
If there were errors then add a comment at the end of the file that says
how many errors occurred and add a line after this that prevents the file
from running with out an error. This requires the user to see that errors
occurred and remove the offending line if they want to use the file anyway.
Since the vlog95 code generator needs the strength information we do
not want to hide it behind a concat-Z optimization. For now we abort
the optimization, but in the future we could add parts of this back
in (e.g. all the drivers have matching strength then replace with a
normal concat and a buf-Z if the strength are not both strong. The
original buf-Z should be removed to reduce the number of LPM devices).
The Verilog-A abs(), min() and max() functions can be converted if the
expressions do not have side effects. Also note the new, null and class
property operators from SystemVerilog are not supported.
This patch updates the code to translate the SystemVerilog assignments with
an opcode to the appropriate vlog95. This includes ++ and -- when used in
a statement context. The ++ and -- operators are not currently translated
in an expression context. This translation only occurs in two places:
A simple assignment statement (foo += 2;) and the increment of a for
statement. I still need to check if there are other places where these
operators are allowed.
SystemVerilog supports using assignments with opcodes (e.g. +=). This
patch checks for these in a few common places and prints a warning
that they are not currently supported. Eventually the simple cases
will be converted.
We can not convert SystemVerilog strings or dynamic arrays to valid vlog95.
This patch adds an error message that they are not supported. There are still
issues with converting some of the dynamic array constructs (the compiler
crashes), but the message is printed before the crash.
This patch adds support for SystemVerilog packed arrays and adds sorry
messages for generate blocks as well as the new SV final and
fork/join_any/join_none statements.
Cary R
Arun Persaud