3 Commits

Author	SHA1	Message	Date
steve	1e0660522f	Proberly print vectors in binary.	1999-01-01 01:44:40 +00:00
steve	7859de1e4e	Add support it vvm target for level-sensitive ... triggers (i.e. the Verilog wait). Fix display of $time is format strings.	1998-11-10 00:48:31 +00:00
steve	8705aa94c6	Add vvm library.	1998-11-09 23:44:10 +00:00