luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
10,111 Commits 23 Branches 234 Tags 41 MiB
Commit Graph

1 Commits

Author SHA1 Message Date
Lars-Peter Clausen 37f7308f80 Add regression test for omitting trailing ports in ordered list connection 
Check that it is possible to omit trailing ports in a module ordered list
connection list.

Also check that an error is generated if too many ports are specified in a
ordered list connection.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2023-06-11 08:45:34 -07:00