ca9616dc7b
Better simple_expression parse rules.
2013-06-12 14:21:36 -07:00
24bd630cb2
Parse (to sorry messages) unbounded array definitions.
2013-06-12 14:21:36 -07:00
dca6171f5f
SV emit function ports in package subprograms.
2013-06-12 14:09:07 -07:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
d9fea802da
Function declarations in packages
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This is still basic. Definitions are still not done.
2013-06-12 14:09:07 -07:00
bad8ed39c1
Parse VHDL subprogram bodies and return statements.
2012-11-03 09:54:07 -07:00
5651e6e001
Improve error handling.
2012-11-02 19:30:12 -07:00
7fad717a1e
Redesign selected_name rule to better handle complex prefixes
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Prefixes of hierarchical names are complex and cannot be handled
by simple strings, to the rules must be reworked.
2012-09-03 16:00:10 -07:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
1749d10966
Fix some clang/bison compile warnings.
2012-08-06 15:49:11 -07:00
befff82655
Spelling fixes
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Comments and debug messages.
2012-07-27 18:25:32 -07:00
4748f0cb5e
Handle incomplete type declarations
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Use these in the package library to allow for arbitrary mixing
of type declaration and use. This makes writing libraries much
easier.
2012-05-22 17:31:27 -07:00
63b7fe059d
Reword concat to handle aggregate arguments.
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When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
a5458828cd
Some vhdl parser error handling.
2012-05-22 17:31:26 -07:00
7eb89c5548
Parse name prefix syntax for record member reference.
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When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
9b816f6478
Add support for nested when/else expressions.
2012-05-22 17:31:25 -07:00
1249b5dd32
Initial support for if_generate syntax.
2012-05-22 17:31:25 -07:00
9ed56a6354
Parse record types, and some new aggregate types.
2012-05-22 17:31:25 -07:00
aedbda5a75
Identifiers need to be deleted with delete[]
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This patch fixes a mismatch in the delete style.
2011-12-18 16:45:08 -08:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
98d928f6e0
Add support for VHDL for-generate
2011-10-30 17:10:19 -07:00
15da45f7cb
VHDL initialization expressions for signals.
2011-10-29 17:06:40 -07:00
4f98a6d181
Rewire VHDL addition expression parsing.
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The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
2be682f8a5
Support VHDL component instantiations with generics as Verilog parameters.
2011-10-23 17:08:48 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
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Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
a6f63b8a54
Parse generic clause in entity headers
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The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
6268db6e68
Handle simple type declarations.
2011-10-09 15:25:35 -07:00
271aaf6376
Parse enumeration type declarations.
2011-10-01 17:04:04 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
88cce86c63
Emit code for the to_unsigned() bulit-in function.
2011-09-18 19:31:28 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
4d445dc269
Fix parse of unnamed processes.
2011-09-18 09:37:11 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
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Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
6d28c989ce
Handle the basics of aggregate expressions
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This takes care of the parser support, and a shell of the
elaboration. Handle some special cases all the way through.
2011-09-03 17:11:55 -07:00
4464c5849b
Handle a few built-in functions internally.
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The "unsigned" and "std_logic_vector" functions are internal
functions and VHDL and can be handled internally in the code
generator.
2011-08-28 15:30:45 -07:00
7556a37859
Parse function calls, and detect type case expressions.
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Type cast expressions and some function calls are syntactically
identical to array element select, so we can only tell the difference
by looking up the name of the identifier being selected. If it is a
type name, then create an ExpCast instead of an ExpName object.
Also, parse and emit vector part selects.
2011-08-21 16:52:18 -07:00
f5220c54f1
Handle variables in process statements
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Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
f2629d53a2
Add VHDL support for named libraries
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Named libraries are similar to the work library, but they are not
written to implicitly, or imported implicitly. They are only brought
in by a "library" clause, the the packages within the library are
brought in by a "use" clause.
2011-07-30 15:04:07 -07:00
de356b03c8
Fix most of the cppcheck warnings in the vhdlpp directory.
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Mostly using size() vs empty() in the STL and a missing initialization.
2011-07-30 09:35:12 -07:00
836e61e878
Fix spacing issues in the code.
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Remove space at the end of line and space before tab since they serve
no purpose.
2011-07-30 09:33:28 -07:00
116d9f5f54
Merge branch 'master' into work7
2011-07-24 11:06:22 -07:00
50f7e1b69e
Add parser cleanup to vhdlpp
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This commit adds removal of global objects in
the execution of vhdlpp. This includes deleting
design entities and the global parse scope.
2011-07-24 10:03:03 -07:00
3764216a88
Use stl stack for for carrying scopes
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This is rather a cosmetic change. The patch changes
the container used for stack of scopes from std::list
to std::stack. It suits this particular application
a bit better.
2011-07-24 09:50:31 -07:00
21008f2ba9
Add missing or fix existing deletes in VHDL parser
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Thanks to valgrind analysis it turned out that
there were objects in the parser that were not being
deleted in a proper way. This patch fixes them all.
2011-07-24 09:47:41 -07:00
df8efed22b
Parse work library for imported packages
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When a "use" clause tries to pull a package from the work library,
put together a file name and try to find that package in the
work library directory. If found, parse the package file and
try again to find the package.
2011-07-23 10:07:20 -07:00
3ef1d01ad1
Rework parse/lex API to be reentrant
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Bison and Flex generate different interfaces for reentrant
parsers, so handle that different API. We need this change
because library support is going to reuse the parser to
read in library packages.
2011-07-22 20:49:57 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
b376115e15
Add parser support for VHDL's null statements
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Handle null statements in sequences of statements.
If a null is encountered, it is omitted and not
added to the list of statements.
2011-07-08 18:14:00 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
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Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
721f9d5d9b
Add String Expression to the VHDL parser
2011-07-08 18:05:06 -07:00
Stephen Williams
Arun Persaud
Cary R
Larry Doolittle
Pawel Szostek