Commit Graph

565 Commits

Author SHA1 Message Date
Pawel Szostek d747859a85 New compound VHDL symbols 2011-02-10 18:33:34 -08:00
Pawel Szostek ac28743eb0 New keywords to lexer added and typos corrected 2011-02-10 18:33:07 -08:00
Cary R 633ee85dc2 vhdlpp: update make clean and vpath, add cppcheck target
This patch updates the make clean target and modifies the vpath search to
match what is done in the main ivl Makefile since this one has the same
issues it does. It also adds a cppcheck target and removes the redundant
libmisc build target since the vpath already handles this.
2011-01-26 18:07:39 -08:00
Cary R a6c02f8cb9 Some vhdlpp git cleanup.
This patch adds vhdlpp/parse.output to .gitignore and moves all the
vhdlpp depend files to the local dep directory.
2011-01-26 18:07:27 -08:00
Stephen Williams 9229256f6f Fix identation style. 2011-01-26 17:44:58 -08:00
Pawel Szostek 7eddaaf5bf Entity parsing changed 2011-01-26 17:43:26 -08:00
Cary R 6bf7e88611 Fix build of ivl with files in libmisc and vhdlpp check issues.
This patch fixes the ivl build to find files in libmisc using vpath instead
of a separate target. The existing constructs caused build problems after
running a make clean. It also adds an empty checking target to vhdlpp.
2011-01-24 13:34:47 -08:00
Jared Casper ffca523d39 Fix vhdlpp Makefile for out-of-tree builds.
The INCLUDE_PATH in the vhdlpp Makefile was not including $(srcdir)
and $(srcdir)/.. when building outside of the source tree.
2011-01-24 13:33:41 -08:00
Stephen Williams ab8f623cea Add file/line information to entities and ports
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.

Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
2011-01-18 17:03:51 -08:00
Stephen Williams d72f7ea249 Save the type name if an InterfacePort object. 2011-01-18 17:03:51 -08:00
Stephen Williams 5a6d07ff9f Emit Verilog stubs for entities
The verilog includes the module declaration with correct ports
in the correct order. Get the port directions correct.
2011-01-18 17:03:51 -08:00
Stephen Williams 02820c9e34 Parse create entities with ports
Create entity objects from entity declarations in the source,
and populate them with ports.
2011-01-18 17:03:51 -08:00
Stephen Williams 05122d3e2c Add VHDLPP support to ivlpp program
The ivlpp program is a good place to detect that the source file
is VHDL, and pass the source file to the vhdlpp program. Do so
automatically.
2011-01-18 17:03:51 -08:00
Stephen Williams 04b239a5fb Flesh out VHDL parser engine.
Add enough rules to parse a simple VHDL program:
  Parse library and use clauses,
  Parse entity declarations, and
  Parse architecture bodies.

Add some parser infrastructure:
  Handle syntax errors with useful error messages,
  Include file name and line numbers in parse errors,
  Add some parser debug aids.
2011-01-18 17:03:51 -08:00
Stephen Williams 8cf1fd1820 Introduce shell of vhdlpp program.
Create the makefiles and configuration scripts to hold together
the vhdlpp front-end program. Create a shell main.
2011-01-18 17:03:51 -08:00