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415 Commits

Author SHA1 Message Date
steve e5f5f41515 Elaborate gate ranges. 1999-02-15 02:06:15 +00:00
steve 30a3953c85 Turn the NetESignal into a NetNode so 
that it can connect to the netlist.
 Implement the case statement.
 Convince t-vvm to output code for
 the case statement.
 1999-02-08 02:49:56 +00:00
steve 8bdd381cdf Parse and elaborate the Verilog CASE statement. 1999-02-03 04:20:11 +00:00
steve a7ad8985ac Carry some line info to the netlist, 
Dump line numbers for processes.
 Elaborate prints errors about port vector
 width mismatch
 Emit better handles null statements.
 1999-02-01 00:26:48 +00:00
steve fb439c78b9 Add the LineInfo class to carry the source file 
location of things. PGate, Statement and PProcess.

 elaborate handles module parameter mismatches,
 missing or incorrect lvalues for procedural
 assignment, and errors are propogated to the
 top of the elaboration call tree.

 Attach line numbers to processes, gates and
 assignment statements.
 1999-01-25 05:45:56 +00:00
steve 10b345bd16 Fully elaborate Sequential UDP behavior. 1998-12-14 02:01:34 +00:00
steve 9a73433759 Generate OBUF or IBUF attributes (and the gates 
to garry them) where a wire is a pad. This involved
 figuring out enough of the netlist to know when such
 was needed, and to generate new gates and signales
 to handle what's missing.
 1998-12-07 04:53:16 +00:00
steve ada45acb0c Add the nobufz function to eliminate bufz objects, 
Object links are marked with direction,
 constant propagation is more careful will wide links,
 Signal folding is aware of attributes, and
 the XNF target can dump UDP objects based on LCA
 attributes.
 1998-12-02 04:37:13 +00:00
steve e097c999d5 Elaborate UDP devices, 
Support UDP type attributes, and
 pass those attributes to nodes that
 are instantiated by elaboration,
 Put modules into a map instead of
 a simple list.
 1998-12-01 00:42:13 +00:00
steve af8d6fbf01 NetAssign handles lvalues as pin links 
instead of a signal pointer,
 Wire attributes added,
 Ability to parse UDP descriptions added,
 XNF generates EXT records for signals with
 the PAD attribute.
 1998-11-23 00:20:22 +00:00
steve 338240c37b Give anonymous modules a name when elaborated. 1998-11-21 19:19:44 +00:00
steve 6b2fa19429 Handle while loops. 1998-11-11 03:13:04 +00:00
steve ebad845fc3 Add procedural while loops, 
Parse procedural for loops,
 Add procedural wait statements,
 Add constant nodes,
 Add XNOR logic gate,
 Make vvm output look a bit prettier.
 1998-11-09 18:55:33 +00:00
steve b118634189 Handle procedural conditional, and some 
of the conditional expressions.

 Elaborate signals and identifiers differently,
 allowing the netlist to hold signal information.
 1998-11-07 17:05:05 +00:00
steve 3fb7a053be Introduce verilog to CVS. 1998-11-03 23:28:49 +00:00