07543315cf
vhdlpp: Stricter array type matching
...
Arrays type match if they have a common parent, instead of the
element type. Now (un)signed & std_logic_vector types do not match,
as it should be in VHDL.
2016-09-01 12:08:43 +02:00
fca2fff24e
vhdlpp: VTypeRange::type_match()
2016-03-07 09:54:28 +01:00
045d9e7117
vhdlpp: Improved type matching rules.
2016-03-07 09:54:28 +01:00
cfa038e75c
vhdlpp: VType::type_match() fixes.
2016-03-07 09:54:28 +01:00
95044d9ac7
vhdlpp: VType::type_match() checks definitions provided by VTypeDef.
2015-06-24 23:53:33 +02:00
e927960121
Implement subprogram bodies in package bodies.
2013-06-12 14:09:07 -07:00
Maciej Suminski
Stephen Williams