Nick Gasson
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fe80da362c
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Collect required packages as compilation progresses
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2008-06-03 19:14:47 +01:00 |
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Nick Gasson
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4211e651d0
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Stub file for processing statements
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2008-06-03 18:26:36 +01:00 |
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Nick Gasson
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9292a087e8
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Generate VHDL processes from Verilog processes
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2008-06-02 16:17:01 +01:00 |
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Nick Gasson
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8189c4ee43
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Generate VHDL entities and architectures for all module scopes
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2008-05-31 15:28:25 +01:00 |
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Nick Gasson
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e38494a10c
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Pretty-print VHDL output
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2008-05-29 16:24:16 +01:00 |
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Nick Gasson
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bfa2bfc8ae
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Makefile and autoconf changes to build VHDL code generator
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2008-05-28 17:17:39 +01:00 |