12d67bb9ae
Support SV [size] dimension for module and gate instances (issue #553 ).
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Also output a proper error message if multiple dimensions are supplied
instead of failing an assertion.
(cherry picked from commit dcc9b59f6d
2021-11-06 08:44:13 +00:00
c288487810
Clean up indentation.
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(cherry picked from commit dbf55da0f5
2021-11-06 08:40:58 +00:00
52b099feae
Remove "using namespace std" from compiler header files and fix the fallout.
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(cherry picked from commit ecbbb60fb6
2021-11-04 19:22:43 +00:00
19dc81a242
Fix detection of directly nested generate constructs.
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If a generate construct is enclosed in a begin-end pair, it can't
be directly nested (1364-2005 section 12.4.2).
(cherry picked from commit c34167b2c0
2021-08-04 15:40:20 +01:00
c690558cd6
output ports of type real are variables, not wires.
2020-12-29 22:22:20 -08:00
f0b3056bfc
Add support for an empty ';' in the description text
2020-11-20 21:42:47 -08:00
412195e660
Update module items to include just a ';'
2020-11-20 21:01:12 -08:00
50cd3b107c
Refactor task declaration parsing and fix warning for empty port list.
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1364-2005 and later allow a task declaration with an empty port list.
(cherry picked from commit 6880b39770
2020-10-03 09:38:46 +01:00
1064543d27
parse.y: Mark enum output ports always as IMPLICT_REG
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Unless explicitly declared a wire an enum output port is of variable type
and should be marked as IMPLICT_REG.
Currently this is only done when the base type of the enum is `logic`. But
it should be done for all enums regardless of their base type.
Without this change for example the following snippet
```
typedef enum {
A,
B
} E;
module M (
input E ei,
output E eo
);
always_comb eo = ei;
endmodule
```
fails with the following error message
test_enum.sv:11: error: eo is not a valid l-value in M.
test_enum.sv:8: : eo is declared here as wire.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2020-09-20 19:14:28 +02:00
6ff07c1074
Enable support for providing a queue maximum index
2020-07-17 01:32:53 -07:00
07256646a5
Merge pull request #334 from purdeaandrei/f_fix_portless_declarationless_functions
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Fix port-list-less declaration-less functions for SystemVerilog
2020-07-10 22:47:53 +01:00
c003bcc59a
Add support for <-> in constant and procedural contexts
2020-07-07 23:29:19 -07:00
018a649f59
A time variable defaults to unsigned, but can be declared as signed
2020-07-07 20:33:03 -07:00
a4d91c9023
Fix port-list-less declaration-less functions for SystemVerilog
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For functions without a port list in parantheses, declarations are optional in SystemVerilog.
This is true even in IEEE1800-2005, but not in IEEE1364-2005
2020-06-22 23:51:10 +03:00
8b85064341
Fix GitHub issue 310 - improve port declaration error message.
2020-02-15 12:02:15 +00:00
b1114760fc
Fix for compatibility with old C++ standard.
2020-02-02 09:25:05 +00:00
33b822d997
Add support for local genvar declaration in generate loops.
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As requested in GitHub issue #304 .
2020-01-31 20:29:22 +00:00
0023804777
Add support for increment/decrement operators in generate loop iteration.
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As requested in GitHub issue #303 .
2020-01-30 21:45:04 +00:00
9f712429c8
Fix elaboration of void functions with no arguments (GitHub issue #281 )
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N.B. commit 82c8a495#281 . It should have
referenced issue #280 .
2019-11-09 20:16:25 +00:00
06a60cac01
For SystemVerilog, support localparam in module parameter port lists.
2019-10-06 08:44:51 +01:00
befc91340c
Parse and elaborate unique and priority case statements
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The unique, unique0, and priority keywords can decorate case statements
to tell the run time (or synthesis) to do extra tests (or make extra
assumptions). These tests are not implemented in the vvp run time, but
now the decorations make it to the code generators.
2019-10-05 16:23:04 -07:00
c86dc285cc
Fix for br1004 - fully support class construction in variable initialisation.
2019-10-05 20:10:11 +01:00
05641f386f
Add -g option to only enable supported assertion statements.
2019-10-05 13:37:03 +01:00
455702810e
Add support for parsing (and ignoring) the other unsupported SV assertions.
2019-10-05 08:55:11 +01:00
9167a236d8
Support import statements in packages and in the unit scope.
2019-10-03 19:44:44 +01:00
17f0dd7e6e
Enable package imports in blocks.
2019-10-01 09:07:59 +01:00
c5c264400e
Add support for package scope resolution for named events.
2019-10-01 09:07:54 +01:00
12fe4f2bf3
Fix handling of wildcard-imported types.
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Don't add them to the explicit imports until they are referenced legally.
Stop searching when a matching name is found, even if it isn't a type name.
2019-10-01 09:07:48 +01:00
b0142a6406
Add support for named events in packages.
2019-10-01 09:07:39 +01:00
f69eccf903
Merge remote-tracking branch 'origin/master' into package-imports-rework
2019-10-01 09:06:15 +01:00
80478db6cc
Support typedefs in class definitions.
2019-09-30 08:07:56 -07:00
50d71c8512
Support for enumerations in classes.
2019-09-29 18:27:27 -07:00
03c4c63df1
Fix file/line reported for duplicate named blocks.
2019-09-27 22:19:30 +01:00
d3bced57cc
Correctly handle explicit and wildcard package imports.
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Explicit imports should always conflict with local declarations using
the same name. Wildcard imports only conflict if they are referenced
before a local declaration with the same name.
This also unifies the detection of identifier conflicts.
2019-09-27 22:19:30 +01:00
823a508d6b
Implement SV immediate assertions.
2019-09-20 21:30:43 +01:00
02ee1c65d0
Support dynamic array initialisation in variable declarations.
2019-09-16 20:35:27 +01:00
832adc5c74
Improve handling of invalid packed and unpacked dimensions.
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As reported on iverilog-devel on 2018-10-12, a dimension size of zero
could case the compiler to go into an infinite loop. Further tests
showed that unsized or queue dimensions entered as packed dimensions
would cause the compiler to crash.
2019-09-14 09:10:52 +01:00
e97883b1db
Fix for br1015 : assertion failure when task/function port is an array.
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This is an error for Verilog and not yet supported for SystemVerilog.
2019-08-02 15:34:31 +01:00
acdd78db7d
Merge branch 'primitive_redefinition' of https://github.com/thasti/iverilog
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- make primitive redefinition a warning, not an error
- make edge-sensitive ifnone a warning, not an error
This allows Icarus to be used to simulate designs using third-party
cell libraries that contain such things.
2019-07-23 21:53:57 +01:00
4055752959
Fix white space errors.
2019-07-23 10:08:37 +01:00
b619b43ddd
Added support for parsing attributes on function calls
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-05 16:42:52 +02:00
e6fa2625a4
Added support for parsing attributes on port connections
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-06-05 16:28:45 +02:00
c6cf83a13a
make ifnone-error a warning
2019-05-17 16:17:08 +02:00
7cd078e7ab
Restrict cast type to what's allowed by the IEEE standard.
2018-12-15 12:26:33 +00:00
69d80839a5
Improved check for missing task/function port direction.
2018-02-21 20:07:13 +00:00
6b1b402a79
Fix for br1027: incorrect inference of task/function port direction.
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In traditional Verilog, each task_port_item must have an explicit port
direction.
In SystemVerilog, if the port direction is not specified, it should be
inherited from the preceding task_port_item for that task/function, and
only the first task_port_item should infer the direction to be 'input'.
2018-02-20 20:59:26 +00:00
585a0232cb
Add preliminary support for always_comb, always_ff and always_latch
2017-11-20 07:50:05 -08:00
3fc9ad2db0
Add support for the wild compare operators ==? and !=?
2017-11-17 19:32:50 -08:00
0f2ce7da45
Fix for GitHub issue #172 : don't use %precedence in parser.
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Older versions of bison don't support this. Use %nonassoc instead.
2017-11-08 20:20:04 +00:00
f83e01847a
Fix a couple of minor bugs in the timescale parsing rework.
2017-11-06 00:37:56 +00:00
Martin Whitaker
Stephen Williams
Cary R
Lars-Peter Clausen
Purdea Andrei
Stephen Williams
Maciej Kurc
Stefan Biereigel