cc9b182eb6
vhdlpp: Procedure calls.
2015-06-24 23:53:32 +02:00
169228ad0f
vhdlpp: Refactored the way of handling standard VHDL library functions.
2015-06-24 23:53:31 +02:00
29ddd5208f
vhdlpp: 'wait on' and 'wait until' statements.
2015-06-08 18:42:52 +02:00
68f8007fc4
vhdlpp: 'wait for' statement.
2015-06-08 18:42:52 +02:00
cfa43c7742
vhdlpp: Support for reports & asserts.
2015-04-23 11:58:40 +02:00
19ff6a434b
vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances).
2015-02-05 12:00:25 +01:00
5b7b980ead
vhdlpp: Support for multiple choices in case statements.
2015-02-05 12:00:25 +01:00
25c3798248
vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture.
2015-02-04 16:57:43 +01:00
962330f20a
vhdlpp: Functions support unbounded vectors as return type and parameters.
2015-02-04 16:57:43 +01:00
f5aafc32f9
updated FSF-address
2012-08-29 10:12:10 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
f5220c54f1
Handle variables in process statements
...
Parse variables declared in the declaration section of process
statements, and support variable assignment statements.
2011-08-17 20:19:15 -07:00
72769146ee
Remove all the user code compilation warnings
...
Remove all the compilation warnings that are from user changeable code.
There are still some warnings related to the flex generated lexor code.
2011-07-30 09:37:14 -07:00
60deb775ca
Add support for VHDL's loop statements
2011-07-12 19:20:04 -07:00
ad31eaaea8
Add parser support for VHDL's procedure call
...
Parse procedure calls and put them into
abstract syntax tree. Elaboration and emission
still has to be done.
2011-07-08 18:10:30 -07:00
d14f60f28a
Elaborate and emit vhdl elsif sections.
...
The IfStatement contains a list of elsif sections that need
to be elaborated/emitted in the middle of the true and false
clauses.
2011-06-22 18:13:40 -07:00
cab974c0c2
vhdl sequential l-values cause variables to be reg vs. net.
...
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
2011-06-12 15:38:03 -07:00
22ab8e4a76
Elaboration of r-value expressions
...
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
2011-05-30 19:17:40 -07:00
a53082176d
Arrange for ports used as l-values to be declared as "reg".
...
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
2011-05-15 16:17:51 -07:00
Maciej Suminski
Arun Persaud
Stephen Williams
Cary R
Pawel Szostek