Commit Graph

128 Commits

Author SHA1 Message Date
Stephen Williams 69c10c4722 Handle case generate under a conditional generate that is unnamed.
When a conditional statement is unnamed, it doesn't create a scope
and we get into "direct" generate scheme elaboration. This direct
elaboration needs to handle case generate schemes.
2012-04-30 16:00:25 -07:00
Stephen Williams 13348ba7ac Ranges are ranges, not expression lists.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)

Conflicts:

	PTask.h
	elab_scope.cc
	elab_sig.cc
	parse.y
	pform.cc
	pform.h
	pform_types.h

Signed-off-by: Stephen Williams <steve@icarus.com>
2012-04-10 14:29:28 -07:00
Stephen Williams 0e01dcf2b9 Miscellaneous SystemVerilog syntax.
... and sorry messages.
2012-03-04 19:33:16 -08:00
Stephen Williams f749867369 Rework rules for variable_dimensions, and support more syntax. 2012-03-02 18:34:43 -08:00
Stephen Williams dd3a7411cd Parse SystemVerilog ref ports. 2012-02-25 10:19:48 -08:00
Stephen Williams 3e4f8b625f Get packed signals working through to simulation in some situations.
When dynamic indexing of early dimensions is not needed, we can get
pretty far with getting packed arrays to work.
2012-02-10 17:17:59 -08:00
Stephen Williams e5c49022b4 The NetNet class carries multiple packed dimensions. 2012-02-06 17:47:53 -08:00
Stephen Williams ae11010707 Evaluate packed ranges for signals. 2012-02-05 17:41:11 -08:00
Stephen Williams 950e7a632c Parse multi-dimension packed arrays to pform. 2012-02-04 16:19:27 -08:00
Stephen Williams 5d35ad8a0d Support uwire resolved writes to non-overlapping parts
The individual bits of an unresolved wire may be assigned in
different continuous assignments without generating an error.
2012-02-02 16:18:50 -08:00
Stephen Williams 3a2866b57c Handle members of packed struct as implicit part selects.
Packed struct members are synonymous with part selects, but in a
much more convenient form, so get them to work that way.
2012-02-02 16:18:49 -08:00
Stephen Williams d362c8dba0 Parse support for struct variables. 2012-02-02 16:18:49 -08:00
Stephen Williams f0bf64271b SystemVerilog has more lax rules for function declarations.
Allow empty parameter lists
Allow lists of statements instead of simple statements.
2011-09-17 12:10:05 -07:00
Cary R 4006bb2336 Some more cppcheck cleanup.
This patch cleans up most of the warnings in the main (ivl) directory.
2011-04-20 18:09:11 -07:00
Martin Whitaker 1e9f9685cc First step towards supporting constant user functions.
This patch allows the compiler to perform early elaboration
of functions if they are encountered in expressions that are
elaborated before the function would normally be elaborated.
This makes the function available for constant evaluation.
Suitable error messages are generated if a function that is
used in a constant expression is not a valid constant function.
2011-04-13 18:40:19 -07:00
Martin Whitaker 93067149f1 Rework of constant expression error reporting.
This patch changes the method used to signal that a constant expression
is being elaborated from flags stored in global variables to flags
passed down the call chain. It also generates more informative error
messages when variable references are found in a constant expression.
2011-04-06 18:50:53 -07:00
Cary R 2a0d33608f Fix spacing problems.
This patch fixes spacing problems in the source code, space/tab at
the end of line and space before tab.
2011-03-03 11:21:31 -08:00
Martin Whitaker 312b4da46f Expression width rework.
This patch is a major rework of expression elaboration and
evaluation in the compiler, aimed at better compliance with
the IEEE standard.
2011-03-01 18:13:26 -08:00
Martin Whitaker 275dde7712 Rework of parameter expression elaboration.
The compiler currently performs parameter expression elaboration before
performing parameter overrides. This means that the information needed
to correctly determine the expression type and width may not be available
at the time elaboration is performed. This patch reworks the code to
delay elaboration until after all overrides have been performed. It
also provides a new -g option that controls how the width of parameter
expressions is calculated when the parameter itself is unsized.
2010-12-06 14:56:50 -08:00
Stephen Williams 16e1570737 Merge branch 'master' into work2
Conflicts:
	elab_scope.cc
	net_nex_input.cc
	t-dll-api.cc
	vvp/parse.y
2010-11-28 08:38:40 -08:00
Cary R 13b8dcc0b1 Fail if the user defines a real variable as a vector.
Using reg real [1:0] var you can define a real variable with a
range. This was crashing the run time. This patch catches this
in the compiler and prints an appropriate message.
2010-11-25 09:27:05 -08:00
Stephen Williams 27dfdf99dd Enumeration element values can be expressions
Allow more complex enumeration expressions, which means putting
off the evaluation of the expression values until elaboration.
2010-11-12 18:47:06 -08:00
Stephen Williams cd6c6c7a70 Get the netenum_t base type data from the pform.
The pform propagates the parsed enum base type information
to the elaborator so that the base type can be fully elaborated.
This is necessary to get the types of the enumeration literals
correct.
2010-11-03 20:11:19 -07:00
Stephen Williams 5b5a6b05b7 Test type correctness during elaboration.
Create a netenum_t class to carry the enumeration type in the
netlist.h structures, and use that type to check enumerations
with assignments.
2010-11-02 20:16:42 -07:00
Cary R bb5ca97f2d Fix some -Wextra warnings and some other bug fixes/enhancements.
This patch covers more than it should. It removes many of the -Wextra
warnings in the main ivl directory. It also makes some minor code
improvements, adds support for constant logicals in eval_tree (&&/||),
adds support for correctly sign extending === and !==, it starts to
standardize the eval_tree debug messages and fixes a strength bug
in the target interface (found with -Wextra). The rest of the warnings
and eval_tree() rework will need to come as a second patch.
2010-11-02 11:05:11 -07:00
Cary R 225ca1e205 Change iterators to use prefix ++ since it is more efficient.
This patch changes all the iterator code to use a prefix ++ instead
of postfix since it is more efficient (no need for a temporary). It
is likely that the compiler could optimize this away, but lets make
it efficient from the start.
2010-11-02 10:43:16 -07:00
Stephen Williams cced1e771b Remove some uses of the svector template.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
2010-10-25 19:36:44 -07:00
Stephen Williams af6fd66648 Tasks functions with atom2 arguments.
Parse 2-value atoms as arguments to functions and tasks.
2010-10-10 10:06:27 -07:00
Cary R e0001de3ba Add support for bit <-> real conversion for output ports.
This patch adds support for converting bit based ports to real signals.
You can only do this for single instances. Arrayed instance would
create multiple instances driving the same real signal.

Any real port can be connected to a bit based signal. The only limitation
is that the signal width must be an integer multiple of the instance
count since all the real conversions must have the same width.

Also add an error message for an arrayed instance with real to real
output connections. Again multiple drivers.

This patch also adds errors for inout real and bit based inout ports
driving a real signal. There is no logical way to deal with the full
capabilities of inout and real ports/signals. So for now they are not
allowed.
2010-04-27 12:12:04 -07:00
Stephen Williams 79f8b8fcfd Remove Link::strength_t and PGate::strength_t types.
These types are useless repetition of the ivl_drive_t type.
This is also another chapter in the series to push ivl_target
generation further upstream.
2010-03-16 15:16:53 -07:00
Martin Whitaker f95593716f Fix for pr2924354.
Creation of implicit nets requires knowledge of whether an identifier
has been declared before it is used. Currently implicit nets are
created during elaboration, but by this stage the order of declaration
and use is not known. This patch moves the creation of implicit nets
into the parser stage.
2010-01-23 09:10:00 -08:00
Cary R 872962ef18 Fix subtle bug in scope checking.
This check looks to be defined to check the child scope not the
top level scope.
2009-09-03 16:58:36 -07:00
Cary R 72a98e85cb Add full genvar support and name space checking.
This patch adds genvars to the elaboration process. It adds checks
that a genvar is defined for a generate loop and that a genvar does
not conflict with any other items in its name space.
2009-07-28 20:04:54 -07:00
Cary R 192522b3d8 Check for name space collisions.
This patch adds code to check for most of the name space
collisions. genvars are not checked correctly since they
are not completely implemented.
2009-04-27 17:24:36 -07:00
Cary R b1dd0b1f6d It is an error to select part of a scalar value.
In 1364-2005 it is an explicit error to take the select of a scalar
or real value. We added the checks for real a while ago. This patch
adds the functionality for scalar values. In the future we may want
to push the scalar property to the run time.
2009-04-17 18:18:22 -07:00
Larry Doolittle 3a18bda8ee Don't make useless arrays of nexa
When a pin array is virtual, dll_target::signal() doesn't need
to make a corresponding set of stub nexa.

This patch includes new detection of oversized arrays, configurable
with the ARRAY_SIZE_LIMIT flag.  This limit only applies to devirtualized
arrays; virtual arrays are only limited by your architecture's
unsigned int type.

The concept and earlier versions of this patch have been successfully
stress-tested by multiple people.  This one causes no testsuite
regressions on my machine.

Closes: pr2023076
2009-03-11 10:30:37 -07:00
Cary R d143597996 Add better constant user functions are not supported messages.
This patch adds messages in various places to warn that constant
user functions are not supported. It uses a global variable to
indicate when we are in a constant context. This is a bit of a
kludge, but works well without needing to change a bunch of code.

It is interesting to note that ports are elaborated late enough
that if we had the constant function evaluation code they would
evaluate correctly. This also applies to the function return
range, the concatenation repeat, specparams and initial values.

Signal definitions are early enough that elaboration is what is
failing because the function body is not available (has not been
elaborated). The same thing applies to both parameters and
localparms.
2009-02-27 21:29:54 -08:00
Stephen Williams bd754b24f4 Support direct nesting of conditional generate schemes.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
2008-11-27 19:45:22 -08:00
Stephen Williams 90bfebd578 During test_width is not the time to assert on no_type
unary expressions that have problems should not assert in the
test_width method. Instead, let the error propagate back and be
handled during expression elaboration. This found a few places
where expression widths/types weren't probed before elaboration.
2008-11-26 15:37:38 -08:00
Stephen Williams 5e174f54ee Elaborate signals in generated named blocks.
Named blocks create scopes, and generated named blocks' scopes can
have signals declared in them. So the elaborate_sig for the generate
scheme needs to call the elaborate_sig for the processes as well as
the obvious gates and tasks/functions.
2008-11-18 20:10:10 -08:00
Stephen Williams ddb2c60701 Remove svector class from Module.h
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
2008-11-02 20:08:38 -08:00
Stephen Williams f4687757f1 Bring signal discipline all the way to the ivl_target API.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
2008-11-02 08:10:41 -08:00
Martin Whitaker 18edf2f15f Rework of automatic task/function support.
This patch splits any VVP net functor that needs to access both
statically and automatically allocated state into two sub-classes,
one for handling operations on statically allocated state, the
other for handling operations on automatically allocated state.
This undoes the increase in run-time memory use introduced when
automatic task/function support was first introduced.

This patch also fixes various issues with event handling in automatic
scopes. Event expressions in automatic scopes may now reference either
statically or automatically allocated variables or arrays, or part
selects or word selects thereof. More complex expressions (e.g.
containing arithmetic or logical operators, function calls, etc.) are
not currently supported.

This patch introduces some error checking for language constructs
that may not reference automatically allocated variables. Further
error checking will follow in a subsequent patch.
2008-10-29 20:43:00 -07:00
Martin Whitaker 082e06edb0 Remove checks for constant expressions from the parser.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.

This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
2008-10-09 11:11:32 -07:00
Larry Doolittle 66949122cf Non-controversial whitespace cleanup
Nothing to do with tab width!  Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings.  No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.

Low priority, simple entropy reduction.  Please apply
unless it deletes some steganographic content you want
to keep.
2008-09-04 21:31:30 -07:00
Stephen Williams 1ca8241b88 Merge branch 'master' into verilog-ams 2008-08-29 19:03:34 -07:00
Cary R f835c7569e Check for a possible corrupt function definition and return.
If a function definition has no ports and no return type it is
assumed to be a bad definition so we don't check it further.
2008-08-09 18:46:18 -07:00
Cary R 2a389a9abe Display signal array size when using -delaborate.
This patch modifies one of the debug_elaborate messages to display
the array information when needed.
2008-08-09 18:10:59 -07:00
Stephen Williams b292a5fc05 Create a branch object to be the argument to the access function.
The NetBranch object is connected, but not like an object, so the
NetPins object base class is factored out from NetObj to handle the
connectivity, and the NetBranch class uses the NetPins to connect a
branch.

Also, account for the fact that nets with a discipline are by default
real-valued.
2008-08-04 20:54:05 -07:00
Stephen Williams 2f3627cd6d Allow generate schemes to generate task/function definitions.
Generating task/function definitions involves getting the functions
to put themselves into the generate scheme instead of the module,
and getting elaboration to elaborate those definitions in the
generate scheme.
2008-06-18 21:54:58 -07:00