Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
These go into the architecture/block of their scope and will be
used by component instantiations to make sure the bindings are
correct and complete.
Also handle signal declarations. The elaborator will use these
to generate module local variables that are used by the architecture.
Include the compiler infrastructure to vhdlpp for collecting the
file and line information and attaching it to entities and ports.
Make the parser store the file name during parse.
Create a libmisc library where I can put source files that are
used by multiple programs within the source tree.
Maciej Suminski
Arun Persaud
Stephen Williams
Cary R
Pawel Szostek