Commit Graph

33 Commits

Author SHA1 Message Date
Cary R fbe42f13e2 Update tgt- directories with cppcheck suggested fixes 2021-01-02 13:31:26 -08:00
Martin Whitaker 4ea18196c8 Fix deprecated dynamic exception specification warnings. 2018-10-06 21:02:41 +01:00
Stephen Williams ec49f10e2d Revert bad merge from vhdl branch 2010-10-02 11:02:27 -07:00
Nick Gasson e6846ea3a7 Improve memory management in VHDL target
Previously the VHDL code generator managed memory for
the AST objects by requiring that each AST element be
responsible for deleting its children. The disadvantages
of this are that it's quite easy to accidentally leak
memory by forgetting to delete a child, and no AST pointers
may be shared by multiple parents (or we'd end up with
double-deletes) -- this results in unnecessary copies of
objects being made.

There's no real need for fine-grained memory management of
AST objects since once they're allocated they tend to
persist until the code generator is about to terminate, when
they should all be freed.

This patch provides a custom new/delete operator for
vhdl_element which logs the vhdl_element objects allocated
in a std::vector (after calling the default operator new).
Once the code generator is finished a single free_all_objects
call deletes all the AST objects in one go. The custom delete
operator is required so that we can still explicitly deallocate
vhdl_element objects before the code generator completes.

There are also some allocation statistics printed at the end
when -pdebug=1 is specified.
2009-01-18 16:42:10 -08:00
Nick Gasson 38de6ebf3a Compress support function definitions a bit 2008-07-19 21:04:52 +01:00
Nick Gasson ef89a760d6 Add vhdl_element::print method for debugging 2008-07-01 10:44:20 +01:00
Nick Gasson 050aa277ae Make vhdl_element::emit a little more generic 2008-07-01 10:37:22 +01:00
Nick Gasson 1d28b935e8 Split vhdl_element.cc into multiple files 2008-06-08 13:27:48 +01:00
Nick Gasson 4b4a1c6cac Tidy up type casting 2008-06-08 12:55:18 +01:00
Nick Gasson 110a1b2ac7 Replace type classes with enumeration 2008-06-08 12:48:56 +01:00
Nick Gasson fbf85398da Support converting bit strings to std_logic 2008-06-07 16:19:10 +01:00
Nick Gasson c064ae6bc3 Generate VHDL for non-blocking assignments 2008-06-07 14:54:00 +01:00
Nick Gasson 39228f3495 VHDL AST element for non-blocking assignment 2008-06-07 14:31:33 +01:00
Nick Gasson 12e2237131 Add Type'Image cast to $display parameters 2008-06-07 14:21:50 +01:00
Nick Gasson 066a9b7a61 Add AST element for function call expressions 2008-06-07 13:29:27 +01:00
Nick Gasson cdb180e1d4 Associate a type with each VHDL expression node 2008-06-07 13:23:21 +01:00
Nick Gasson a8ecce7421 Make sure all declarations have a type 2008-06-07 12:15:46 +01:00
Nick Gasson 96cf190720 Generate signals and sensitivity list for @(..) statement 2008-06-06 17:56:52 +01:00
Nick Gasson 373832ba22 Specify correct sensitivity list 2008-06-06 17:36:15 +01:00
Nick Gasson d36bbec5b5 Generate VHDL for no-op statements 2008-06-05 13:16:35 +01:00
Nick Gasson 6e448da90d Emit Write() calls for parameters of $display 2008-06-04 15:19:44 +01:00
Nick Gasson 4bf2e1669d Store packages required with entity rather than globally
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
Nick Gasson dd30c1b39d Support procedure call generation for $display 2008-06-04 13:27:42 +01:00
Nick Gasson 94006cb44c Working on code generation for $display task 2008-06-03 19:46:10 +01:00
Nick Gasson 2e6ec91ce0 Scalar types 2008-06-03 19:20:45 +01:00
Nick Gasson a09b4e3b92 Initial process have wait at the end
(do it properly this time rather than a hack :-)
2008-06-03 17:39:24 +01:00
Nick Gasson 041925c123 Component instantiation to replicate Verilog hierarchy 2008-06-02 17:45:58 +01:00
Nick Gasson 9292a087e8 Generate VHDL processes from Verilog processes 2008-06-02 16:17:01 +01:00
Nick Gasson fef0fd82ff Comments 2008-06-02 00:12:47 +01:00
Nick Gasson 5cbd587833 Clean up generated objects 2008-05-31 16:08:57 +01:00
Nick Gasson 8189c4ee43 Generate VHDL entities and architectures for all module scopes 2008-05-31 15:28:25 +01:00
Nick Gasson e38494a10c Pretty-print VHDL output 2008-05-29 16:24:16 +01:00
Nick Gasson bfa2bfc8ae Makefile and autoconf changes to build VHDL code generator 2008-05-28 17:17:39 +01:00