`named_pexpr_t` is a typedef for `named<PExpr*>`. There are a few places
where `named<PExpr*>` is used directly. Replace those with `named_pexpr_t`
for consistency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
The custom `svector` class is essentially a subset of `std::vector`. There
is no inherent advantage to using `svector`. Both have the same memory
footprint.
`svector` was designed to be of static size, but there are a few places in
the parser where it has to grow at runtime. Handling this becomes a bit
easier by switching to `std::vector` since it is possible to use its
methods which take care of resizing the vector.
This also allows to remove the unused parameter of the `lgate` struct
constructor, which was only needed for compatibility with `svector`.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
(* my_fancy_attribute *)
foobar1 foobar (clk(clk), rst(rst) ...);
- Modifies PGModule to hold the attribute map (can be verified with pform_dump)
- pform_make_modgate(s) bind the attributes from the parser to the above map
- The attributes from PGModule are inserted into the NetScope of that module
PGModule::elaborate_scope_mod_instances_
- Currently these attributes automatically make it into netlist
- These attributes are accessible via ivl_scope_attr_cnt and ivl_scope_attr_val
from ivl_target.h
An important advantage of program blocks is its ability to nest
within a module. This winds up also allowing modules to nest, which
is legal but presumably less used feature.
The compiler was handling bi-directional pass switches using the default
case for primitive gates, where the first port is treated as an output
and the remaining ports are treated as inputs. This patch adds a special
case for pass switches, so that the first two ports are treated as
bi-directional.
For now Icarus doesn't support a UDP instantiation with a range.
Instead of generating a warning about the port count being wrong
this patch adds code to calculate the range and print a message
if a range greater than one is found.
This patch covers more than it should. It removes many of the -Wextra
warnings in the main ivl directory. It also makes some minor code
improvements, adds support for constant logicals in eval_tree (&&/||),
adds support for correctly sign extending === and !==, it starts to
standardize the eval_tree debug messages and fixes a strength bug
in the target interface (found with -Wextra). The rest of the warnings
and eval_tree() rework will need to come as a second patch.
I'm adding more uses of the make_range_from_width function, so
it seems like time to get rid of its use of the svector template.
This thread led to a lot of other uses of svector that had to
also be removed.
This patch adds checks that the delay count is correct for the
various gates and adds support for a missing variable decay
time. For this case the decay time is the minimum of the rise
and fall times. This is denoted by setting the decay variable
to 0 in the vvp file. vvp notes this and sets an ignore decay
time property in the base delay. This turns off the ability
to set the decay time and the minimum delay calculation will
also update the decay time.
Later passes need the intermediate results for width and size so that
some special cases, were self-determined arguments occur, can be
processed properly during elaboration. This can be especially tricky
and interesting for ternary expressions.
This patch pads inputs and output ports correctly when the port
and the port expression have different widths. It does not fix
inout ports.
It also sets the file and line number information in the unsigned
pad_to_width() routine.
Logic gates usually have one output and several inputs, but a few
have multiple outputs and one input. Since the NetNode objects have
only a single output, handle the case by creating multiple NetNode
objects, one for each output.
When we detect that a module instance is an array of instances, delay
the elaboration of the array until after the first defparam processing
is complete. This allows for defparam statements to control the
instantiation of module instance arrays.
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <steve@icarus.com>
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
I now generate the scopes and notice the parameters
in a separate pass over the pform. Once the scopes
are generated, I can process overrides and evalutate
paremeters before elaboration begins.
Cary R
Lars-Peter Clausen
Martin Whitaker
Vamsi Vytla
Stephen Williams
Arun Persaud
steve