Add regression tests for type identifiers as implicit nets

Check that a type identifier is rejected rather than declared as an implicit
net when used in a continuous assignment, primitive terminal, or ordered
module port connection. Cover local typedefs, explicit imports, and activated
wildcard imports.

These contexts are currently rejected by the grammar. Keep the tests in place
when type and hierarchy identifiers start using the same parser path.

Signed-off-by: Lars-Peter Clausen <[email protected]>

ivtest/gold/sv_type_identifier_implicit_assign_fail-iverilog-stderr.gold

@@ -0,0 +1,2 @@
+ivltests/sv_type_identifier_implicit_assign_fail.v:6: syntax error
+ivltests/sv_type_identifier_implicit_assign_fail.v:6: error: Syntax error in left side of continuous assignment.

ivtest/gold/sv_type_identifier_implicit_gate_fail-iverilog-stderr.gold

@@ -0,0 +1,2 @@
+ivltests/sv_type_identifier_implicit_gate_fail.v:10: syntax error
+ivltests/sv_type_identifier_implicit_gate_fail.v:10: error: Invalid module item.

ivtest/gold/sv_type_identifier_implicit_port_fail-iverilog-stderr.gold

@@ -0,0 +1,2 @@
+ivltests/sv_type_identifier_implicit_port_fail.v:12: syntax error
+ivltests/sv_type_identifier_implicit_port_fail.v:12: error: Syntax error in instance port expression(s).

ivtest/ivltests/sv_type_identifier_implicit_assign_fail.v

@@ -0,0 +1,7 @@
+// Check that a type identifier does not become an implicit net on the left
+// side of a continuous assignment.
+
+module test;
+  typedef logic value;
+  assign value = 1'b1;
+endmodule

ivtest/ivltests/sv_type_identifier_implicit_gate_fail.v

@@ -0,0 +1,11 @@
+// Check that a type identifier does not become an implicit primitive terminal.
+
+package p;
+  typedef logic value;
+endpackage
+
+module test;
+  import p::value;
+  wire result;
+  buf (result, value);
+endmodule

ivtest/ivltests/sv_type_identifier_implicit_port_fail.v

@@ -0,0 +1,13 @@
+// Check that a type identifier does not become an implicit module connection.
+
+package p;
+  typedef logic value;
+endpackage
+
+module M(input wire data);
+endmodule
+
+module test;
+  import p::*;
+  M i_m(value);
+endmodule

ivtest/regress-vvp.list

@@ -523,6 +523,9 @@ sv_type_identifier_function_name	vvp_tests/sv_type_identifier_function_name.json
 sv_type_identifier_generate_label_name	vvp_tests/sv_type_identifier_generate_label_name.json
 sv_type_identifier_genvar_name	vvp_tests/sv_type_identifier_genvar_name.json
 sv_type_identifier_hier_fail	vvp_tests/sv_type_identifier_hier_fail.json
+sv_type_identifier_implicit_assign_fail	vvp_tests/sv_type_identifier_implicit_assign_fail.json
+sv_type_identifier_implicit_gate_fail	vvp_tests/sv_type_identifier_implicit_gate_fail.json
+sv_type_identifier_implicit_port_fail	vvp_tests/sv_type_identifier_implicit_port_fail.json
 sv_type_identifier_inherited_property_shadow	vvp_tests/sv_type_identifier_inherited_property_shadow.json
 sv_type_identifier_modport_name	vvp_tests/sv_type_identifier_modport_name.json
 sv_type_identifier_modport_named_port	vvp_tests/sv_type_identifier_modport_named_port.json

ivtest/vvp_tests/sv_type_identifier_implicit_assign_fail.json

@@ -0,0 +1,6 @@
+{
+    "type"          : "CE",
+    "source"        : "sv_type_identifier_implicit_assign_fail.v",
+    "gold"          : "sv_type_identifier_implicit_assign_fail",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_implicit_gate_fail.json

@@ -0,0 +1,6 @@
+{
+    "type"          : "CE",
+    "source"        : "sv_type_identifier_implicit_gate_fail.v",
+    "gold"          : "sv_type_identifier_implicit_gate_fail",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_implicit_port_fail.json

@@ -0,0 +1,6 @@
+{
+    "type"          : "CE",
+    "source"        : "sv_type_identifier_implicit_port_fail.v",
+    "gold"          : "sv_type_identifier_implicit_port_fail",
+    "iverilog-args" : [ "-g2005-sv" ]
+}